Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based upon an application filed in JAPAN on 09/26/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/22/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7-11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over US20120299011A1; Hikita et al.; (hereinafter “Hikita”) in view of US20140367742A1; John Kevin Twynam; (hereinafter “Twynam”).
Regarding Claim 1, Hikita teaches a nitride semiconductor device ([0008], transistor with nitride semiconductors), comprising:
an electron transit layer composed of a nitride semiconductor (#103, Figure 1, GaN layer);
an electron supply layer (#104, AlGaN layer) formed on the electron transit layer (#103) and composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer ([0008], second nitride layer #104 has larger band gap than the first nitride layer #103);
a gate layer (#105-106, GaN layer) formed on the electron supply layer (#104) and composed of a nitride semiconductor including an acceptor impurity ([0032], #105 contains a p-type impurity);
a gate electrode (#111, gate electrode) formed on the gate layer (#105-106); and
a source electrode (#109, source electrode) and a drain electrode (#110, drain electrode) that are formed on the electron supply layer (#104),
wherein the gate layer includes an upper surface in contact with the gate electrode (#105-106 has upper surface contacting #111).
Hikita does not explicitly teach the upper surface is a Ga-polar surface.
However, Twynam teaches a nitride semiconductor device (Figure 1), wherein the upper surface is a Ga-polar surface (Figure 1, upper surface of AlGaN or GaN layer, [0086], #13 has a Ga polarity according to [0042]).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Hikita with the teaching of Twynam, as it would be simply a substitution of one known element (nitride layer of Hikita) for another (nitride layer of Twynam) in comparable devices to obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 7, Hikita in view of Twynam teaches the nitride semiconductor device as described in claim 1.
Hikita does not explicitly teach the gate layer is composed of Ga-polar GaN.
However, Twynam teaches the gate layer (#13, Figure 1, AlGaN or GaN layer, [0086]) is composed of Ga-polar GaN ([0042], #13 has a Ga polarity).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Hikita with the teaching of Twynam for the reason set forth in the rejection of claim 1.
obtain predictable results. See MPEP 2143(I)(B).
Regarding Claim 9, Hikita in view of Twynam teaches the nitride semiconductor device as described in claim 1, wherein Hikita further teaches the upper surface of the gate layer (Figure 1, nitride layer #106) forms a Schottky junction with the gate electrode (gate electrode #111, [0038]).
Regarding Claim 10, Hikita in view of Twynam teaches the nitride semiconductor device as described in claim 1, wherein Hikita further teaches:
a passivation layer (#108, Figure 1, SiN film) covering the electron supply layer (#104, AlGaN layer), the gate layer (#105-106, GaN layer), and the gate electrode (#111 or #1411, Figure 14, gate electrode) and including a first opening and a second opening (Figure 1, source/drain electrodes #109/#110 dispose in openings of #108), wherein
the source electrode (#109) is in contact with the electron supply layer (#104) through the first opening,
the drain electrode (#110) is in contact with the electron supply layer (#104) through the second opening, and
the gate layer is arranged between the first opening and the second opening (#105-106 disposes between #109 and #110).
Regarding Claim 11, Hikita in view of Twynam teaches the nitride semiconductor device as described in claim 1, wherein Hikita further teaches the electron transit layer is composed of GaN (nitride layer #103 comprises of GaN), and the electron supply layer is composed of AlxGa1-xN, where 0.1<x<0.3 (nitride layer #104 comprise of Al0.25Ga0.75N).
Regarding Claim 13, Hikita in view of Twynam teaches the nitride semiconductor device as described in claim 1, wherein Hikita further teaches
a semiconductor substrate (#101, Figure 1, substrate); and
a buffer layer (#102, buffer layer) formed on the semiconductor substrate (#101),
wherein the electron transit layer (#103, nitride layer) is formed on the buffer layer (#102).
Regarding Claim 14, Hikita in view of Twynam teaches a method for manufacturing a nitride semiconductor device, the method comprising:
forming an electron transit layer composed of a nitride semiconductor (#103, Figure 1, GaN layer);
forming an electron supply layer (#104, AlGaN layer) on the electron transit layer (#103) and composed of a nitride semiconductor having a band gap that is larger than that of the electron transit layer ([0008], second nitride layer #104 has larger band gap than the first nitride layer #103);
forming a gate layer (#105-106, GaN layer) on the electron supply layer (#104) and composed of a nitride semiconductor including an acceptor impurity ([0032], #105 contains a p-type impurity);
forming a gate electrode (#111, gate electrode) on the gate layer (#105-106); and
forming a source electrode (#109, source electrode) and a drain electrode (#110, drain electrode) on the electron supply layer (#104),
wherein the gate layer includes an upper surface in contact with the gate electrode (#105-106 has upper surface contacting #111).
Hikita does not explicitly teach the upper surface is a Ga-polar surface.
However, Twynam teaches a nitride semiconductor device (Figure 1), wherein the upper surface is a Ga-polar surface (Figure 1, upper surface of AlGaN or GaN layer, [0086], #13 has a Ga polarity according to [0042]).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Hikita with the teaching of Twynam, as it would be simply a substitution of one known element (nitride layer of Hikita) for another (nitride layer of Twynam) in comparable devices to obtain predictable results. See MPEP 2143(I)(B).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hikita in view of Twynam, and further in view of US20190006500A1; Ueda et al.; (hereinafter “Ueda”).
Regarding Claim 8, Hikita in view of Twynam teaches the nitride semiconductor device as described in claim 7.
Hikita in view of Twynam does not explicitly teach the gate layer includes a ridge in contact with the electron supply layer and including the upper surface of the gate layer, and an extension in contact with the electron supply layer and extending outward from the ridge in plan view, the extension being smaller in thickness than the ridge.
However, Ueda teaches a nitride semiconductor device ([0010]), wherein the gate layer (#400, Figure 1, nitride layer) includes:
a ridge (#MS, mesa part) in contact with the electron supply layer (#300, nitride layer, wherein #MS contact #300) and including the upper surface of the gate layer (#MS contains upper surface of #400), and
an extension (#410, side parts) in contact with the electron supply layer (#410 contacts #300) and extending outward from the ridge in plan view (Figure 1), the extension being smaller in thickness than the ridge (thickness of #410 is smaller than #MS).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Hikita in view of Twynam with the teaching of Ueda in order to improve the device’s normally-off characteristics according to Ueda, [0094], and as it would be simply a substitution of one known element (nitride layer of Hikita) for another (nitride layer of Ueda) in comparable devices to obtain predictable results. See MPEP 2143(I)(B).
Allowable Subject Matter
Claim 2-6, 12 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the most relevant arts of record, Hikita discloses the nitride semiconductor device as described in claim 1 and the gate layer includes a first GaN layer (#106, Figure 1) in contact with the gate electrode (#111), and a second GaN layer (#105) in contact with the electron supply layer (#104).
Twynam discloses the GaN layer is composed of Ga-polar GaN.
Currently cited art but not relied upon US20230090106A1; Then et al.; (hereinafter “Then”) teaches a first GaN layer (Figure 1D, #116D) is composed of Ga-polar GaN ([0053]) and a second GaN layer (#124D) is composed of N-polar GaN ([0053]). Then does not teach other features of the device such as the first GaN layer in contact with the gate electrode and the second GaN layer in contact with the electron supply layer. One of ordinary skill in the art may not be motivated to combine Then with the current arts of record to achieve the claimed invention.
Hence, none of the prior art of record discloses or makes obvious the limitations: “the second GaN layer is composed of N-polar GaN” recited in claim 2, in combination with the other claimed elements.
Therefore, claim 2 is allowed and claims 3-6 and 12 are allowed at least by virtue of their dependency on claim 2.
Regarding Claim 15, the most relevant arts of record, Hikita discloses the method for manufacturing a nitride semiconductor device as described in claim 14 and the forming a gate layer includes forming a first nitride semiconductor layer (#105, Figure 1) on the electron supply layer (#104) and forming a second nitride semiconductor layer (#106) on the first nitride semiconductor layer (#105).
Then discloses a first nitride semiconductor layer being N-polar GaN (#124D, Figure 1D, [0053]) and a second nitride semiconductor layer being Ga-polar GaN (#116D, [0053]). Then does not teach other method steps of the device such as forming the second nitride semiconductor layer on the first nitride semiconductor layer. One of ordinary skill in the art may not be motivated to combine Then with the current arts of record to achieve the claimed invention.
None of the prior art of record discloses or makes obvious the limitations: “the first nitride semiconductor layer being N-polar GaN that is grown using N2 as a carrier gas” and “the second nitride semiconductor layer being Ga-polar GaN that is grown using H2 as a carrier gas” recited in claim 15, in combination with the other claimed method steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20230090106A1 – Figures 1A-B and 1D
US20200365694A1 – Figures 11 and 15
US20220029007A1 – Figures 6-8, [0054] and [0082]
US20080296618A1 – Figure 1(a)
US20220199816A1 – Figure 5, [0032]
US20140084344A1 – Figures 4B and 5B
WO2023276972A1 – Figures 1-19
Mohan, B, et al. “Analyzing Ga-Polar and N-Polar GaN HEMTs: A Comparative Study for High-Power DC Performance in Semiconductor Applications.” 2022 6th International Conference on Devices, Circuits and Systems (ICDCS), 23 Apr. 2024, pp. 317–321, ieeexplore.ieee.org/document/10560584, https://doi.org/10.1109/icdcs59278.2024.10560584.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812