Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Applicant’s amendments to the claims have overcome all 112(b) rejections. Therefore, the 112(b) rejections are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 10-13, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon’20 et al US 20200395531 A1, and in view of Kwon’14 et al US 20140124881 A1 and in further view of Park et al US 20140021566 A1. Kwon’20 et al and Kwon’14 et al will be referenced to as Kwon’20, Kwon’14, and Park respectively henceforth.
Regarding Claim 1,
Kwon’20 teaches:
“A semiconductor device comprising (FIG. 4):
a magnetic tunnel junction (MTJ) stack (MTJ, [0021]),), wherein a tunneling barrier of the MTJ stack (tunnel barrier pattern TBP, [0021]) and
a first encapsulation layer located around the reference layer (Park: sidewall portion, WP, [0037] [0074], [0091-0093], FIG. 25, FIG. 33: In FIG. 25, the lower and upper magnetic structures, 41 and 42 respectively, are formed using a damascene process. 41 may have a fixed magnetization and therefore may be a reference layer. Therefore, 41 and 42 may have the structure shown in FIG. 33. The structure of FIG. 33 includes a sidewall portion WP which is made of a metal oxide which may be demagnetized and therefore prevent an unintended physical effect.), wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer (Park: annotated FIG. 33 #1), wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer (Park: [0037], FIG. 25, FIG. 33: tunnel barrier 55 laterally extends past the entirety of 41. Therefore, 55 extends laterally past an outer vertical side surface of the first encapsulation layer.), wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer (Park: annotated FIG. 33 #1).”
Kwon’20 doesn’t substantially teach:
“is wider than a reference layer of the MTJ stack .”
However, Kwon’14 teaches:
“is wider than a reference layer of the MTJ stack (Kwon’14: [0172], annotated FIG. 6 #1: TB has a width w1, FL has a width greater than w1, and RL has width w2. w1 > w2.).”
Neither Kwon’20 nor Kwon’14 substantively teach:
“a first encapsulation layer located around the reference layer, wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer, wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer, wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer.”
However, Park teaches:
“a first encapsulation layer located around the reference layer (Park: sidewall portion, WP, [0037] [0074], [0091-0093], FIG. 25, FIG. 33: In FIG. 25, the lower and upper magnetic structures, 41 and 42 respectively, are formed using a damascene process. 41 may have a fixed magnetization and therefore may be a reference layer. Therefore, 41 and 42 may have the structure shown in FIG. 33. The structure of FIG. 33 includes a sidewall portion WP which is made of a metal oxide which may be demagnetized and therefore prevent an unintended physical effect.), wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer (Park: annotated FIG. 33 #1), wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer (Park: [0037], FIG. 25, FIG. 33: tunnel barrier 55 laterally extends past the entirety of 41. Therefore, 55 extends laterally past an outer vertical side surface of the first encapsulation layer.), wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer (Park: annotated FIG. 33 #1).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Kwon’20 is modifiable in view of Kwon’14 and Park.
This is because Kwon’14 teaches that a deposition process with poor step coverage results in the formation of MTJ layers that are formed spaced apart without a patterning process. One of ordinary skill in the art would recognize that this is advantageous because a patterning process is expensive and one of ordinary skill in the art would want to reduce costs.
This is further because the sidewall portion of Park substantially prevents the MTJ from exhibiting an unintended physical effect (Park: [0093]). That is, the sidewall portion may prevent unwanted magnetic behavior which disrupts the operation of the MTJ. One of ordinary skill in the art would recognize this effect to be beneficial because one of ordinary skill in the art would want the operation of the MTJ to work as expected.
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Regarding Claim 2,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 1(Kwon’20: FIG. 4), further comprising:
the MTJ stack comprises vertically aligned layers of a top electrode (Kwon’20: top electrode TE, [0032]), a free layer (Kwon’20: MP2, [0021]: MP2 may be a free layer.), the tunneling barrier (Kwon’20: TBP), the reference layer (Kwon’20: MP1) and a bottom electrode (Kwon’20: bottom electrode BE, [0032]).”
Regarding Claim 3,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 2, wherein the free layer is wider than the reference layer (Kwon’14: [0172], annotated FIG. 6 #1: TB has a width w1, FL has a width greater than w1, and RL has width w2. w1 > w2.).”
Regarding Claim 4,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 2, wherein a width of the free layer is equal to a width of the tunneling barrier (Kwon’20: annotated FIG. 4 #1: MP2 and TBP share the length w3.).”
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Regarding Claim 10,
Kwon’20/Kwon’14/Park teaches:
“A semiconductor device comprising (Kwon’20: annotated FIG. 4 #1):
a magnetic tunnel junction (MTJ) stack (Kwon’20: MTJ, [0021]), wherein a tunneling barrier of the MTJ stack (Kwon’20: tunnel barrier pattern TBP, [0021]) is wider than a reference layer of the MTJ stack (Kwon’14: [0172], annotated FIG. 6 #1: TB has a width w1, FL has a width greater than w1, and RL has width w2. w1 > w2.), wherein the tunneling barrier comprises a center portion and two outer portions (Kwon’20: annotated FIG. 4 #2), wherein the center portion is on an upper horizontal portion of the reference layer (Kwon’20: annotated FIG. 4 #2), and
a first encapsulation layer located around the reference layer (Park: sidewall portion, WP, [0037] [0074], [0091-0093], FIG. 25, FIG. 33: In FIG. 25, the lower and upper magnetic structures, 41 and 42 respectively, are formed using a damascene process. 41 may have a fixed magnetization and therefore may be a reference layer. Therefore, 41 and 42 may have the structure shown in FIG. 33. The structure of FIG. 33 includes a sidewall portion WP which is made of a metal oxide which may be demagnetized and therefore prevent an unintended physical effect.), wherein the first encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer (Park: annotated FIG. 33 #1), wherein the tunnel barrier extends laterally past an outer vertical side surface of the first encapsulation layer (Park: [0037], FIG. 25, FIG. 33: tunnel barrier 55 laterally extends past the entirety of 41. Therefore, 55 extends laterally past an outer vertical side surface of the first encapsulation layer.), wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the first encapsulation layer (Park: annotated FIG. 33 #1).”
Regarding Claim 11,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 10 (Kwon’20: FIG. 4), further comprising:
the MTJ stack comprises vertically aligned layers of a top electrode (Kwon’20: top electrode TE, [0032]), a free layer (Kwon’20: MP2, [0021]: MP2 may be a free layer.), the tunneling barrier (Kwon’20: TBP), the reference layer (Kwon’20: MP1) and a bottom electrode (Kwon’20: bottom electrode BE, [0032]).”
Regarding Claim 12,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 11, wherein the free layer is wider than the reference layer (Kwon’14: [0172], annotated FIG. 6 #1: TB has a width w1, FL has a width greater than w1, and RL has width w2. w1 > w2.).”
Regarding Claim 13,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 11, wherein a width of the free layer is equal to a width of the tunneling barrier (Kwon’20: annotated FIG. 4 #1: MP2 and TBP share the length w3.).”
Regarding Claim 19,
Kwon’20/Kwon’14/Park teaches:
“A method comprising (Kwon’20: annotated FIG. 4 #1):
forming a magnetic tunnel junction (MTJ) stack (Kwon’20: MTJ, [0021]), wherein a tunneling barrier of the MTJ stack (Kwon’20: tunnel barrier pattern TBP, [0021]) is wider than a reference layer of the MTJ stack (Kwon’14: [0172], annotated FIG. 6 #1: TB has a width w1, FL has a width greater than w1, and RL has width w2. w1 > w2.); and
forming an encapsulation layer located around the reference layer (Park: sidewall portion, WP, [0037] [0074], [0091-0093], FIG. 25, FIG. 33: In FIG. 25, the lower and upper magnetic structures, 41 and 42 respectively, are formed using a damascene process. 41 may have a fixed magnetization and therefore may be a reference layer. Therefore, 41 and 42 may have the structure shown in FIG. 33. The structure of FIG. 33 includes a sidewall portion WP which is made of a metal oxide which may be demagnetized and therefore prevent an unintended physical effect.), wherein the encapsulation layer has an interior vertical side surface that is in direct contact with the reference layer (Park: annotated FIG. 33 #1), wherein the tunnel barrier extends laterally past an outer vertical side surface of the encapsulation layer (Park: [0037], FIG. 25, FIG. 33: tunnel barrier 55 laterally extends past the entirety of 41. Therefore, 55 extends laterally past an outer vertical side surface of the first encapsulation layer.), wherein the interior vertical side surface and the outer vertical side surfaces are located on opposite sides of the encapsulation layer (Park: annotated FIG. 33 #1).”
Regarding Claim 20,
Kwon’20/Kwon’14/Park teaches:
“The method according to claim 19, wherein the tunneling barrier comprises a center portion and two outer portions (Kwon’20: annotated FIG. 4 #2), wherein the center portion is on an upper horizontal portion of the reference layer (Kwon’20: annotated FIG. 4 #2), and the two outer portions are on a slanted upper surface of an encapsulation layer surrounding the reference layer (Kwon’20: annotated FIG. 4 #2).”
Claims 6-7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon’20/Kwon’14/Park as applied to claims 1-4, 10-13, and 19-20 above, and further in view of Sugiyama et al US 20050195532 A1. Sugiyama et al will be referenced to as Sugiyama henceforth.
Regarding Claim 6,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 1,”
Kwon’20/Kwon’14/Park doesn’t substantially teach:
“wherein a lowermost portion of the tunneling barrier is below an uppermost portion of the reference layer.”
However, Sugiyama teaches:
“wherein a lowermost portion of the tunneling barrier is below an uppermost portion of the reference layer (Sugiyama: pinned layer 5, tunnel barrier 8b, recording layer 8c, [0110] [0116], [0119], FIG. 6: a portion of 8b is below 5.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Kwon’20/Kwon’14/Park is modifiable in view of Sugiyama.
This is because one of ordinary skill in the art would recognize that the error in the area of a TMR element may be reduced with the geometry of Sugiyama by one half. (Sugiyama: [0106-0109]). One of ordinary skill in the art would desire a reduction in the error of the area of a TMR element because these errors may compound to form large deformities leading to detrimental errors in the function of a semiconductor device.
Regarding Claim 7,
Kwon’20/Kwon’14/Park/Sugiyama teaches:
“The semiconductor device according to claim 2, wherein a lowermost portion of the free layer is below an uppermost portion of the reference layer (Sugiyama: pinned layer 5, tunnel barrier 8b, recording layer 8c, [0110] [0116], [0119], FIG. 6: a portion of 8c is below 5.). ”
Regarding Claim 15,
Kwon’20/Kwon’14/Park/Sugiyama teaches:
“The semiconductor device according to claim 10, wherein a lowermost portion of the tunneling barrier is below an uppermost portion of the reference layer (Sugiyama: pinned layer 5, tunnel barrier 8b, recording layer 8c, [0110] [0116], [0119], FIG. 6: a portion of 8b is below 5.). ”
Regarding Claim 16,
Kwon’20/Kwon’14/Park/Sugiyama teaches:
“The semiconductor device according to claim 11, wherein a lowermost portion of the free layer is below an uppermost portion of the reference layer (Sugiyama: pinned layer 5, tunnel barrier 8b, recording layer 8c, [0110] [0116], [0119], FIG. 6: a portion of 8c is below 5.). ”
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon’20/Kwon’14 as applied to claims 1-4, 10-13 and 19-20 above, and further in view of Kanaya et al US 20140284734 A1. Kanaya et al will be referenced to as Kanaya henceforth.
Regarding Claim 8,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 2,”
Kwon’20/Kwon’14/Park doesn’t substantially teach:
“further comprising:
a second encapsulation layer surrounding vertical side surfaces of the free layer and the tunneling barrier.”
However, Kanaya teaches:
“further comprising:
a second encapsulation layer surrounding vertical side surfaces of the free layer and the tunneling barrier (Kanaya: protective portion 29, [0083], FIG. 4). ”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Kwon’20/Kwon’14 is modifiable in view of Kanaya.
This is because the additional protective portion covering the sidewalls of an MTJ suppress oxidation of the peripheral materials of the MTJ element in the air. This oxidation increases the resistance of the MTJ which may cause degradation. (Kanaya: [0083])
Regarding Claim 17,
Kwon’20/Kwon’14/Park/Kanaya teaches:
“The semiconductor device according to claim 11, further comprising:
a second encapsulation layer surrounding vertical side surfaces of the free layer and the tunneling barrier (Kanaya: protective portion 29, [0083], FIG. 4). ”
Claims 9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon’20/Kwon’14/Park as applied to claims 1-4, 10-13, and 19-20 above, and further in view of Aggarwal et al US 20190221609 A1. Aggarwal et al will be referenced to as Aggarwal henceforth.
Regarding Claim 9,
Kwon’20/Kwon’14/Park teaches:
“The semiconductor device according to claim 2,”
Kwon’20/Kwon’14/Park doesn’t substantially teach:
“further comprising:
a first inter-layer dielectric surrounding the bottom electrode;
a second inter-layer dielectric surrounding the reference layer;
a third inter-layer dielectric surrounding the free layer and the tunneling barrier; and
a fourth inter-layer dielectric surrounding the top electrode.”
However, Aggarwal teaches:
“further comprising:
a first inter-layer dielectric surrounding the bottom electrode (Aggarwal: layer 434, [0071-0072], FIG. 5E: 434 may include silicon nitride. Silicon nitride is a dielectric. 434 surrounds a bottom electrode.);
a second inter-layer dielectric surrounding the reference layer (Aggarwal: layer 442, [0065-0066], [0071-0072], FIG. 5E: 442 may include silicon nitride. Silicon nitride is a dielectric. 442 surrounds a reference layer. The reference layer is the top layer of stack 406. 406 forms an MTJ bit.);
a third inter-layer dielectric surrounding the free layer and the tunneling barrier (Aggarwal: layer 436, [0065-0066], [0071-0072], FIG. 5E: 436 may include silicon nitride. Silicon nitride is a dielectric. 436 surrounds a free layer and a tunnel barrier layer. The free layer is the bottom layer of stack 406 and the tunnel barrier layer is the middle layer of 406. 406 forms an MTJ bit.); and
a fourth inter-layer dielectric surrounding the top electrode (Aggarwal: layer 444, [0069, 0072], FIG. 5E: 444 comprises a dielectric material. 444 surrounds via 450. Via 450 is a top electrode.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Kwon’20/Kwon’14/Park is modifiable in view of Aggarwal.
This is because one of ordinary skill in the art would recognize that alternating dielectric materials with different etch rates or etch properties may assist in the performance of further processing steps, such as etching conductive vias to varying depths. One of ordinary skill in the art would recognize that in the invention of Kwon’20/Kwon’14/Park, vias are etched to varying depths and therefore the alternating dielectric layers of Aggarwal are useful.
Regarding Claim 18,
Kwon’20/Kwon’14/Park/Aggarwal teaches:
“The semiconductor device according to claim 11, further comprising:
a first inter-layer dielectric surrounding the bottom electrode (Aggarwal: layer 434, [0071-0072], FIG. 5E: 434 may include silicon nitride. Silicon nitride is a dielectric. 434 surrounds a bottom electrode.);
a second inter-layer dielectric surrounding the reference layer (Aggarwal: layer 442, [0065-0066], [0071-0072], FIG. 5E: 436 may include silicon nitride. Silicon nitride is a dielectric. 442 surrounds a reference layer. The reference layer is the top layer of stack 406. 406 forms an MTJ bit.);
a third inter-layer dielectric surrounding the free layer and the tunneling barrier (Aggarwal: layer 436, [0065-0066], [0071-0072], FIG. 5E: 436 may include silicon nitride. Silicon nitride is a dielectric. 436 surrounds a free layer and a tunnel barrier layer. The free layer is the bottom layer of stack 406 and the tunnel barrier layer is the middle layer of 406. 406 forms an MTJ bit); and
a fourth inter-layer dielectric surrounding the top electrode (Aggarwal: layer 444, [0069, 0072], FIG. 5E: 444 comprises a dielectric material. 444 surrounds via 450. Via 450 is a top electrode.).”
Allowable Subject Matter
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claims 5 and 14,
Kwon’20/Kwon’14/Park fails to explicitly teach :
“wherein the first encapsulation layer has a slanted upper surface” In view of the rest of the limitations of claims 5 and 14 respectively.
Kwon’20/Kwon’14/Park fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because upon the inclusion of the encapsulation layer of Park into the invention of Kwon’20, the encapsulation layer no longer includes a slanted upper surface. There is no clear reason why one of ordinary skill in the art would make the upper surface of the encapsulation layer slanted. The other prior arts of record do not remedy this deficiency.
Response to Arguments
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Park.
The Examiner notes that no office action makes reference to, “Su” or “Block”. These are references the Examiner used in another application. The Examiner believes Applicant meant to reference prior arts in the current record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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