Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/472,312 filed on 09/22/2023.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 and 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 8 recite the limitation "the second semiconductor region of the trunk portion" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claims 2 and 8 also recite the limitation “wherein a width of the second semiconductor region of the trunk portion." However, it is unclear as to what Applicant is intending to claim in view of the specification and drawings. What applicant is referring to? What applicant mean by the second semiconductor region of the trunk portion? The trunk portion only described to be a part of the semiconductor substrate.
Additionally, the limitations “the second semiconductor region of the trunk portion entirely becomes a channel” is indefinite. What is considered to be “…entirely becomes a channel when the semiconductor device is turned on”?
Claims 4 and 9 recite the limitation "the second semiconductor region of the branch portion" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claims 4 and 9 also recite the limitation “wherein a width of the second semiconductor region of the branch portion." However, it is unclear as to what Applicant is intending to claim in view of the specification and drawings. What applicant is referring to? What applicant mean by the second semiconductor region of the trunk portion? The branch portion only described to be a part of the semiconductor substrate.
Additionally, the limitations “the second semiconductor region of the branch portion entirely becomes a channel” is indefinite. What is considered to be “…entirely becomes a channel when the semiconductor device is turned on”?
Claim 6 recites the limitation "the second semiconductor regions" in lines 2 and 4-5. There is insufficient antecedent basis for this limitation in the claim.
As best understood, the branch portion and the trunk portion are referring to the part of the semiconductor substrate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2019/0189800 to Orita et al. (Orita).
Regarding independent claim 1, Orita discloses a semiconductor device (Figs. 11 and 12) comprising:
a semiconductor substrate (Fig. 12: elements 11-12, 21-23 and 30 are considered to be a semiconductor substrate) having a first main surface and a second main surface, wherein a first semiconductor region (11) having a first conductivity type (N), a second semiconductor region (20) having a second conductivity type (P), and a third semiconductor region (21) having a first conductivity type (N) are arranged in this order in a thickness direction of the semiconductor substrate, the third semiconductor region (21) being provided at a position exposed from the first main surface (Fig. 12); and
a plurality of trench gates (Fig. 12: 30 and ¶0083) extended from the first main surface of the semiconductor substrate (10) to reach the first semiconductor region (11) beyond the third semiconductor region (21) and the second semiconductor region (20), wherein
the plurality of trench gates (30) is arranged to be spaced apart from each other in a first direction (x) when the semiconductor substrate is viewed in a plan view (Although the Orita illustrates the plurality of trench gates in a cross-sectional view, a cross-sectional figure represents only a slice of a physical structure. The depiction in cross-section does not negate the presence of the same plurality of trench gates when the device is viewed from a plan perspective. The plurality of trench gates necessarily exists within the semiconductor substrate regardless of the viewing orientation of the illustration), and
a part of the semiconductor substrate (Fig. 11: 23) located between the trench gates (Fig. 12: 30) adjacent to each other in the first direction (x) includes a trunk portion (Fig. 11: 23H) extending in a second direction (Y) orthogonal to the first direction and a branch portion (Fig. 11: 23G) protruding from the trunk portion (Fig. 11: 23H) when the semiconductor substrate is viewed in a plan view (Fig. 11).
Regarding claim 6, Orita discloses wherein the second semiconductor regions (23) oppose each other (Figs. 11 and 12) with the trench gate (30) interposed therebetween, and the branch portion (Fig. 11: W1) of one of the second semiconductor regions (23) faces the trunk portion (Fig. 11: W2) of the other of the second semiconductor regions (23) in the first direction.
Regarding independent claim 7, Orita discloses a method of manufacturing a semiconductor device (Figs. 11 and 12) comprising:
forming a plurality of trenches (Fig. 12: where 30 is formed in trenches with respect to Fig. 5B and ¶0042) on a first main surface of a semiconductor substrate (Fig. 12: elements 11-12, 21-23 and 30 are considered to be a semiconductor substrate), wherein a first semiconductor region (11) having a first conductivity type (N), a second semiconductor region (20) having a second conductivity type (P), and a third semiconductor region (21) having a first conductivity type (N) are arranged in this order in a thickness direction of the semiconductor substrate, the third semiconductor region (21) being provided at a position exposed from the first main surface (Fig. 12), each of the trenches (Fig.5B: 50) being extended from the first main surface of the semiconductor substrate to reach the first semiconductor region (11) beyond the third semiconductor region (21) and the second semiconductor region (20); and
forming a trench gate (Fig. 12: 30) in each of the plurality of trenches, wherein
the trench gate (30) is one of a plurality of trench gates (30) arranged to be spaced apart from each other in a first direction (x) when the semiconductor substrate is viewed in a plan view (Although the Orita illustrates the plurality of trench gates in a cross-sectional view, a cross-sectional figure represents only a slice of a physical structure. The depiction in cross-section does not negate the presence of the same plurality of trench gates when the device is viewed from a plan perspective. The plurality of trench gates necessarily exists within the semiconductor substrate regardless of the viewing orientation of the illustration), and
a part of the semiconductor substrate (Fig. 11: 23) between the trench gates (Fig. 12: 30) adjacent to each other in the first direction includes a trunk portion (Fig. 11: 23H) extending in a second direction (Y) orthogonal to the first direction and a branch portion (Fig. 11: 23G) protruding from the trunk portion (Fig. 11: 23G) when the semiconductor substrate is viewed in a plan view (Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2019/0189800 to Orita et al. (Orita).
Regarding claims 2 and 8, Orita discloses wherein a width (W2) of the second semiconductor region (23) of the trunk portion (Fig. 11: 23H) in the first direction (x) is set within a range in which the second semiconductor region (23) of the trunk portion (Fig. 11: 23H) entirely becomes a channel when the semiconductor device is turned on.
As best understood, this claim is referring to an intended use of the device. It is not clear what is intended to structurally limited the device claimed. The limitations “entirely becomes a channel when the semiconductor device is turned on” is an intended use recitation rather than required feature further limiting the scope of the claims.
It is noted that Prior art's device can be operated such that the entirety of the second semiconductor region 23 becomes fully depleted give adequate bias voltage such that it entirely becomes a conductive path (i.e. a channel). No specific structure features are otherwise claimed that would render the device structurally distinguishable over the prior art device teaching the claimed device structure.
The applied prior art can be so modified or used and therefore renders unpatentable such claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals): In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP§2114. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. The recitation of “entirely becomes a channel when the semiconductor device is turned on” does not distinguish the present invention over the prior art of Orita).
Regarding claim 3, Orita discloses wherein a width (W1) of the second semiconductor region (23) of the trunk portion (Fig. 11: 23G) in the first direction is 200 nm or less (¶0048).
Regarding claims 4 and 9, Orita discloses wherein a width (W1) of the second semiconductor region (23) of the branch portion (Fig. 11: 23G) in the first direction (x) is set within a range in which the second semiconductor region (23) of the branch portion (Fig. 11: 23G) entirely becomes a channel when the semiconductor device is turned on.
As best understood, this claim is referring to an intended use of the device. It is not clear what is intended to structurally limited the device claimed. The limitations “entirely becomes a channel when the semiconductor device is turned on” is an intended use recitation rather than required feature further limiting the scope of the claims.
It is noted that Prior art's device can be operated such that the entirety of the second semiconductor region 23 becomes fully depleted give adequate bias voltage such that it entirely becomes a conductive path (i.e. a channel). No specific structure features are otherwise claimed that would render the device structurally distinguishable over the prior art device teaching the claimed device structure.
The applied prior art can be so modified or used and therefore renders unpatentable such claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals): In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP§2114. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. The recitation of “entirely becomes a channel when the semiconductor device is turned on” does not distinguish the present invention over the prior art of Orita).
Regarding claim 5, Orita discloses wherein a width (W2) of the second semiconductor region (23) of the trunk portion (Fig. 11: 23H) in the first direction is 200 nm or less (¶0048).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2024/00969578 to Kondo et al., US Pub # 2023/0078116., US Pub # 2021/0083097 to Gangi, US Pub # 2018/0240906 to Tsujimura et al., US Pub # 2009/0072304 to Adan, US Pat # 6,005,271 to Hshieh.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896