Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 15, 16 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The office now relies on new reference Koyama (WO 2016159385 A1) for the rejection of amended limitations of claims 1 and 15, as necessitated by the applicant’s amendments. Koyama teaches the added electrode structures in the amended claims 1 and 15 as explained below. Hence, the rejection for claims 1, 11, 14, 16-17 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Koyama (WO 2016159385 A1) in view of Konrath (US 20150255362 A1) further in view of Zhang (Thin Solid Films, Volume 580, 1 April 2015).
Re: Independent Claim 1 (Currently amended), Koyama discloses a semiconductor device, comprising:
a cell region in which cells are formed; and a peripheral region located at an outer side of the cell region so as to surround the cell region (Koyama teaches, in Fig. 1 and its description, an active region 20a through which current flows in an on-state and a breakdown-voltage structure region 20b surrounding the active region 20a. Koyama further teaches, in Fig. 2 and its description, that the active region 20a includes unit cells repeatedly arranged adjacent to one another. Thus, Koyama’s active region 20a corresponds to the claimed cell region, and Koyama’s breakdown-voltage structure region 20b corresponds to the claimed peripheral region),
wherein: the cell region includes
gate structures spaced apart from each other in a first direction intersecting a thickness direction of the semiconductor device, each of the gate structures including a gate insulating layer and an electrode material electrically connected to a gate electrode (Koyama teaches, in Fig. 4 and Embodiment 3 description, a trench-gate embodiment in which trench 30 is provided at the front-surface side of active region 20a, gate insulating film 35 is provided in trench 30, and gate electrode 36 is provided inside trench 30 via gate insulating film 35. Koyama further teaches that the trench-gate embodiment is applied to the active-region MOS gate structure and that the unit cells are repeatedly arranged in the active region. Therefore, the repeated trench-gate structures include gate insulating film 35 and gate electrode 36 corresponding to the claimed gate structures spaced apart from each other),
a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductivity type partially formed in the first semiconductor layer (Koyama teaches, in Fig. 4, and Embodiment 3 description, n-type drift layer 1 as a first semiconductor layer of a first conductive type, and p-type base region 32 as a second semiconductor region of a second conductivity type partially formed at the front-surface side of the n-type drift layer 1),
an insulation film covering the cells, the insulation film covering the electrode material and a head surface of the first semiconductor layer (Koyama teaches, in Fig. 3, interlayer insulating film 7 is formed on the front surface of the wafer and covers gate electrode 6. In the trench-gate embodiment, Koyama teaches, in Fig. 4, trench 30, gate insulating film 35, and gate electrode 36, and states that the configuration of interlayer insulating film 7 is the same as in the first embodiment. Therefore, Koyama’s interlayer insulating film 7 covers the cells, covers the gate electrode material 36, and covers the front/head surface of the cell region inducing the n-type drift layer 1 and semiconductor regions formed at the front-surface side thereof), the insulation film including openings exposing part of the head surface of the cell region, at least one of the openings being arranged between the gate structures (Koyama teaches, in Embodiment 1 description, that interlayer insulating film 7 is selectively removed to form contact holes, thereby exposing n+ type region 3 and p+ region 4 in the cell region. Because Koyama applies the same interlayer-insulation/contact-electrode configuration to the trench-gate embodiment, the corresponding contact hole in the trench-gate embodiment expose n+ type source region 33 and p+ type contact region 34 between adjacent trench gate structures 30/35/36. Thus, Koyama teaches openings in the insulation film exposing part of the head surface of the cell region, with at least one opening arranged between the gate structures),
an electrode portion including a stacked part stacked on the insulation film (Koyama teaches, in Fig. 4 and Embodiment 3 description, barrier metal 8 and front surface electrode 9 formed over the interlayer insulating film 7 and electrically connected to the exposed source/contact regions through the contact openings).
Regarding the limitation “a barrier layer that covers both the insulation film and the electrode portion, the barrier layer having a smaller diffusion coefficient than the insulation film, and a passivation film stacked on the barrier layer and having a larger diffusion coefficient than the barrier layer; and wherein the barrier layer entirely covers at least one of the openings as viewed in the thickness direction” Koyama teaches, in Abstract, a protective film 10 made of a material having a smaller mobile-ion diffusion coefficient than interlayer insulating film 7. Koyama specifically teaches that protective film 10 may be silicon nitride, while interlayer film 7 may be PSG/BPSG or another silicon oxide film. Koyama also teaches that sodium-ion diffusion in silicon nitride is smaller/slower than in silicon oxide. Koyama is silent regarding a barrier layer that covers both the insulation film and the electrode portion, the barrier layer having a smaller diffusion coefficient than the insulation film, and a passivation film stacked on the barrier layer and having a larger diffusion coefficient than the barrier layer; and wherein the barrier layer entirely covers at least one of the openings as viewed in the thickness direction.
However, Konrath teaches, in Fig. 1 and ¶ [0026], a passivation stack for a semiconductor device including oxide layer 31, nitride layer 32 and imide layer 33. Konrath teaches that nitride layer 32 may be silicon nitride and is formed below imide layer 33. Konrath further teaches that the oxide/nitride layers function as humidity barriers to protect the semiconductor device and contact electrode from humidity and corrosion.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Koyama by forming Konrath’s silicon nitride barrier layer over Koyama’s cell region interlayer insulating film 7 and electrode portion 8/9, and by forming Konrath’s imide passivation film over the nitride barrier layer, in order to improve humidity resistance, corrosion protection, and mobile-ion blocking in the semiconductor device.
In the modified Koyama/Konrath device, the silicon nitride barrier covers both the insulation film 7 and the electrode portion 8/9. Further, because the electrode portion 8/9 overlies and contacts the source/contact regions through the contact openings, and because Konrath’s nitride barrier layer is formed over the electrode/passivation structure, the nitride barrier layer entirely covers at least one of Koyama’s contact openings as view in the thickness direction.
Both Koyama and Konrath are silent regarding:
the barrier layer having a smaller diffusion coefficient than the peripheral insulation film; and the passivation film having a larger diffusion coefficient than the barrier layer.
However, Zhang (Thin Solid Films, Volume 580, 1 April 2015; Title: Moisture barrier evaluation of SiOx/SiNx stacks on polyimide substrates using electrical calcium test) teaches the barrier layer having a smaller diffusion coefficient than the peripheral insulation film; and the passivation film having a larger diffusion coefficient than the barrier layer (Zhang teaches Silicon nitride (SiNx) and silicon oxide (SiOx) films deposited on a polyimide substrate show great moisture impermeability while the SiNx film present higher moisture resistance than the SiOx film, while the underlying polyimide substrate has high moisture permeation properties. A person of ordinary skill in the art would understand that in a oxide/nitride/imide stack as in Koyama in view of Konrath, the nitride layer 32 of Konrath has a smaller diffusion coefficient for moisture than the underlying oxide peripheral insulation film (layer 31 of Konrath), and that the outer imide/polyimide passivation film (layer 33 of Konrath) stacked on the nitride barrier layer has a larger diffusion coefficient than the nitride barrier, consistent with the measured ordering of permeabilities in Zhang (polyimide> SiOx>SiNx).
Accordingly, with Koyama in view of Konrath and Zhang, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Koyama, a nitride barrier layer covering the insulation film and field late, and an outer imide/polyimide passivation film stacked on the barrier in order to reduce the permeation rate of moisture through the polymeric substrate, inorganic or organic barrier layer usually prepared on the substrates (Zhang, Introduction 2nd paragraph).
Re: Claim 11 (Original), Koyama in view of Konrath and further in view of Zhang disclose all the limitations of claim 1 on which this claim depends.
Konrath further teaches wherein a thickness of the barrier layer is less than a thickness of the passivation film (as applied in the claim 1 rejection, Konrath teaches a multilayer passivation/encapsulation stack including (i) a second layer 32 comprising a nitride (corresponding to the claimed barrier layer) and (ii) a third layer 33 comprising an imide (corresponding to the claimed passivation film stacked on the barrier layer). Konrath further teaches, in ¶¶ [0028] - [0029], that the nitride second layer 32 has thickness of 0.6 micrometer and the imide third layer 33 has thickness of 7 micrometer). Therefore, Konrath teaches thickness of the barrier layer (nitride layer 32) is less than a thickness of the passivation film (imide layer 33).
Re: Claim 14 (Currently Amended), Koyama in view of Konrath and further in view of Zhang disclose all the limitations of claim 1 on which this claim depends.
Koyama and Konrath further teach wherein: the insulation film is a silicon oxide film; the passivation film is an organic insulation film; and the barrier layer is a silicon nitride film.
Koyama teaches the insulation film is a silicon oxide film (Koyama teaches insulating film 7 covering the gate electrode/gate material and teaches that interlayer insulating film 7 is made of a silicon oxide film such as PDG or BPSG).
Konrath teaches the peripheral insulation film is a silicon oxide film the passivation film is an organic insulation film; and the barrier layer is a silicon nitride film (Konrath teaches, in ¶ [0033], a passivation layer stack including the oxide first layer 31, second layer 32 is silicon nitride. Konrath teaches that nitride layer 32 may be silicon nitride and that imide layer 33 is formed on nitride layer 32.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Koyama by forming Konrath’s silicon nitride layer 32 as the barrier layer over Koyama’s silicon-oxide interlayer insulating film 7 and electrode portion, and by forming Konrath’s imide layer 33 as the organic insulation passivation film stacked on the silicon nitride barrier layer, in order to protect the device surface from humidity and corrosion (Konrath, ¶ [0042]);
Re: Claim 16 (New), Koyama in view of Konrath and further in view of Zhang disclose all the limitations of claim 1 on which this claim depends.
Konrath further teaches
wherein the barrier layer extends across the entire cell region (Konrath teaches forming passivation stack over the semiconductor device surface and contact electrode, including oxide layer 31, nitride layer 32, and imide later 33. Konrath’s nitride layer 32 is provided as a barrier layer in the passivation stack and is formed over the underlying surface/electrode structure to protect the device form humidity and corrosion. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to from Konrath’s silicon nitride barrier layer 32 so that it extends across Koyama’s entire active/cell region 20a, including over the interlayer insulating film 7 and electrode portion 8/9, in order to provide uniform humidity-barrier protection and corrosion resistance across active cell region of the semiconductor device).
Re: Claim 17 (New), Koyama in view of Konrath and further in view of Zhang disclose all the limitations of claim 1 on which this claim depends.
Koyama further teaches
wherein the barrier layer is in contact with the electrode portion (Koyama teaches protective film 10 on interlayer insulating film 7. Koyama also teaches, in Fig. 3 and Embodiment 1 description, that barrier metal layer 8 is provided on the surface of protective film 10, and front surface electrode 9 is provided on barrier metal 8 so as to bury the contact hole. Thus, Koyama teaches that the protective/barrier film 10 is in direct contact with the electrode portion, including barrier metal 8 and front surface electrode 9).
Claims 15 are rejected under 35 U.S.C. 103 as being unpatentable over Koyama (WO 2016159385 A1) in view of Konrath (US 20150255362 A1).
Re: Independent Claim 15 (Currently amended)
A semiconductor device, comprising:
a cell region in which cells are formed; and a peripheral region located at an outer side of the cell region so as to surround the cell region (Koyama teaches, in Fig. 1 and its description, an active region 20a through which current flows in an on-state and a breakdown-voltage structure region 20b surrounding the active region 20a. Koyama further teaches, in Fig. 2 and its description, that the active region 20a includes unit cells repeatedly arranged adjacent to one another. Thus, Koyama’s active region 20a corresponds to the claimed cell region, and Koyama’s breakdown-voltage structure region 20b corresponds to the claimed peripheral region),
wherein: the cell region includes
gate structures spaced apart from each other in a first direction intersecting a thickness direction of the semiconductor device, each of the gate structures including a gate insulating layer and an electrode material electrically connected to a gate electrode (Koyama teaches, in Fig. 4 and Embodiment 3 description, a trench-gate embodiment in which trench 30 is provided at the front-surface side of active region 20a, gate insulating film 35 is provided in trench 30, and gate electrode 36 is provided inside trench 30 via gate insulating film 35. Koyama further teaches that the trench-gate embodiment is applied to the active-region MOS gate structure and that the unit cells are repeatedly arranged in the active region. Therefore, the repeated trench-gate structures include gate insulating film 35 and gate electrode 36 corresponding to the claimed gate structures spaced apart from each other),
a first semiconductor layer of a first conductive type, a second semiconductor region of a second conductivity type partially formed in the first semiconductor layer (Koyama teaches, in Fig. 4, and Embodiment 3 description, n-type drift layer 1 as a first semiconductor layer of a first conductive type, and p-type base region 32 as a second semiconductor region of a second conductivity type partially formed at the front-surface side of the n-type drift layer 1),
an insulation film covering the cells, the insulation film formed of a silicon oxide film, the insulation film covering the electrode material and a head surface of the first semiconductor layer (Koyama teaches, in Fig. 3, interlayer insulating film 7 is formed on the front surface of the wafer and covers gate electrode 6. In the trench-gate embodiment, Koyama teaches, in Fig. 4, trench 30, gate insulating film 35, and gate electrode 36, and states that the configuration of interlayer insulating film 7 is the same as in the first embodiment. Therefore, Koyama’s interlayer insulating film 7 covers the cells, covers the gate electrode material 36, and covers the front/head surface of the cell region inducing the n-type drift layer 1 and semiconductor regions formed at the front-surface side thereof. Koyama further teaches that interlayer insulating film 7 is made of a silicon oxide film such as PDG or BPSG),
the insulation film including openings exposing part of the head surface of the cell region, at least one of the openings being arranged between the gate structures (Koyama teaches, in Embodiment 1 description, that interlayer insulating film 7 is selectively removed to form contact holes, thereby exposing n+ type region 3 and p+ region 4 in the cell region. Because Koyama applies the same interlayer-insulation/contact-electrode configuration to the trench-gate embodiment, the corresponding contact hole in the trench-gate embodiment expose n+ type source region 33 and p+ type contact region 34 between adjacent trench gate structures 30/35/36. Thus, Koyama teaches openings in the insulation film exposing part of the head surface of the cell region, with at least one opening arranged between the gate structures),
an electrode portion including a stacked part stacked on the insulation film (Koyama teaches, in Fig. 4 and Embodiment 3 description, barrier metal 8 and front surface electrode 9 formed over the interlayer insulating film 7 and electrically connected to the exposed source/contact regions through the contact openings).
Koyama is silent regarding
a barrier layer formed of a silicon nitride film and covering both the insulation film and the electrode portion, and a passivation film formed of an organic insulation film, the passivation film stacked on the barrier layer; and wherein the barrier layer entirely covers at least one of the openings as viewed in the thickness direction.
However, Konrath teaches, in Fig. 1 and ¶ [0026], a passivation stack for a semiconductor device including oxide layer 31, nitride layer 32 and imide layer 33. Konrath teaches that nitride layer 32 may be silicon nitride and is formed below imide layer 33. Konrath further teaches that the oxide/nitride layers function as humidity barriers to protect the semiconductor device and contact electrode from humidity and corrosion.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Koyama by forming Konrath’s silicon nitride barrier layer over Koyama’s cell region interlayer insulating film 7 and electrode portion 8/9, and by forming Konrath’s organic imide passivation film over the nitride barrier layer, in order to improve humidity resistance, corrosion protection, and mobile-ion blocking in the semiconductor device.
In the modified Koyama/Konrath device, the silicon nitride barrier covers both the insulation film 7 and the electrode portion 8/9. Further, because the electrode portion 8/9 overlies and contacts the source/contact regions through the contact openings, and because Konrath’s nitride barrier layer is formed over the electrode/passivation structure, the nitride barrier layer entirely covers at least one of Koyama’s contact openings as view in the thickness direction.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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