CTNF 18/472,338 CTNF 100158 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first interconnect must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. [ Note: It is possible the “first interconnect” is depicted in the drawings; however, it is not clear from the drawings, specification, and claims what the “first interconnect” comprises. See the discussion of objections to the specification, which follows.] 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 06-16 AIA 3. Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. 4. The abstract of the disclosure is objected to for the following reasons: It recites “is disclosed” in lines 2-3, which can be implied; and It recites “on-volatile memory” in line 4, which should read “non-volatile memory.” Examiner also suggests clarifying references to “via plug” in lines 11-12 and “first plug” in line 14. Note the rest of the disclosure uses the terms “first via plug” and “second via plug,” while “first plug” and “via plug” appear only in the Abstract. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). 06-11 AIA 5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: “Memory Device with ESD Protection Element.” 07-44 6. The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required. 7. ¶[0065] recites, “The above described first interconnect comprises the footprint 60 (the first electrically conductive part 61), the first via plug 51, the micro-strip line 40, the first pad electrode 41, and the bonding wire 43.” However, in claim 1, the “first interconnect” is connected to first pad electrode 41 and first electrically conductive part 61. In claim 6, the “first interconnect” is connected to first pad electrode 41 and first via plug 51. Unless ¶[0065] describes an embodiment not mentioned in the claims, the “first interconnect” cannot comprise elements it is also connected to (see also claims 15 and 17). Because the specification appears to contradict the claims in this regard, it does not provide proper antecedent basis for the claimed subject matter in at least claims 1, 6, 15, and 17. 8. In the embodiment of claim 12, the “first interconnect” is exclusively a micro-strip line. Nowhere in the specification is the “first interconnect” identified as a micro-strip line, although ¶[0065] states the “first interconnect” comprises micro-strip line 40 among other components. Therefore, the specification does not provide proper antecedent basis for the claim subject matter of claim 12. Claim Objections 9. Claim 18 is objected to because of the following informalities. On page 7, lines 32-33 (lines 27-28 of the claim), the claim recites, “a first via plug that is provided in the substrate and includes one end and another,” which should recite, “a first via plug that is provided in the substrate and includes one end and another end .” Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA 11. Claim s 1-3, 13-16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Nishizawa, et al (US 20010011766 A1), hereinafter Nishizawa, in view of Han, et al (US 7606046 B2), hereinafter Han, further in view of Han, et al (US 20170018535 A1), hereinafter Han ‘535, further in view of Feinberg, et al (US 4245273 A), hereinafter Feinberg, and further in view of IPC-4761 (IPC-4761, Design Guide for Protection of Printed Board Via Structures, July 2006) . Regarding independent claim 1, Nishizawa teaches a memory device comprising: a substrate ( FIG. 6, 1 ) that includes a first surface and a second surface opposite to the first surface ( FIG. 6, e.g., “top” and “bottom” surfaces of substrate 1 ); a non-volatile memory that is provided on the first surface of the substrate ( FIGS. 5-6, 34a..34d; ¶[0112] ); a memory controller that is provided on the first surface of the substrate ( FIGS. 5-6, 33; ¶[0112] ) and connected to the non-volatile memory ( FIG. 5, controller 33 is shown connected to non-volatile memory chips 34a..34d ); a first interconnect ( FIG. 5, 37; ¶[0113] ) that is provided on the first surface of the substrate ( ¶[0142] ) and includes one end and another end ( one end may be connected to bonding pattern 38 and another end may be connected to electrically conducting pattern 36; ¶[0113] ); a first pad electrode that is provided on the first surface of the substrate ( FIGS. 5-6, bonding pattern 38; ¶[0113] ); a second pad electrode that is provided on the memory controller ( FIG. 5, external terminal 50 shown on memory controller 33; ¶[0113] ); a wire that includes one end and another end and connects the first pad electrode and the second pad electrode ( FIG. 5, wire 41 shown connecting 38 to 50; ¶[0113] ); a footprint that is provided on the first surface of the substrate and includes a first electrically conductive part and a second electrically conductive part ( FIGS. 5 and 6, a “footprint” may be for mounting ESD protection component 11a, with first conducting part being electrically conducting pattern 36 and second conducting part connected to wiring pattern 35 (see pad of 35 in FIGS. 6 and 13); ¶[0112] ); an ESD protection element that is connected to the footprint and includes a first terminal and a second terminal ( FIG. 5, ESD protection component 11a, with first terminal connected to electrically conducting pattern 36 and second terminal connected to wiring pattern 35; ¶[0112] ); a connection terminal that is exposed from the second surface of the substrate and electrically connectable to a host device ( FIG. 6, e.g., 3d exposed from second (bottom) surface through plastic casing (¶[0155]; FIG. 21) ); and a first via plug that is provided in the substrate and includes one end and another end ( FIGS. 5 and 6, via 40 has a first (“top”) end and a second (bottom) end ), wherein: a shape of the second electrically conductive part is a solid shape ( e.g., FIG. 13 shows pad connecting 11a to 35 as a solid rectangle ); the one end of the wire is connected to the first pad electrode; the another end of the wire is connected to the second pad electrode ( FIG. 5, wire 41 shown connecting one end to first pad electrode 38 and another end to second pad electrode 50; ¶[0113] ); the one end of the first interconnect is connected to the first pad electrode; the another end of the first interconnect is connected to the first electrically conductive part of the footprint ( FIG. 5, one end of “first interconnect” 37 shown connected to “first pad electrode” 38 and another end is shown connected to the “first electrically conductive part of the footprint” 36; ¶[0113] ); the one end of the first via plug is connected to the first electrically conductive part of the footprint ( FIGS. 5 and 6, via 40 shown with one end connected to 36 ); the first terminal of the ESD protection element is connected to the first electrically conductive part of the footprint; and the another end of the first via plug is connected to the connection terminal ( FIG. 5, via 40 is shown with one end connected to 36 and the other end connected to connection terminal 3d ). Nishizawa does not teach a first ground plane that is provided on the first surface of the substrate and connected to the footprint; a second ground plane that is provided in the substrate; a shape of the second ground plane is a solid shape; and via 40 is a via plug. Han teaches a first ground plane that is provided on the first surface of the substrate and connected to the footprint ( FIG. 5A shows first signal layer with component mounting features and ground plane 122; Col. 2, ll. 30-32; Col. 4, ll. 54-60 ); a second ground plane that is provided in the substrate ( FIG. 5B shows second (interior) signal layer with ground plane 122; Col. 2, ll. 30-32; Col. 4, ll. 54-63 ); a shape of the second ground plane is a solid shape ( FIG. 5B shows ground plane 122 as solid except where routing is accommodated ). Han ‘535 teaches in FIGS. 3 and 4 and ¶[0034] a via plug ( 130 ) connecting a first electrically conductive part of a footprint ( 125 ) to a connection terminal ( 115 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Han into the method of Nishizawa to include ground planes on multiple layers of a substrate. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of confining or containing electric fields contained in the signals between ground planes ( Feinberg Col. 3, ll. 34-39 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Han ‘535 into the method of Nishizawa to include via plugs (plugged vias) in a substrate. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of preventing solder and chemistry from migrating to the opposite side of the board in assembly ( IPC-4761 p. 4, Col. 2, ¶2, bullet 1 ). Regarding claim 2, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 1. Nishizawa further teaches the second electrically conductive part of the footprint is connected to the second terminal of the ESD protection element ( FIGS. 5 and 6, a “footprint” may be for mounting ESD protection components 11a, with first conducting part being electrically conducting patterns 36 and second conducting part connected to wiring patters 35 (see pad of 35 in FIGS. 6 and 13 for connecting the second terminals of 11a to wiring patterns 35); ¶[0112] ). Regarding claim 3, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 2. Nishizawa as modified by Han further teaches the first ground plane is connected to the second electrically conductive part of the footprint ( Nishizawa’s second electrically conductive part of the footprint (FIGS. 4-6, wiring patterns 35) is shown connected to ground on the first surface, and therefore may be Han’s first signal layer ground plane (FIG. 5A, 122) ). Regarding claim 13, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 1. Nishizawa further teaches the ESD protection element includes a first diode and a second diode; and a cathode of the first diode and a cathode of the second diode are connected ( FIG. 4, 11a..11e show bidirectional Zener diode arrangements connected cathode-to-cathode ). Regarding claim 14, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 13. Nishizawa further teaches each of the first diode and the second diode is a Zener diode ( FIG. 4, 11a..11e show bidirectional Zener diode arrangements connected cathode-to-cathode ). Regarding claim 15, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 1. Nishizawa as modified by Han ‘535 further teaches the second pad electrode is connected to the connection terminal via the wire, the first pad electrode, the first interconnect, the footprint and the first via plug ( Nishizawa FIGS. 5 and 6, second pad electrode 50 is connected through wire 41, first pad electrode 38, first interconnect 37, footprint first electrically conducting pattern 36, and via 40 to connection terminal 3d; Nishizawa as modified by Han ‘535 teaches via 40 may be a via plug ). Regarding claim 16, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 1. Nishizawa further teaches when viewing the ESD protection element and the footprint from above the first surface of the substrate, an area in which the ESD protection element is provided and an area in which the footprint is provided are partially overlapped ( FIGS. 5 and 6, ESD protection element 11d is shown partially overlapping footprint pads 35 and 36 ). Regarding independent claim 18, Nishizawa teaches a memory device comprising: a substrate ( FIG. 6, 1 ); a non-volatile memory that is provided on a first surface of the substrate ( FIGS. 5-6, 34a..34d; ¶[0112] ); a memory controller that is provided on the first surface of the substrate ( FIGS. 5-6, 33; ¶[0112] ) and connected to the non-volatile memory ( FIG. 5, controller 33 is shown connected to non-volatile memory chips 34a..34d ); a first interconnect ( FIG. 5, 37; ¶[0113] ) that is provided on the first surface of the substrate ( ¶[0142] ) and includes one end and another end, wherein the one end is connected to the memory controller ( one end may be connected to bonding pattern 38 and another end may be connected to electrically conducting pattern 36; ¶[0113] ); a footprint that is provided on the first surface of the substrate, connected to the another end of the first interconnect and includes a first electrically conductive part and a second electrically conductive part ( FIGS. 5 and 6, a “footprint” may be for mounting ESD protection component 11a, with first conducting part being electrically conducting pattern 36 and second conducting part connected to wiring pattern 35 (see pad of 35 in FIGS. 6 and 13); ¶[0112] ); an ESD protection element that is connected to the footprint and includes a first terminal and a second terminal ( FIG. 5, ESD protection component 11a, with first terminal connected to electrically conducting pattern 36 and second terminal connected to wiring pattern 35; ¶[0112] ); a connection terminal that is exposed from a second surface of the substrate and electrically connectable to a host device ( FIG. 6, e.g., 3d exposed from second (bottom) surface through plastic casing (¶[0155]; FIG. 21) ); and a first via plug that is provided in the substrate and includes one end and another ( FIGS. 5 and 6, via 40 has a first (“top”) end and a second (bottom) end ), the one end of the first via plug being connected to the another end of the first interconnect ( FIGS. 5 and 6, first end of via 40 is connected to first interconnect 37 through electrically conducting pattern 36 ), the another end of the first via plug being connected to the connection terminal ( FIGS. 5 and 6, second end of via 40 is connected to connection terminal 3d ), wherein: a shape of the first electrically conductive part is a solid shape ( e.g., FIG. 5 shows electrically conducting pattern 36 as a solid rectangle ); and a shape of the second electrically conductive part is a solid shape ( FIG. 6, 35; see also FIG. 13 showing pad connecting 11a to 35 as a solid rectangle ). Nishizawa does not teach a first ground plane that is provided on the first surface of the substrate and connected to the footprint; a second ground plane that is provided in the substrate; and via 40 is a via plug. Han teaches a first ground plane that is provided on the first surface of the substrate and connected to the footprint ( FIG. 5A shows first signal layer with component mounting features and ground plane 122; Col. 2, ll. 30-32; Col. 4, ll. 54-60 ); a second ground plane that is provided in the substrate ( FIG. 5B shows second (interior) signal layer with ground plane 122; Col. 2, ll. 30-32; Col. 4, ll. 54-63 ); Han ‘535 teaches in FIGS. 3 and 4 and ¶[0034] a via plug ( 130 ) connecting a first electrically conductive part of a footprint ( 125 ) to a connection terminal ( 115 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Han into the method of Nishizawa to include ground planes on multiple layers of a substrate. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of confining or containing electric fields contained in the signals between ground planes ( Feinberg Col. 3, ll. 34-39 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Han ‘535 into the method of Nishizawa to include via plugs (plugged vias) in a substrate. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of preventing solder and chemistry from migrating to the opposite side of the board in assembly ( IPC-4761 p. 4, Col. 2, ¶2, bullet 1 ). Regarding claim 19, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 18. Nishizawa further teaches the first electrically conductive part of the footprint is connected to the first terminal of the ESD protection element; the second electrically conductive part of the footprint is connected to the second terminal of the ESD protection element ( FIGS. 5 and 6, a “footprint” may be for mounting ESD protection component 11a, with first conducting part being electrically conducting pattern 36 and second conducting part connected to wiring pattern 35 (see pad of 35 in FIGS. 6 and 13 for connecting the second terminals of 11a to wiring patterns 35); ¶[0112] ); and the one end of the first via plug is connected to the first electrically conductive part of the footprint ( FIGS. 5 and 6, via 40 shown with one end connected to 36 ). Regarding claim 20, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 19. Nishizawa as modified by Han further teaches the first ground plane is connected to the second electrically conductive part of the footprint ( Nishizawa FIGS. 5 and 6, second conducting part connected to wiring pattern 35 is shown in FIG. 4 as connected to ground; Han FIG. 5A shows first signal layer with component mounting features and ground plane 122; therefore, Nishizawa’s ground connected to wiring pattern 35 may be connected to Han ‘535’s ground plane ). Regarding claim 21, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 20. Han further teaches a shape of the second ground plane is a solid shape ( FIG. 5B, ground plane 122 is shown as solid except where accommodating signal routing ) . 07-21-aia AIA 12. Claim s 6-7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nishizawa, et al (US 20010011766 A1), hereinafter Nishizawa, in view of Shrier, et al (US 20060061925 A1), hereinafter Shrier, further in view of Dohya (US 5012047 A), further in view of Han, et al (US 20170018535 A1), hereinafter Han ‘535, and further in view of IPC-4761 (IPC-4761, Design Guide for Protection of Printed Board Via Structures, July 2006) . Regarding independent claim 6, Nishizawa teaches a memory device comprising: a substrate ( FIG. 6, 1 ) that includes a first surface and a second surface opposite to the first surface ( FIG. 6, e.g., “top” and “bottom” surfaces of substrate 1 ); a non-volatile memory that is provided on the first surface of the substrate ( FIGS. 5-6, 34a..34d; ¶[0112] ); a memory controller that is provided on the first surface of the substrate ( FIGS. 5-6, 33; ¶[0112] ) and connected to the non-volatile memory ( FIG. 5, controller 33 is shown connected to non-volatile memory chips 34a..34d ); a first interconnect ( FIG. 5, 37; ¶[0113] ) that is provided on the first surface ( ¶[0142] ) of the substrate and includes one end and another end ( one end may be connected to bonding pattern 38 and another end may be connected to electrically conducting pattern 36; ¶[0113] ); a first pad electrode that is provided on the first surface of the substrate ( FIGS. 5-6, bonding pattern 38; ¶[0113] ); a second pad electrode that is provided on the memory controller ( FIG. 5, external terminal 50 shown on memory controller 33; ¶[0113] ); a wire that includes one end and another end and connects the first pad electrode and the second pad electrode ( FIG. 5, wire 41 shown connecting 38 to 50; ¶[0113] ); a first via plug that is provided in the substrate and includes one end and another end ( FIGS. 5 and 6, via 40 has a first (“top”) end and a second (bottom) end ); a connection terminal that is exposed from the second surface of the substrate and electrically connectable to a host device ( FIG. 6, e.g., 3d exposed from second (bottom) surface through plastic casing (¶[0155]; FIG. 21) ); and a second via plug that is provided in the substrate and includes one end and another end ( FIG. 5 shows multiple instances of via 40 ), wherein: the one end of the wire is connected to the first pad electrode; the another end of the wire is connected to the second pad electrode ( FIG. 5, wire 41 shown connecting one end to first pad electrode 38 and another end to second pad electrode 50; ¶[0113] ); the one end of the first interconnect is connected to the first pad electrode; the another end of the first interconnect is connected to the one end of the first via plug ( FIG. 5, one end of “first interconnect” 37 shown connected to “first pad electrode” 38 and another end is shown connected to the “first electrically conductive part of the footprint” 36, which contains via 40; ¶[0113] ); the another end of the first via plug is connected to the first electrically conductive part of the footprint ( FIGS. 5-6, via 40 is shown connected to 36 ); and the first terminal of the ESD protection element is connected to the first electrically conductive part of the footprint ( FIG. 5, ESD component 11b is shown connected to “first electrically conductive part of the footprint” 36 ). Nishizawa does not teach the another end of the second via plug is connected to the connection terminal; an ESD protection element that is provided in the substrate and includes a first terminal and a second terminal; a footprint that is provided in the substrate and includes a first electrically conductive part and a second electrically conductive part; and vias are via plugs. Shrier teaches an ESD protection element ( FIG. 8, 110; ¶[0031-0032] ) that is provided in the substrate ( FIG. 8, 210; ¶[0032] ) and includes a first terminal ( FIG. 8, top conductor 114 (see FIG. 7) connected to via 148 (see FIG. 7) ) and a second terminal ( FIG. 8, bottom conductor 216 connected to via 266 ); a footprint that is provided in the substrate and includes a first electrically conductive part ( FIG. 8, top conductor 114 (see FIG. 7) connected to via 148 (see FIG. 7) ), and a second electrically conductive part ( FIG. 8, bottom conductor 216 connected to via 266 ). Shrier teaches a single via ( FIGS. 7-8, 148 ) is connecting a “first electrically conducting part” ( top surface of PCB ) to a “connection terminal” ( FIG. 8, 250 ). Dohya teaches in FIG. 1 a plurality of signal wiring layers ( 11, 12a, 12b, etc. ) and vias ( 17 ) connecting a “first electrically conducting part” ( 15 ) to a “connection terminal” (16). Therefore, Shrier as modified by Dohya may use one via to connect Shrier’s ESD component to a “first electrically conducting part” and another via to connect Shrier’s ESD component to a “connection terminal.” Han ‘535 teaches in FIGS. 3 and 4 and ¶[0034] a via plug ( 130 ) connecting a first electrically conductive part of a footprint ( 125 ) to a connection terminal ( 115 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Shrier into the method of Nishizawa to include embedding an ESD suppression device in a printed circuit board. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of providing a way to protect board components from harmful ESD events ( Shrier, Abstract ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dohya into the method of Nishizawa to include a plurality of vias. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of connecting signal wiring layers ( Dohya, Col. 2, ll. 6-7 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Han ‘535 into the method of Nishizawa to include via plugs (plugged vias) in a substrate. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of preventing solder and chemistry from migrating to the opposite side of the board in assembly ( IPC-4761 p. 4, Col. 2, ¶2, bullet 1 ). Regarding claim 7, Nishizawa as modified by Shrier, Dohya, Han ‘535, and IPC-4761 teaches the limitations of claim 6. Nishizawa and Shrier further teach the second electrically conductive part of the footprint is connected to the second terminal of the ESD protection element ( Nishizawa FIGS. 5 and 6, a “footprint” may be for mounting ESD protection component 11a, with first conducting part being electrically conducting pattern 36 and second conducting part connected to wiring pattern 35 (see pad of 35 in FIGS. 6 and 13 for connecting the second terminals of 11a to wiring patterns 35); ¶[0112]; Shrier FIG. 8, bottom conductor 216 connected to via 266 functions as both the second electrically conducting part and second terminal ). Regarding claim 17, Nishizawa as modified by Shrier, Dohya, Han ‘535, and IPC-4761 teaches the limitations of claim 6. Nishizawa as modified by Han ‘535 further teaches the second pad electrode is connected to the connection terminal via the wire, the first pad electrode, the first interconnect, the first via plug, the footprint and the second via plug ( Nishizawa FIGS. 5 and 6, second pad electrode 50 is connected through wire 41, first pad electrode 38, first interconnect 37, footprint first electrically conducting pattern 36, and via 40 to connection terminal 3d; Nishizawa as modified by Han ‘535 teaches via 40 may be a via plug ) . 07-21-aia AIA 13. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nishizawa, et al (US 20010011766 A1), hereinafter Nishizawa, in view of Shrier, et al (US 20060061925 A1), hereinafter Shrier, further in view of Dohya (US 5012047 A), further in view of Han, et al (US 20170018535 A1), hereinafter Han ‘535, further in view of IPC-4761 (IPC-4761, Design Guide for Protection of Printed Board Via Structures, July 2006), further in view of in view of Han, et al (US 7606046 B2), hereinafter Han, and further in view of Feinberg, et al (US 4245273 A), hereinafter Feinberg , Regarding claim 8, Nishizawa as modified by Shrier, Dohya, Han ‘535, and IPC-4761 teaches the limitations of claim 7. Nishizawa does not teach a first ground plane that is provided on the first surface of the substrate and a second ground plane that is provided in the substrate, wherein the first ground plane is connected to the second electrically conductive part of the footprint. Han teaches a first ground plane that is provided on the first surface of the substrate ( FIG. 5A shows first signal layer with component mounting features and ground plane 122; Col. 2, ll. 30-32; Col. 4, ll. 54-60 ) and a second ground plane that is provided in the substrate ( FIG. 5B shows second (interior) signal layer with ground plane 122; Col. 2, ll. 30-32; Col. 4, ll. 54-63 ), Shrier and Han further teach the first ground plane is connected to the second electrically conductive part of the footprint ( Shrier teaches in FIG. 8 and ¶[0032] the second electrically conductive part of the footprint (bottom conductor of 110) is electrically connected to ground 260, and therefore may be electrically connected to the ground planes of Han ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Han into the method of Nishizawa to include ground planes on multiple layers of a substrate. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of confining or containing electric fields contained in the signals between ground planes ( Feinberg Col. 3, ll. 34-39 ) . 07-21-aia AIA 14. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Nishizawa, et al (US 20010011766 A1), hereinafter Nishizawa, in view of Han, et al (US 7606046 B2), hereinafter Han, further in view of Han, et al (US 20170018535 A1), hereinafter Han ‘535, further in view of Feinberg, et al (US 4245273 A), hereinafter Feinberg, further in view of IPC-4761 (IPC-4761, Design Guide for Protection of Printed Board Via Structures, July 2006), and further in view of Kleveland, et al (US 5969929 A), hereinafter Kleveland . Regarding claim 12, Nishizawa as modified by Han, Han ‘535, Feinberg, and IPC-4761 teaches the limitations of claim 1. Nishizawa does not teach the first interconnect is a micro-strip line. Kleveland teaches the first interconnect is a micro-strip line ( FIG. 4A; Col. 6, ll. 35-39 ). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kleveland into the method of Nishizawa to include micro-strip lines for high-speed interconnects. The ordinary artisan would have been motivated to modify Nishizawa in the above manner for the purpose of ensuring when the transmission line elements are coupled to ESD protection elements, the effective impedance of the ESD protection circuit is the desired value (Kleveland, Col. 6, ll. 49-55) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 15. Claim s 4-5, 9-11, and 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 16. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 4, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the substrate includes an insulating layer and a printed wiring board; the insulating layer and the printed wiring board are stacked in this order in a first direction that is from the second surface toward the first surface; and the first via plug is provided in the printed wiring board and in the insulating layer. Claims 5 and 11 depend on claim 4. Regarding claim 9, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the substrate includes a first insulating layer, a second insulating layer, a third insulating layer and a printed wiring board; and the first insulating layer, the second insulating layer and the printed wiring board are stacked in this order in a first direction that is from the second surface toward the first surface. Claim 10 depends on claim 9. Regarding claim 22, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the substrate includes an insulating layer and a printed wiring board; the insulating layer and the printed wiring board are stacked in this order in a first direction that is from the second surface toward the first surface; and the first via plug is provided in the printed wiring board and in the insulating layer. Claim 23 depends on claim 22. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.S.C./Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827 Application/Control Number: 18/472,338 Page 2 Art Unit: 2827 Application/Control Number: 18/472,338 Page 3 Art Unit: 2827 Application/Control Number: 18/472,338 Page 4 Art Unit: 2827 Application/Control Number: 18/472,338 Page 5 Art Unit: 2827 Application/Control Number: 18/472,338 Page 6 Art Unit: 2827 Application/Control Number: 18/472,338 Page 7 Art Unit: 2827 Application/Control Number: 18/472,338 Page 8 Art Unit: 2827 Application/Control Number: 18/472,338 Page 9 Art Unit: 2827 Application/Control Number: 18/472,338 Page 10 Art Unit: 2827 Application/Control Number: 18/472,338 Page 11 Art Unit: 2827 Application/Control Number: 18/472,338 Page 12 Art Unit: 2827 Application/Control Number: 18/472,338 Page 13 Art Unit: 2827 Application/Control Number: 18/472,338 Page 14 Art Unit: 2827 Application/Control Number: 18/472,338 Page 15 Art Unit: 2827 Application/Control Number: 18/472,338 Page 16 Art Unit: 2827 Application/Control Number: 18/472,338 Page 17 Art Unit: 2827 Application/Control Number: 18/472,338 Page 18 Art Unit: 2827 Application/Control Number: 18/472,338 Page 19 Art Unit: 2827 Application/Control Number: 18/472,338 Page 20 Art Unit: 2827 Application/Control Number: 18/472,338 Page 21 Art Unit: 2827 Application/Control Number: 18/472,338 Page 22 Art Unit: 2827 Application/Control Number: 18/472,338 Page 23 Art Unit: 2827 Application/Control Number: 18/472,338 Page 24 Art Unit: 2827 Application/Control Number: 18/472,338 Page 25 Art Unit: 2827 Application/Control Number: 18/472,338 Page 26 Art Unit: 2827
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