Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 7
b. Pending: 1-12
Claims 1, 3, 5, 7 and 11 have been amended. Claims 13-26 are withdrawn.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Information Disclosure Statement
New information disclosure statement (IDS) is submitted on 12/2/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 3 objection is withdrawn pursuant to amendment.
Claim Rejections - 35 USC § 112
Claims 5-6 and 11-12 rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20140068171) in view of Kawakubo et al. (US 2008015670).
Regarding independent claim 1, Lee discloses a method of performing multi-memory bank refreshes of volatile memory devices performed by a memory controller (Fig. 3 shows multiple memory banks and ABSTARCT describes refresh control circuit), comprising:
selecting a number of memory banks within a plurality of memory banks to refresh in a multi-bank memory refresh cycle ([0052] describes that modified mode information represent a number of memory banks for refresh operation);
selecting a first memory bank within the plurality of memory banks to refresh in the multi-bank refresh cycle ([0052] describes that a selection signal activation unit configured to activate one or more of selection signals for selecting corresponding one or more of the memory banks); and
applying a multi-bank of memory refresh command to a memory device, wherein the multi-bank of memory refresh command encodes the number of memory banks to be refreshed, and the first memory bank to refresh (Fig. 3 and [0068] describes mode information modification unit 100 receives mode information MODE_INF, modifies the mode information MODE_INF using the internal chip information CHIP_INF and outputs modified mode information MOD_MODE_INF. The mode information MODE_INF is used to adjust a number of memory bank groups involved with refresh operation in response to a single refresh command), and
wherein the memory device is configured to refresh the number of memory bank including the first memory bank in response to the multi- bank of memory refresh command ([0069]-[0087] along with Table 1, 2 and 3 describes performing refresh operation for a number of memory banks).
Also, Kawakubo teaches the multi-bank of memory refresh command encodes the number of memory banks to be refreshed in Fig. 117 and corresponding sections of the specification.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kawakubo to Lee in order to provide with memory device, memory controller and memory system for increasing an effective bandwidth indicating the number of data items that can be processed per unit time as taught by Kawakubo ([0003]).
Regarding claim 2, Lee and Kawakubo together disclose all the elements of claim 1 as above and through Lee further the multi-bank of memory refresh command encodes the number of memory banks to be refreshed in z bits, wherein z is an integer; and the multi-bank of memory refresh command is completed in m clock cycles, wherein m is an integer (Figs. 2A-2C and [0012] shows activated refresh pulse REFP in multiple cycles and [0052] along with claim 1 describes that modified mode information represent a number of memory banks to be refreshed).
Regarding claim 4, Lee and Kawakubo together disclose all the elements of claim 1 as above and through Lee further selecting one of a plurality of different patterns of memory bank refreshing sequences, wherein the multi-bank of memory refresh command also encodes the pattern for refreshing particular memory banks ([0012] describes The mode information MODE_INF indicates one of 3 modes. When the mode information MODE_INF indicates the first (1st) mode, the refresh operations on all of memory bank groups 31 to 34 are performed. When the mode information MODE_INF indicates the second (2nd) mode, the refresh operations on a pair of memory bank groups 31 to 34 are performed. When the mode information MODE_INF indicates the 3rd mode, the refresh operations on each of memory bank groups 31 to 34 are performed. Each refresh operation is performed in response to application of an activated refresh pulse REFP).
Regarding claim 5, Lee and Kawakubo together disclose all the elements of claim 4 as above and through Lee further selecting one of a plurality of different patterns of memory bank refreshing sequences comprises selecting one of an incremental pattern, a pairwise pattern based on pairs of memory banks specified for the memory device, a step of N pattern to refresh every Nth memory bank from the first memory bank, or a diagonal pattern based on the pairs of memory banks specified for the memory device ([0012], Fig. 3 and [0069] describes selecting from various refreshing patterns).
Regarding claim 6, Lee discloses all the elements of claim 5 as above and further wherein in N equals 2 ([0012], Fig. 3 and [0069]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20140068171) in view of Kawakubo et al. (US 2008015670) and Iyer et al. (US 20130080694).
Regarding claim 3, Lee and Kawakubo together disclose all the elements of claim 2 as above and through Iyer further z equals 3 and m equals 2 ([0062] describes that refresh cycles that will be required is dependent upon several parameters of the memory system. Specifically, the number of reserved refresh cycles will be a function of a number of memory banks B in the memory system, a number of rows R in each memory bank, and the total number of memory cycles W that occur during each cell retention time period Here Examiner asserts that 8 memory bank groups can be coded by three bits. And in 2 clock cycles all those could be refreshed).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Iyer to modified Lee in order to provide mechanism for a multi-bank memory system with dual concurrent refresh, the memory refresh operations do not consume most of the available operating cycles since most memory refreshing is performed concurrently with memory access (read or write) operations as taught by Iyer ([0041]).
Claims 7-12 are exact device claims of corresponding method claims 1-6 and henceforth rejected the same way.
Response to Arguments
Applicant’s arguments with respect to independent claims 1 and 7 have been considered but are not persuasive and also moot because the new ground of rejection rely on new reference along with previously used references applied in the prior rejection of record.
Primary reference Lee in Fig 2 and paragraphs [0068]-[0069] states that MODE_INF adjusts a number of memory banks to be refreshed. That means it is a coded information.
Also, new reference Kawakubo supports coding number of banks to be refreshed in Fig. 117 and corresponding sections of the specification.
Rejections are maintained at-least for above mentioned reasons. Details will be found under “Claim Rejections”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 1/26/2025
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