DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities: claim 20 recites the phrase “aligned with third gate spacer” which is being interpreted to read “aligned with a third gate spacer.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8-11 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0331232 A1 to Frougier et al. (hereinafter “Frougier”).
Regarding claim 1, Frougier discloses a microelectronic structure comprising:
a first nanosheet transistor column, wherein the first nanosheet transistor column includes a plurality of first channel layers and a first gate located around each of the plurality of first channel layers (FET structure having fin 26 with gate structure 44 surrounding the semiconductor channel layers 10; Figs. 9-10 and 13; paragraphs [0008]-[0009], [0024]-[0025], [0028]);
a second nanosheet transistor column, wherein the second nanosheet transistor column includes a plurality of second channel layers and a second gate located around each of the plurality of second channel layers, wherein the first nanosheet transistor column is adjacent to the second nanosheet column (adjacent fin 26 with gate structure 44 surrounding the semiconductor channel layers 10; Figs. 9-10 and 13; paragraphs [0024]-[0025]);
a source/drain located between the first nanosheet transistor column and the second nanosheet transistor column (source/drain 40 disposed between adjacent fins 26; Figs. 9-10 and 13); and
a dielectric cap located on top of and in direct contact with a frontside surface of the source/drain, wherein the dielectric cap is in contact with a sidewall of the first gate and the dielectric cap is in contact with a sidewall of the second gate (dielectric layers 28, 46 collectively disposed on top of an in direct contact with side surface of source/drain 40 as well as sidewalls of first and second gate structures 44; Figs. 9-10 and 13).
Regarding claim 2, Frougier discloses microelectronic structure of claim 1, wherein the dielectric cap extends laterally over the plurality of first channel layers and the plurality of second channel layers (dielectric layers 28, 46 extend laterally over first and second channel layers 10; Figs. 9-10 and 13).
Regarding claim 3, Frougier discloses the microelectronic structure of claim 2, wherein a bottom surface of the dielectric cap is in contact with the source/drain, one of the plurality of first channel layers, and one of the plurality of second channel layers (bottom surface of dielectric layers 28, 46 contacts source/drain 40 and first and second channel layers 10; Figs. 9-10 and 13).
Regarding claim 4, Frougier discloses the microelectronic structure of claim 1, wherein a top surface of the dielectric cap is level with a top surface of the first gate and the top surface of the second gate (top surface of dielectric layers 28, 46 level with top surface of first and second gates 44; Figs. 9-10 and 13).
Regarding claim 8, Frougier discloses the microelectronic structure of claim 1, further comprising: an airgap located adjacent to the second gate, wherein the airgap is located on the opposite side of the second gate than the dielectric cap (airgap adjacent second gate 44 on side opposite layers 28, 46; Figs. 9-10 and 13).
Regarding claim 9, Frougier discloses the microelectronic structure of claim 8, wherein the airgap and the dielectric cap are located on the same level (airgap and layers 28, 46 are located on same horizontal level; Figs. 9-10 and 13).
Regarding claim 10, Frougier discloses a microelectronic structure comprising:
a first nanosheet transistor column, wherein the first nanosheet transistor column includes a plurality of first channel layers and a first gate located around each of the plurality of first channel layers (FET structure having fin 26 with gate structure 44 surrounding the semiconductor channel layers 10; Figs. 9-10 and 13; paragraphs [0008]-[0009], [0024]-[0025], [0028]);
a second nanosheet transistor column, wherein the second nanosheet transistor column includes a plurality of second channel layers and a second gate located around each of the plurality of second channel layers, wherein the first nanosheet transistor column is adjacent to the second nanosheet column (adjacent fin 26 with gate structure 44 surrounding the semiconductor channel layers 10; Figs. 9-10 and 13; paragraphs [0024]-[0025]);
a first source/drain located between the first nanosheet transistor column and the second nanosheet transistor column (first source/drain 40 disposed between adjacent fins 26; Figs. 9-10 and 13); a dielectric cap located on top of and in direct contact with a frontside surface of the first source/drain, wherein the dielectric cap is in contact with a sidewall of the first gate and the dielectric cap is in contact with a sidewall of the second gate (dielectric layers 28, 46 collectively disposed on top of an in direct contact with side surface of source/drain 40 as well as sidewalls of first and second gate structures 44; Figs. 9-10 and 13); and
an airgap located adjacent to the second gate, wherein the airgap is located on the opposite side of the second gate than the dielectric cap, wherein the airgap is vertically aligned over the plurality of second channel layers (airgap adjacent second gate 44 on side opposite layers 28, 46 and aligned vertically over part of channel layers 10; Figs. 9-10 and 13).
Regarding claim 11, Frougier discloses the microelectronic structure of claim 10, further comprising: a third nanosheet transistor column, wherein the third nanosheet transistor column includes a plurality of third channel layers and a third gate located around each of the plurality of third channel layers, wherein the third nanosheet transistor column is adjacent to the second nanosheet column (another adjacent fin 26 with gate structure 44 surrounding the semiconductor channel layers 10; Figs. 9-10 and 13; paragraphs [0024]-[0025]); and a second source/drain located between the second nanosheet transistor column and the third nanosheet transistor column (second source/drain 40 disposed between adjacent fins 26; Figs. 9-10 and 13).
Regarding claim 15, Frougier discloses a microelectronic structure comprising:
a plurality of nanosheet transistor columns, wherein the plurality of nanosheet columns are horizontally aligned (FET structure having fin 26 with gate structure 44 surrounding the semiconductor channel layers 10; Figs. 9-10 and 13; paragraphs [0008]-[0009], [0024]-[0025], [0028]);
a first dielectric cap located between and in contact with a gate of two adjacent nanosheet transistor columns, wherein the first dielectric cap is horizontally aligned with the plurality of nanosheet columns (dielectric layers 28, 46 collectively between and in contact with first and second gate structures 44 and horizontally aligned with fins 26; Figs. 9-10 and 13); and
a second dielectric cap located in a region adjacent to the plurality of nanosheet transistor columns, wherein the second dielectric cap is located and in contact with two adjacent gates (another iteration of dielectric layers 28, 46 collectively between and in contact with another iteration of gate structures 44 and horizontally aligned with fins 26; Figs. 9-10 and 13).
Regarding claim 16, Frougier discloses the microelectronic structure of claim 15, wherein a bottom surface of the first dielectric cap is in contact with a top surface of a source/drain, wherein the bottom surface of the first dielectric cap is in contact with a channel layer of each of the two adjacent nanosheet columns (bottom surface of dielectric layers 28, 46 contacts source/drain 40 and first and second channel layers 10 of adjacent fins 26; Figs. 9-10 and 13).
Regarding claim 17, Frougier discloses the microelectronic structure of claim 16, further comprising: a first airgap located adjacent to a gate of one of the two adjacent nanosheet columns, wherein the first airgap is located on the opposite side of the gate than the first dielectric cap (airgap adjacent gate 44 on side opposite layers 28, 46; Figs. 9-10 and 13).
Regarding claim 18, Frougier discloses the microelectronic structure of claim 17, wherein a bottom surface of the second dielectric cap is in contact with a top surface of a frontside interlayer dielectric layer, wherein the bottom surface of the second dielectric cap is in contact with a top surface of a first gate spacer and a top surface of a second gate spacer, and wherein the first gate spacer and second gate spacer are located on opposite sides of the frontside interlayer dielectric layer (layers 28, 46 in part disposed directly over top surface of dielectric material 22 and left and right gate spacers 24, where spacers 24 are disposed on opposite sides of dielectric material 22; Figs. 9-10 and 13).
Regarding claim 19, Frougier discloses the microelectronic structure of claim 18, further comprising: a second airgap located adjacent to a gate of one of the two adjacent gates, wherein the second airgap is located on the opposite side of the gate than the second dielectric cap (another airgap adjacent gate 44 on side opposite layers 28, 46; Figs. 9-10 and 13).
Regarding claim 20, Frougier discloses the microelectronic structure of claim 19, wherein the second airgap is vertically aligned with third gate spacer (second airgap vertically aligned with one of gate spacers 24 of one of fins 26; Figs. 9-10 and 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier.
Regarding claim 5, Frougier discloses the microelectronic structure of claim 4. Frougier fails to explicitly disclose a gate contact is in direct contact to the second gate of the second nanosheet transistor column, wherein the gate contact is in in direct contact with multiple surfaces of the second gate.
However, paragraph [0027] of Frougier discloses middle-of-line and back-end-of-line processing, which includes formation of contacts and wiring for the local interconnect structure overlying the device structure, and formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled by the interconnect wiring with the functional gate structure 44 and source/drain regions 40 of the field-effect transistor 50.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Frougier with this particular design choice in order to potentially provide reduced gate resistance, improved switching speed, reduced gate delay spread, and provides increased flexibility for layout and scaling of the device.
Regarding claim 6, Frougier discloses the microelectronic structure of claim 5. Frougier fails to explicitly disclose wherein the gate contact is in contact with a side surface of the second gate and the top surface of the second gate.
However, paragraph [0027] of Frougier discloses middle-of-line and back-end-of-line processing, which includes formation of contacts and wiring for the local interconnect structure overlying the device structure, and formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled by the interconnect wiring with the functional gate structure 44 and source/drain regions 40 of the field-effect transistor 50.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Frougier with this particular design choice in order to potentially provide reduced gate resistance, improved switching speed, reduced gate delay spread, and provides increased flexibility for layout and scaling of the device.
Regarding claim 7, Frougier discloses the microelectronic structure of claim 6. Frougier fails to explicitly disclose wherein the gate contact extends into the dielectric cap.
However, paragraph [0027] of Frougier discloses middle-of-line and back-end-of-line processing, which includes formation of contacts and wiring for the local interconnect structure overlying the device structure, and formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled by the interconnect wiring with the functional gate structure 44 and source/drain regions 40 of the field-effect transistor 50. Further, Fig. 9 of Frougier illustrates layer 26 surrounding the gate structure 44, which if connected to contacts of the interconnect structure, would render obvious the contacts extending through layer 26 in order to connect to gate structure 44.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Frougier with this particular design choice in order to potentially provide reduced gate resistance, improved switching speed, reduced gate delay spread, and provides increased flexibility for layout and scaling of the device.
Regarding claim 12, Frougier discloses the microelectronic structure of claim 11. Frougier fails to explicitly disclose a frontside contact in direct contact with a frontside surface of the third source/drain.
However, paragraph [0027] of Frougier discloses middle-of-line and back-end-of-line processing, which includes formation of contacts and wiring for the local interconnect structure overlying the device structure, and formation of dielectric layers, via plugs, and wiring for an interconnect structure coupled by the interconnect wiring with the functional gate structure 44 and source/drain regions 40 of the field-effect transistor 50.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Frougier with this particular design choice in order to potentially provide reduced gate resistance, improved switching speed, reduced gate delay spread, and provides increased flexibility for layout and scaling of the device.
Allowable Subject Matter
Claims 13 is objected to for being allowable subject matter dependent upon a rejected claim because the prior art uncovered does not disclose, teach or suggest a dielectric layer located on top of the first nanosheet transistor column, the second nanosheet transistor column, the third nanosheet transistor column, the dielectric cap, and the frontside contact, wherein the dielectric layer is located between the second gate and the frontside contact. Specifically, Fig. 10 of Frougier does disclose dielectric layer 30 which is located on top of the first nanosheet transistor column, the second nanosheet transistor column, the third nanosheet transistor column and the dielectric cap, but it does not explicitly disclose the same for the frontside contact, nor does it explicitly disclose the dielectric layer being located between the second gate and the frontside contact. Further, there does not appear to be a motivation to modify Frougier further in this regard given this design choice is narrowly tailored and expands upon modifications already made to Frougier in claim 12 from which claim 13 depends. Claim 14 is also objected to for being allowable subject matter dependent upon a rejected claim for depending upon claim 13.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: each of US 10,103,238 B1 to Zang et al., US 10,014,390 B1 to Bouche et al., and US 2019/0198381 A1 to Park et. al each disclose related structures and orientations of nanosheets, spacers and airgaps in FET devices.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818