DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 21, 28, and 35 have been amended.
Claims 21-23, 25-30, 32-37, 39, and 40 have been examined.
The specification objections in the previous Office Action have been addressed and are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 8, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-23, 28-30, and 35-37 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 5,933,650 by van Hook et al. (hereinafter referred to as “van Hook”) in view of US Publication No. 2018/0210733 by Stephens et al. (hereinafter referred to as “Stephens”) in view of US Publication No. 2017/0262282 by Ould-Ahmed-Vall et al. (hereinafter referred to as “Ould”).
Regarding claims 21, 28, and 35, taking claim 21 as representative, van Hook discloses:
a system, comprising: a processor configured to execute a vector instruction to generate an output vector from a first source vector and a second source vector, wherein the output vector, the first source vector and the second source vector individually comprise a plurality of data lanes, wherein individual data lanes of the plurality of data lanes respectively comprise a plurality of bits, wherein the vector instruction comprises an immediate operand…,and wherein to execute the vector instruction the processor is configured to (van Hook discloses, at Figure 2 and col. 4, lines 33-49, a system, method, and media comprising using a processor that executes vector instructions, which discloses a plurality of data lanes that respectively comprise a plurality of bits . As disclosed at Figure 5 and related description, e.g., col. 7, lines 9-18 and lines 59 et seq., the vector instructions include an alignment instruction that generates an output vector from first and second input vectors and that specifies an immediate operand.):
extract two or more data lanes from a concatenation of the first source vector and the second source vector starting at an offset greater than zero, according to the extraction width of data lanes …wherein the output vector comprises the extracted data lanes including at least one data lane of the first source vector and at least one data lane of the second source vector (van Hook discloses, at Figure 5, extracting an output vector of elements starting at an offset in the first source and continuing into the second source, which discloses a concatenation of the first source vector and the second source vector.); and
write the extracted output vector to a vector register of the processor (van Hook discloses, at Figure 5, writing the extracted vector to an output register.).
van Hook does not explicitly disclose the aforementioned immediate operand specifies the extraction width and add one or more data lanes containing respective zero values to an end of the output vector to generate an extracted output vector.
However, in the same field of endeavor (e.g., data extraction) Stephens discloses:
an extraction width is identified as an operand of the instruction (Stephens discloses, at Figure 9D and related description, a source register that specifies the number of elements to extract, which discloses specifying the extraction width in as a value operand of the instruction.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify van Hook to include an extraction width in an immediate operand in order to improve performance by increasing flexibility and reducing the need to access additional locations to determine the extraction width.
Also in the same field of endeavor (e.g., vector instructions) Ould discloses:
add one or more data lanes containing respective zero values to an end of the output vector (Ould discloses, at ¶ [0048], adding zeros to unused fields of a vector.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify van Hook to include using fewer bits and zero masking in order to improve performance by increasing flexibility regarding vector sizes.
Regarding claims 22, 29, and 36, taking claim 22 as representative, van Hook, as modified, discloses the elements of claim 21, as discussed above. van Hook also discloses:
wherein the first source vector and the second source vector are accessed from respective source vector registers of the processor identified by respective operands of the vector instruction (van Hook discloses, at Figure 5, accessing the source vectors in registers, which discloses vector registers and identifying the vector registers. Identifying the vector registers as operands of the vector instruction is implicit. See also col. 8, lines 2-3.).
Regarding claims 23, 30, and 37, taking claim 23 as representative, van Hook, as modified, discloses the elements of claim 21, as discussed above. van Hook also discloses:
wherein the data lane offset is identified as an operand of the vector instruction (van Hook discloses, at Figure 5, identifying a first bit of the starting byte address, i.e., the data lane offset. Identifying the offset as an operand of the vector instruction is implicit. See also col. 8, lines 2-3.).
Allowable Subject Matter
Claims 25-27, 32-34, and 39-40 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowability. The prior art of record, alone or in combination, fails to teach or render obvious the following subject matter recited in each of claims 25, 32, and 39, when considered in combination with the other limitations in those claims: “wherein the vector instruction is executed as part of performing a convolution on a vector, wherein the output vector is a left source vector for the convolution, wherein the second source vector is a center source vector for the convolution, and wherein to perform the convolution, the processor is further configured to: load a plurality of source vector registers with respective source vectors of the vector including the first source vector, the second source vector and a third source vector; execute another vector instruction to generate a right source vector from the second source vector and the third source vector, wherein to execute the other vector instruction the processor is configured to: concatenate the second source vector and the third source vector to generate another combined source vector; extract the right source vector from the other combined source vector starting at another data lane offset, wherein the right source vector comprises at least one data lane of the second source vector and at least one data lane of the third source vector; and write the right source vector to another vector register of the processor; load a kernel vector comprising a plurality of weighting values including a center weighting value, a left weighting value and a right weighting value; and generate one or more output vectors respectively comprising weighted sums of a plurality source vectors including the left source vector, the center source vector and the right source vector, wherein to generate a particular output vector of the one or more output vectors, the processor is configured to execute a particular vector instruction to: load a scalar weighting value from a lane of the kernel vector, the lane specified to the particular vector instruction according to the particular output vector and a particular source vector of the plurality of source vectors specified as an operand of the particular vector instruction; scale respective ones of a plurality of data lanes of the particular source vector by the loaded scalar weighting value to generate a scaled vector; add the scaled vector to an accumulator vector stored in a vector accumulator to generate a new output vector; and store the new output vector in the vector accumulator.”
Response to Arguments
On pages 12-13 of the response filed January 8, 2026 (“response”), the Applicant argues, “In the rejection of the extraction width feature, the Action cites Stephens which discloses a Splice instruction in Figure 2 that performs an extraction of data according to predicate (Psp) register. Stephens further discloses in FIGs. 9A - 9D alternative embodiments to the Psp register for controlling a Splice instruction, with the Action citing Figure 9D as disclosing a length (width) and a starting element in separate control registers. While Stephens discloses register operands in the various embodiments of Figures 2 and 9A - 9D, the present claim recites an extraction width feature specified as an immediate operand of the instruction itself. Applicant respectfully submits that the value operand feature recited in the claim is a meaningful distinction over Stephens because it allows the instruction itself to be encoded to include the width data, preventing additional instructions from being needed to load a width value into control registers. As neither Van Hook nor Quid are cited for, nor do they disclose, an extraction width encoded as an immediate operand of a vector instruction, Applicant respectfully submits that the combination of references fails to teach or suggest a processor is configured to extract two or more data lanes, from a concatenation of the first source vector and the second source vector starting at an offset greater than zero, according to the extraction width of data lanes specified in the immediate operand of the vector instruction, wherein the vector instruction comprises an immediate operand specifying an extraction width of data lanes, as claimed.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive in part. Please see above for new grounds of rejection of the amended claims. Stephens discloses an instruction having an operand that identifies a register in which an extraction width is stored. See, e.g., Figure 9D and related description. Stephens does not explicitly disclose including the extraction width as an immediate operand. However, van Hook explicitly discloses using immediate operands. See, e.g., Figure 5 and related description. Together the combination discloses all elements of Applicant’s claims.
The decision of whether to directly specify an operand value as an immediate operand or to indirectly specify the operand value is based on well-known tradeoffs, the evaluation of which is determined by circumstances. These evaluations are within the skill of those of ordinary skill in the art. The advantages include those argued by the Applicant above, namely the ability to specify all operands in a limited set of registers. This avoids the need to tie up additional registers storing operands. Of course, the downside is that there are fewer bits available in the instruction word to be used for other purposes. It depends on design objectives which implementation is more desirable.
Again, immediate operands and their use are notoriously well-known, and whether to use an immediate or an indirect specification is an obvious design choice. Accordingly, the Examiner maintains that it would have been obvious not only to modify van Hook’s instructions to include an extraction width, as disclosed by Stephens, but also to specify the extraction width using an immediate operand, as disclosed by van Hook.
On pages 13-14 of the response the Applicant argues the remaining claims are allowable for similar reasons.
Though fully considered, the Examiner respectfully disagrees. The remarks and rejections presented above apply similarly to these claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAWN DOMAN/Primary Examiner, Art Unit 2183
Prosecution Insights