Prosecution Insights
Last updated: April 19, 2026
Application No. 18/472,541

CIRCUIT BOARD, IMAGE FORMING APPARATUS, MOUNTING METHOD ONTO CIRCUIT BOARD, AND METHOD OF MANUFACTURING PLURALITY OF IMAGE FORMING APPARATUS

Non-Final OA §102§112
Filed
Sep 22, 2023
Examiner
EGOAVIL, GUILLERMO J
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Canon Kabushiki Kaisha
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
574 granted / 640 resolved
+21.7% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
664
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.0%
+4.0% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102 §112
DETAILED ACTION This Office Action is in response to an application that was filed on 09/22/2023. Claims 1-12 are presented for examination consideration. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings Objections The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s): The limitation phrase “region is provided on a surface on an opposite side” in the limitation “wherein the region is provided on a surface on an opposite side of a surface on which the first semiconductor device and the second semiconductor device are to be mounted” claimed in claim 4 must be shown in order to make structural relation with the other limitation structures. The following items in the limitation describing the method limitations “preparing a first image forming apparatus including a first circuit board; ; arranging, on the first circuit board, a first semiconductor device configured to execute a first function and a second function; and arranging, on the second circuit board, a second semiconductor device configured to execute the first function and a component configured to form a circuit configured to execute the second function, wherein the first circuit board further includes a region in which the second semiconductor device of the second image forming apparatus is arrangeable, and a region in which the component of the second image forming apparatus is arrangeable, and wherein the second circuit board further includes a region in which the first semiconductor device of the first image forming apparatus is arrangeable” claimed in the method independent claim 12 must be shown: first image forming apparatus first circuit board second image forming apparatus second circuit board region of first circuit board region of second circuit board No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification Objections The disclosure is objected to because of the following informalities: One skilled in the arts would NOT have full appreciation of the method in independent claim 12 given the filed disclosure. Appropriate correction is required as well as no new matter should be entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. In claim 12, the following method limitations are confusing: “Preparing a first image forming apparatus including a first circuit board”. “Preparing a second image forming apparatus including a second circuit board”. “Wherein the first circuit board further includes a region in which the second semiconductor device of the second image forming apparatus is arrangeable”. “Wherein the second circuit board further includes a region in which the first semiconductor device of the first image forming apparatus is arrangeable”. Specifically, the following items in the claim must be shown to establish the arrangeable relationship between the “region of first circuit board” and the “second semiconductor device” of the “second image forming apparatus” & the arrangeable relationship between the “region of second circuit board” and the “first semiconductor device” of the “first image forming apparatus”: first image forming apparatus first circuit board second image forming apparatus second circuit board region of first circuit board region of second circuit board Since the “cited items” are NOT designated as a designated item numbers in Drawings, then the Drawings does not support the claim resulting in GAP & ENABLING issues. Though, the claim is supported in paragraph ¶[0009] of the PgPub, the limitation structures of the “cited items” needs to be ITEM DESIGNATED in order to establish CONSISTENCY between the structures annotated in the cited method limitations & the filed enclosure. Therefore, one of ordinary skill in the art would NOT be reasonably apprised of the scope of the method of “independent claim 12” in RELATION to the Drawings. Examiner’s Reason for Allowance of Independent Claim 1 and Dependent Claims 2-3 and 5-8. Independent Claim 1 has been fully considered and is allowed due to define the following structural limitations: “Where the circuit board comprises a region in which a component configured to form a circuit for achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device to be mounted”. “Where the component is prevented from being mounted in the region in the case where the first semiconductor device is mounted”. “The component is mounted in the region in the case where the second semiconductor device is mounted”. Examiner’s Reason for Allowance of Independent Claim 9 and Dependent Claim 10 Independent Claim 9 has been fully considered and is allowed due to define the following structural limitations: “Where the circuit board comprises a region in which a component configured to form a circuit for achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device to be mounted”. “Where the component is prevented from being mounted in the region in the case where the first semiconductor device is mounted”. “The component is mounted in the region in the case where the second semiconductor device is mounted”. Examiner’s Reason for Allowance of Independent Claim 11 Method Independent Claim 11 has been fully considered and is allowed due to define the following structural limitations: “The circuit board having the region in which a component for use in achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device to be mounted”. “The mounting method is comprised of preventing the component from being mounted in the region in the case where the first semiconductor device is mounted”. “Mounting the component in the region in the case where the second semiconductor device is mounted”. Allowable Subject Matter Claims 1-3 and 4-11 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding independent claim 1, the prior art taken either singularity or in combination fails to anticipate or fairly suggest the limitations of the independent claim, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper. The prior art fails to teach a circuit board…wherein the circuit board comprises a region in which a component configured to form a circuit for achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device is to be mounted, and wherein the component is prevented from being mounted in the region in a case where the first semiconductor device is mounted, and the component is mounted in the region in a case where the second semiconductor device is mounted, as recited in combination in independent claim 1. After careful review of the specification and the claim in the application and a search of the prior art, considering the claim as a whole, the aforementioned recited limitations in combination in independent claim 1, it is believed to render the claim individually patentable and the claims respectively dependent thereto patentable over the prior art of record. Therefore, claims 2-3 and 5-8 are allowed. Regarding independent claim 9, the prior art taken either singularity or in combination fails to anticipate or fairly suggest the limitations of the independent claim, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper. The prior art fails to teach an image forming apparatus comprising: …wherein the circuit board includes a region in which a component configured to form a circuit for achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device is to be mounted, and wherein the component is prevented from being mounted in the region in a case where the first semiconductor device is mounted, and the component is mounted in the region in a case where the second semiconductor device is mounted, as recited in combination in independent claim 9. After careful review of the specification and the claim in the application and a search of the prior art, considering the claim as a whole, the aforementioned recited limitations in combination in independent claim 9, it is believed to render the claim individually patentable and the claim respectively dependent thereto patentable over the prior art of record. Therefore, claim 10 is allowed. Regarding independent claim 11, the prior art taken either singularity or in combination fails to anticipate or fairly suggest the limitations of the independent claim, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper. The prior art fails to teach a mounting method onto a circuit board…the circuit board having a region in which a component for use in achieving a function incorporated in the first semiconductor device but not incorporated in the second semiconductor device is to be mounted, the mounting method comprising preventing the component from being mounted in the region in a case where the first semiconductor device is mounted, and mounting the component in the region in a case where the second semiconductor device is mounted, as recited in combination in independent claim 11. After careful review of the specification and the claim in the application and a search of the prior art, considering the claim as a whole, the aforementioned recited limitations in combination in independent claim 11, it is believed to render the claim individually patentable over the prior art of record. Examiner’s Note Claim 4 would be allowable if rewritten or amended to overcome the drawing objections set forth in this Office Action, where claim 4 is dependent on claim 1. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUILLERMO J EGOAVIL/Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 22, 2023
Application Filed
Mar 10, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

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WIRING BOARD AND SEMICONDUCTOR PACKAGE
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Patent 12575028
WIRING CIRCUIT BOARD
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
98%
With Interview (+8.5%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allow rate.

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