Prosecution Insights
Last updated: July 17, 2026
Application No. 18/472,725

SYSTEMS AND METHODS FOR IMPLEMENTING INTEGRATED CIRCUIT DESIGN

Non-Final OA §101
Filed
Sep 22, 2023
Examiner
MEMULA, SURESH
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
812 granted / 926 resolved
+27.7% vs TC avg
Minimal -0% lift
Without
With
+-0.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
12 currently pending
Career history
942
Total Applications
across all art units

Statute-Specific Performance

§101
9.9%
-30.1% vs TC avg
§103
26.9%
-13.1% vs TC avg
§102
51.0%
+11.0% vs TC avg
§112
8.6%
-31.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 926 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 16-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to nonstatutory subject matter. Functional descriptive material, such as computer programs or data structures, are nonstatutory, per se, because they are not physical “things” and they are not capable of causing functional change in the computer. To qualify as statutory (MPEP §2106.01), the claimed functional descriptive material: (1) Must be directed to functional descriptive material. In other words, the functional descriptive material must impart functionality when employed as a computer component by a computer system, and cannot be directed to nonfunctional descriptive material, such as but not limited to music, computer listings, and a compilation or mere arrangement of data; and (2) Must be embodied on a non-transitory computer-readable storage medium (also called machine readable medium and other such variations), so as to define a structural and functional interrelationship between the functional descriptive material and a computer system which permits the functional descriptive material’s function to be realized. Moreover, the claims may only be directed to non-transitory storage medium, and the storage medium may not be directed to nonstatutory transitory embodiments such as signal waves, transmission media and the like. See: In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007). Presently, claims 16-20 fail to comply with (2) above. Neither the computer program product nor the computer-readable program medium code necessitates a non-transitory medium. Allowable Subject Matter Claims 1-15 are allowed. Claims 16-20 would be allowed if amended to overcome the § 101 rejections set forth above. Claims 1-12 and 13-15, and potentially claims 16-20, are allowable because the prior art of record does not teach or suggest a system, method, or CRM having all the combinations of steps or elements as recited in and required by independent claims 1, 13, and 16, particularly including, among other things, the following: In claim 1 and similarly recited claims 13 and 16, wherein the first bump map indicates respective locations of a plurality of first bump structures of the first semiconductor die, and the second bump map indicates respective locations of a plurality of second bump structures of the second semiconductor die; wherein, in the first bump map, a first subset of the first bump structures configured for transmitting signals to the second semiconductor die and a second subset of the first bump structures configured for receiving signals from the second semiconductor die are disposed symmetrically to each other with respect to an X-axis or a Y-axis of the first bump map; and wherein, in the second bump map, a first subset of the second bump structures configured for transmitting signals to the first semiconductor die and a second subset of the second bump structures configured for receiving signals from the first semiconductor die are disposed symmetrically to each other with respect to an X-axis or a Y-axis of the second bump map. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SURESH MEMULA/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Sep 22, 2023
Application Filed
Nov 20, 2023
Response after Non-Final Action
Jul 01, 2026
Non-Final Rejection mailed — §101 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
87%
With Interview (-0.3%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 926 resolved cases by this examiner. Grant probability derived from career allowance rate.

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