Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/472730 filed on 09/22/23.
Summary of claims
Claims 1-8 are pending.
Claims 1-8 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Bach et al. (US Pub. 2019/0172826).
As to claim 1 the prior art teaches a selecting method of non-simplified region of 3D model of multilayer metal circuit structure, which is used for selecting a first non-simplified region from a complete 3D model of a layout design of a multilayer metal circuit structure, said complete 3D model containing a plurality of layout layers, the selecting method of said first non-simplified region comprising at least one of the following selecting modes:
a first selecting mode, comprising the steps of: searching a soldering pad group in a surface layer of said layout layers of said complete 3D model, said soldering pad group comprising a plurality of ground pads and at least one signal I/O pad (see fig 1-2 paragraph 0057-0059);
searching a predetermined number of said ground pads around a periphery of said at least one signal I/O pad by taking said at least one signal I/O pad as a center, and selecting an area enveloping said predetermined number of said ground pads and said at least one signal I/O pad as a first area (see fig 1-2 paragraph 0058-0062);
searching a layout layer having a grounding metal zone, which is located below said soldering pad group, in said layout layers of said complete 3D model (see fig 1-3 paragraph 0060-0063);
said ground pads of said soldering pad group are electrically connected to said grounding metal zone through a plurality of ground vias (see fig 1-3 paragraph 0063-0067);
said grounding metal zone further comprising at least one ground void inside; said ground vias are located around a periphery of said at least one ground void (see fig 1-3 paragraph 0066-0070);
selecting and enveloping a region having said at least one ground void and a region having said predetermined number of said ground vias as a first region (see fig 3-5 paragraph 0073-0078);
and combining said first area and said first region as said first non-simplified region; a second selecting mode, comprising the steps of: searching a soldering pad group in a surface layer of said layout layers of said complete 3D model, said soldering pad group comprising a plurality of ground pads and at least one signal I/O pad (see fig 3-5 paragraph 0076-0081);
searching a signal trace electrically connected to said at least one signal I/O pad and coplanar with said at least one signal I/O pad in said surface layer, and searching a signal via electrically connected to the signal trace in said layout layers, wherein said signal via passes through a Mth layer to a Nth layer in said layout layers, and both of M and N are positive integers and M is less than N (see fig 4-7 paragraph 0080-0085);
and in a range from a layer above the Mth layer to a next layer below the Nth layer in said layout layers, searching a predetermined number of said ground vias that are adjacent to said signal via layer by layer with said signal via as a center, then enveloping the predetermined number of said ground vias and said signal via as said first non-simplified region (see fig 4-7 paragraph 0083-0088);
a third selecting mode, comprising the steps of: searching a layout layer having a signal trace and a first coplanar grounding metal zone on one side of said signal trace in said layout layers of said complete 3D model, said first coplanar grounding metal zone extending along said signal trace; dividing said signal trace into a plurality of signal trace units (see fig 4-9 paragraph 0090-0096);
taking each of said signal trace units as a center one by one, in an area of said first coplanar grounding metal zone, searching a layout layer having a first reference grounding zone and searching a predetermined number of first ground vias electrically connecting said first coplanar grounding metal zone and said first reference grounding zone layer by layer in said layout layers, enveloping said predetermined number of said first ground vias and each of said signal trace units as a first non-simplified region unit (see fig 4-10 paragraph 0094-0100);
and combining each of said first non-simplified region units and said signal trace in each layer of said layout layers, and selecting a region combining each of said first non-simplified region units and said signal trace as said first non-simplified region (see fig 1-3 paragraph 0099-0106);
a fourth selecting mode, comprising the steps of: in said layout layers of said complete 3D model, searching a layout layer having a first grounding metal zone, a ground void inside said first grounding metal zone, a signal trace located on one side of said ground void, and a second grounding metal zone located on an opposite side of said ground void (see fig 4-6 and 10-14 paragraph 0110-0116);
searching a predetermined number of ground vias around said ground void and electrically connecting said first grounding metal zone and said second grounding metal zone (see fig 4-6 and 11-15 paragraph 0115-0119);
and enveloping said signal trace, a region around said ground void containing said predetermined number of said ground vias, and said second grounding metal zone, selecting the enveloped region as the first non-simplified region (see fig 4-6 and 11-15 paragraph 0120-0126).
As to claim 2 the prior art teaches wherein in said second selecting mode, selecting one of the ground vias among said predetermined number of said ground vias that is the farthest from said signal via, defining a distance between said signal via and said ground via that is the farthest from said signal via as a selecting radius, and selecting said first non-simplified region according to said selecting radius (see fig 3-5 paragraph 0077-0084).
Allowable Subject Matter
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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