Attorney’s Docket Number: T103430US01
Filing Date: 09/22/2023
Claimed Priority Date: N/A
Applicants: Höhenberger et al
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the election filed on 01/08/2025
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s elections without traverse of Group I Invention, directed to a device, in the reply filed on 08/03/2026, is acknowledged. Accordingly, claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 2 recites “the corrugated dielectric structure having a first surface on a planar top surface of the semiconductor substrate”, then later in Claim 3 recites “a third conductive layer between the semiconductor substrate and the first corrugated conductive layer.” Claim 2 is recited as the dielectric layer (i.e. 122 in Fig 1 of the instant application) having a surface on the surface of the semiconductor substrate (i.e. 102), while none of the figures in the disclosure show this arrangement. Further, according to claim 3, which necessarily refers directly back to claim 2, the third conductive layer would also be located between the corrugated dielectric structure and the semiconductor substrate, which is impossible as claim 2 is recited. For the purpose of examination, the claim will be construed as reciting -- the corrugated dielectric structure having a first planar surface on a side facing the semiconductor substrate --, as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant.
Claims 3-4 depend from claim 2, thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 13, 16 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Joo et al (US 20030020122 A1, Hereinafter Joo).
Regarding Claim 1, Joo (e.g., Abstract and Figure 1A-1C, [0041]-[0047]) shows all aspects of the instant invention, including, an integrated circuit (IC) comprising:
first (130, “wrinkled layer 130 can provide an integrated circuit electrode” ) and second (upper electrode 160) corrugated conductive layers over a semiconductor substrate (integrated circuit substrate 110); and
a corrugated dielectric layer between the first and second corrugated conductive layers (150).
Regarding Claim 5, Joo shows the corrugation of layers is in the shape of a sinusoidal wave function.
Regarding Claim 13, Joo (e.g., Abstract and Figure 26A and 26B, [0041]-[0047]) shows all aspects of the instant invention, including, an integrated circuit (IC) comprising:
a parallel plate capacitor (226) over a semiconductor substrate (202), the parallel plate capacitor comprising:
a first corrugated conductive layer (130, “wrinkled layer 130 can provide an integrated circuit electrode” ) and second (upper electrode 160) corrugated conductive layers over the semiconductor substrate (110); and
a corrugated dielectric layer between the first corrugated conductive layer and the second corrugated conductive layer (150 ).
Regarding Claim 16, see comments from claim 5, as they would be considered repeated here.
Claims 1-4,13-15 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Suo et al (US 20190051596 A1 Hereinafter Suo).
Regarding Claim 1, Suo (e.g., Figure 2A-2F, 4 [0001]-[0035]) shows all aspects of the instant invention, including, an integrated circuit (IC) comprising:
first and second corrugated conductive layers over a semiconductor substrate (substrate 202); and
a corrugated dielectric layer between the first and second corrugated conductive layers (MIM stack is a metal-insulator-metal [0023]).
Regarding Claim 2, Suo further shows the following:
a corrugated dielectric structure (208 and 218 are polymer layers made of polyimide, a common dielectric [0017]), between the semiconductor substrate (202) and the first corrugated conductive layer (bottom metal of MIM stack 226), the corrugated dielectric structure having a first planar surface on a side facing the semiconductor substrate (218 and 208 have a planar surface facing 202) and a second surface touching the first corrugated conductive layer (top surface of the polymer layers touch the bottom of the MIM stack).
Regarding Claim 3, Suo further shows a third conductive layer (206) between the semiconductor substrate and the first corrugated conductive layer, the first corrugated conductive layer contacting the third conductive layer through a trough of the corrugated dielectric structure (Fig 2F, the bottom trough of the MIM stack contacts 204):
Regarding Claim 4, Suo further shows the following:
an interconnect dielectric layer (234 polymer layer may be a polyimide) over the third conductive layer and the second corrugated conductive layer;
a first conductive via through the interconnect dielectric layer to the third conductive layer (Vias and pads 230, 240,228,214,212 filled with a conductive material provide an electrical connection to 206 [0024]); and
a second conductive via through the interconnect dielectric layer to the second corrugated conductive layer (contact 244 is in electrical contact with top metal layer of MIM stack [0024]).
Regarding Claim 13, Suo (e.g., Figure 2A-2F, 4 [0001]-[0035]) shows all aspects of the instant invention, including, an integrated circuit (IC) comprising:
a parallel plate capacitor (226) over a semiconductor substrate (202), the parallel plate capacitor comprising:
a first corrugated conductive layer and a second corrugated conductive layer over the semiconductor substrate (MIM stack 226); and
a corrugated dielectric layer between the first corrugated conductive layer and the second corrugated conductive layer (MIM stack is a metal-insulator-metal [0023] ).
Regarding Claim 14, Suo further shows the following:
a third conductive layer over the semiconductor substrate (metal layer 206); and
a corrugated dielectric structure over the third conductive layer (208 and 218 are polymer layers made of polyimide, a common dielectric), the corrugated dielectric structure having a corrugated upper surface, the first corrugated conductive layer being over the corrugated upper surface of the corrugated dielectric structure (First conductive layer of MIM stack 226 is touching 218 and 208), the first corrugated conductive layer contacting the third conductive layer through a trough of the corrugated upper surface of the corrugated dielectric structure (Bottom conductive layer contacts 206).
Regarding Claim 15, See comments from claim 4 above, as they would be considered repeated here.
Claims 1, 10, 13 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Yin et al (US 20200176557 A1 Hereinafter Yin).
Regarding Claim 1, Yin (e.g., Figures 1-7, [0001]-[0070]) shows all aspects of the instant invention, including, an integrated circuit (IC) comprising:
first (Fig 5A , bottom electrode layer 203 ) and second (middle electrode layer 303) corrugated conductive layers over a semiconductor substrate (integrated circuit substrate 101); and
a corrugated dielectric layer between the first and second corrugated conductive layers (first capacitor insulating layer 301).
Regarding Claim 10, Yin shows a transistor (active device 102) that may be connected to the capacitor via conductive lines and metallization layers ([0080])
Regarding Claim 13, Yin (e.g., Figures 1-7, [0001]-[0070]) shows all aspects of the instant invention, including, an integrated circuit (IC) comprising:
a parallel plate capacitor over a semiconductor substrate (101), the parallel plate capacitor comprising:
a first corrugated conductive layer and a second corrugated conductive layer over the semiconductor substrate (Fig 5A either two of 203,303,503); and
a corrugated dielectric layer between the first corrugated conductive layer and the second corrugated conductive layer (301 or 401).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yin.
Regarding claim 7, Yin shows a parallel plate capacitor on a substrate with a corrugated stack of conductive layers separated by the dielectric layers with angled side surfaces similar to the instant invention.
While Yin does not explicitly define a ratio of the surface area of the metal layers vs, a lateral surface area, it does show (Fig 6A [0052]) that the corrugated layers with angled surfaces provide for a greater surface area resulting in a significant capacitance gain.
Further, with respect to the ratio of surface area, Yin teaches that the surface area of the corrugated layers is a variable of importance that would increase capacitance of a parallel plate structure. Yin also teaches using empirical data (Fig 5B [0052]-[0053]) that the depth of the trenches (hence larger surface area) may be adjusted to increase capacitance while maintaining a small footprint. In the instant application, the disclosure does not show specific data on criticality of the ratio and quantitative evidence on improved function of the device compared to prior art. To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960).MPEP 716.02 (d)
Accordingly, the specific claimed proportion of the surface area of the corrugated upper surface is at least one and a half times larger than a lateral footprint of the corrugated upper surface, absent any criticality, is only considered to be the “optimum” proportion of surface area disclosed by Yin that a person having ordinary skill in the art would have been able to determine using routine experimentation based, among other things, on the capacitance, device size, manufacturing costs, etc. (see Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as a corrugated structure of the parallel plate capacitor is used, as already suggested by Yin .
Since the applicant has not established the criticality (see next paragraph below) of the claimed proportion, it would have been obvious to one of ordinary skill in the art to use these values in the structure of Lin.
CRITICALITY- See MPEP 2144.05 and 716.02 (d)
The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 8, Yin also shows height from peak to trough (depth of trench) may be at least 1500A (150nm) or greater, and that a greater trench depth results in greater surface area and greater capacitance gain.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05(I).
Regarding claim 9, Yin (Fig 6A, 5B, [0050]-[0054]) shows a parallel plate capacitor on a substrate with a corrugated stack of conductive layers separated by the dielectric layers with angled side surfaces similar to the instant invention, including peaks and troughs.
Yin also shows the width of the trenches may be at least 0.5 um (500nm) to a height of the trough to peak (ie depth of trench ) to be at least 1500A resulting in a ratio of height to width of at least 10% (ratio of Yin is 33%).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). "[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05(I).
Regarding Claim 18, See comments from Claim 7 as they would be considered repeated here.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Joo in view of Chen et al (US 6077742 A, Hereinafter Chen ).
Regarding Claim 12, While Joon shows a corrugated capacitor with a dielectric layer, it does not show a dielectric layer comprising silicon oxide.
Chen (Fig 1-7 Col 2), on the other hand and in a related field of capacitors in a IC structure teaches that silicon oxide is a material to be used as a dielectric in a parallel plate capacitor. Since Silicon oxide is a well-known dielectric used in semiconductor applications, it would have been obvious at the time of the invention to one of ordinary skill in the art to have the capacitor dielectric of Joo comprising the silicon oxide because it is recognized in the semiconductor art for its use as a dielectric, as taught by Chen, and because selecting a material for its known conventional use would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 6, 11, 17 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Several references of record (i.e. KR 10 2003 017 910 A, CN 1 04 701 314 A, DE 10 2012 003 545 A1) are applicable to rejecting claims 1 and 13 at least but have not been included in this OA for the sake of brevity.
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/ANEESA RIAZ BAIG/
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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