DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In view of applicant’s amendments and arguments filed on March 19, 2026, the objection of the title as stated in the Office Action mailed on January 6, 2026 has been withdrawn.
Applicant has incorporated certain features from allowable claim 2; however, Applicant has failed to incorporate all of the features of the allowable subject matter identified in the previous Office Action. In particular, the limitation that “the second gate electrode includes an oxide semiconductor material that is conductive” has not been incorporated. Accordingly, the amendment to claim 1 is rendered moot in view of the new or modified ground of rejection set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2022/0045241; hereinafter “Kim”) in view of Park et al. (US Pub. 2014/0299884; hereinafter “Park”), and further in view of Kikuchi et al. (US Pub. 2020/0111433; hereinafter “Kikuchi”).
Regarding Claim 1, Kim discloses a thin film transistor substrate, comprising: a substrate 11 including a display area (DPA) and a non-display area (NDA) adjacent to the display area (DPA) (page 3, paragraph 57; see fig. 1); a pixel driving thin film transistor T1 in the display area (DPA) (see fig. 4); a buffer layer 12 (page 5, paragraph 80) on the substrate 11 (page 3, paragraph 58; see fig. 4), the buffer layer 12 including at least one inorganic insulating layer (silicon oxide; page 5, paragraph 80); a second insulating layer 13 (page 6, paragraph 85), the second insulating layer 13 including at least one inorganic insulating layer (silicon oxide; page 6, paragraph 85), wherein the pixel driving thin film transistor T1 comprises: a first active pattern (ACT) (page 5, paragraph 81); a first gate electrode G1 (page 5, paragraph 81) on the second insulating layer 13 (See fig. 4), the first gate electrode G1 overlapping with the first active pattern (ACT) (page 5, paragraph 81; see fig. 4); a first light shielding pattern (BML) (page 5, paragraph 79) under the first active pattern (ACT) (see fig. 4), the first light shielding pattern (BML) overlapping with the first active pattern (ACT) (page 5, paragraph 79; see fig. 4); and a first source electrode S1 and a first drain electrode D1 electrically connected to the first active pattern (ACT) (page 6, paragraph 90; see fig. 4), wherein the first light shielding pattern (BML) is electrically connected to the first source electrode S1 (page 6, paragraph 90; see fig. 4), wherein the first active pattern (ACT) includes an oxide semiconductor material (pages 5-6, paragraph 83),
Kim fails to disclose explicitly wherein a first insulating layer on the buffer layer, the first insulating layer including at least one inorganic insulating layer; and a gate driving thin film transistor on the non-display area, wherein the gate driving thin film transistor comprises: a second active pattern on the buffer layer; and a second gate electrode on the first insulating layer, wherein the second active pattern includes a polycrystalline semiconductor material.
However, Park discloses wherein a buffer layer 62 such as silicon dioxide (page 3, paragraph 43) is deposited on a substrate 60 (page 3, paragraph 43), and a dielectric layer 66, a silicon oxide, as a thin-film transistor buffer layer is deposited on the buffer layer 62 (page 3, paragraph 45; see fig. 12), and wherein a thin-film transistor device can be formed on buffer layer 66 (page 3, paragraph 46). Furthermore, Kim discloses that the buffer layer 12 may have a multilayer structure (page 5, paragraph 80). Accordingly, Park’s second dielectric buffer layer 66 could be incorporated into Kim’s transistor T1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form an inorganic insulating layer on a buffer layer, as taught by Park, in order to improve electrical isolation protecting a transistor electrically and structurally.
Kim in view of Park fails to disclose explicitly wherein a gate driving thin film transistor on the non-display area, wherein the gate driving thin film transistor comprises: a second active pattern on the buffer layer; and a second gate electrode on the first insulating layer, wherein the second active pattern includes a polycrystalline semiconductor material.
However, Kikuchi discloses a gate driving TFT 10 (page 1, paragraph 7) in a peripheral region FR, which is a non-display area (page4, paragraph 70; see fig. 2), wherein the gate driving TFT comprises an active pattern 11 on a base coat layer 2 (serves as a buffer layer) (page 4, paragraphs 71 and 72; see fig. 2), a gate electrode 12 on a first insulating layer IL1 (page 4, paragraph 73; see fig. 2), wherein the active pattern 11 is a polycrystalline silicon layer (page 4, paragraph 72).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a TFT structure in a non-display area, as taught by Kikuchi, in order to isolate high-voltage switching elements from the pixel driving TFT, thereby reducing noise coupling and improving pixel operation stability.
Regarding Claim 10, Kim discloses an organic light emitting display device, comprising: a thin film transistor substrate (see fig. 4) including: a substrate 11 including a display area (DPA) and a non-display area (NDA) adjacent to the display area (DPA) (page 3, paragraph 57; see fig. 1); a pixel driving thin film transistor T1 in the display area (DPA) (see fig. 4); a buffer layer 12 (page 5, paragraph 80) on the substrate 11 (page 3, paragraph 58; see fig. 4), the buffer layer 12 including at least one inorganic insulating layer (silicon oxide; page 5, paragraph 80); a second insulating layer 13 (page 6, paragraph 85), the second insulating layer 13 including at least one inorganic insulating layer (silicon oxide; page 6, paragraph 85); and a light emitting element 30 (page 4, paragraph 69) electrically connected to the pixel thin film transistor T1 (a first alignment electrode 21 may be electrically connected to the first transistor T1; page 7, paragraph 104; and the first alignment electrode 21 may be electrically connected to the light emitting element 30; page 8, paragraph 109), wherein the pixel driving thin film transistor T1 comprises: a first active pattern (ACT) (page 5, paragraph 81); a first gate electrode G1 (page 5, paragraph 81) on the second insulating layer 13 (See fig. 4), the first gate electrode G1 overlapping with the first active pattern (ACT) (page 5, paragraph 81; see fig. 4); a first light shielding pattern (BML) (page 5, paragraph 79) under the first active pattern (ACT) (see fig. 4), the first light shielding pattern (BML) overlapping with the first active pattern (ACT) (page 5, paragraph 79; see fig. 4); and a first source electrode S1 and a first drain electrode D1 electrically connected to the first active pattern (ACT) (page 6, paragraph 90; see fig. 4), wherein the first light shielding pattern (BML) is electrically connected to the first source electrode S1 (page 6, paragraph 90; see fig. 4), wherein the first active pattern (ACT) includes an oxide semiconductor material (pages 5-6, paragraph 83),
Kim fails to disclose explicitly wherein a first insulating layer on the buffer layer, the first insulating layer including at least one inorganic insulating layer; and a gate driving thin film transistor on the non-display area, wherein the gate driving thin film transistor comprises: a second active pattern on the buffer layer; and a second gate electrode on the first insulating layer, wherein the second active pattern includes a polycrystalline semiconductor material.
However, Park discloses wherein a buffer layer 62 such as silicon dioxide (page 3, paragraph 43) is deposited on a substrate 60 (page 3, paragraph 43), and a dielectric layer 66, a silicon oxide, as a thin-film transistor buffer layer is deposited on the buffer layer 62 (page 3, paragraph 45; see fig. 12), and wherein a thin-film transistor device can be formed on buffer layer 66 (page 3, paragraph 46). Furthermore, Kim discloses that the buffer layer 12 may have a multilayer structure (page 5, paragraph 80). Accordingly, Park’s second dielectric buffer layer 66 could be incorporated into Kim’s transistor T1.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form an inorganic insulating layer on a buffer layer, as taught by Park, in order to improve electrical isolation protecting a transistor electrically and structurally.
Kim in view of Park fails to disclose explicitly wherein a gate driving thin film transistor on the non-display area, wherein the gate driving thin film transistor comprises: a second active pattern on the buffer layer; and a second gate electrode on the first insulating layer, wherein the second active pattern includes a polycrystalline semiconductor material.
However, Kikuchi discloses a gate driving TFT 10 (page 1, paragraph 7) in a peripheral region FR, which is a non-display area (page4, paragraph 70; see fig. 2), wherein the gate driving TFT comprises an active pattern 11 on a base coat layer 2 (serves as a buffer layer) (page 4, paragraphs 71 and 72; see fig. 2), a gate electrode 12 on a first insulating layer IL1 (page 4, paragraph 73; see fig. 2), wherein the active pattern 11 is a polycrystalline silicon layer (page 4, paragraph 72).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a TFT structure in a non-display area, as taught by Kikuchi, in order to isolate high-voltage switching elements from the pixel driving TFT, thereby reducing noise coupling and improving pixel operation stability.
Regarding Claim 11, Kim discloses further comprising a first planarization layer 19 (page 7, paragraph 98) on the second insulating layer 13 (see fig. 4), wherein the light emitting element 30 is disposed on the first planarization layer 19 (see figs. 4 and 5), and wherein the light emitting element 30 comprises: an anode disposed on the first planarization layer 19 (an anode exists in the light emitting element 30; page 8, paragraph 109; see figs. 4 and 5); a cathode corresponding to the anode (a cathode exists in the light emitting element 30; page 8, paragraph 109); and an organic light emitting layer 36 (page 4, paragraph 69) disposed between the anode and the cathode (a typical light emitting element has a structure in which a light emitting layer is disposed between an anode and a cathode).
Allowable Subject Matter
Claims 2-9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites the second gate electrode includes an oxide semiconductor material that is conductive.
Claim 3 recites the third active pattern includes an oxide semiconductor material, wherein the second light shielding pattern includes a semiconductor material that is conductive, and wherein the second light shielding pattern and the third gate electrode are electrically connected.
Claim 12 recites a common voltage line on the non-display area, the common voltage line providing a common voltage to the pixel driving thin film transistor; and a cathode connection electrode electrically connecting the common voltage line to the cathode.
These features in combination with the other elements of the base claim are neither disclosed nor suggested by the prior art of record.
Claims 4-9 depend from claim 3, so they are objected for the same reason.
Claims 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 13 and 20 recite forming a first light shielding pattern and a second active pattern, which are made of a first semiconductor material on the buffer layer; forming a first insulating layer on the first light shielding pattern and the second active pattern; forming a first active pattern and a second gate electrode, which are made of a second semiconductor material on the first insulating layer; forming a second insulating layer on the first active pattern and the second gate electrode.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 14-19 depend from claim 13, so they are allowed for the same reason.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHEUNG LEE/Primary Examiner, Art Unit 2812 March 31, 2026