DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to KR10-2023-0050553, for 04/18/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/22/2023 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: 3D NONVOLATILE MEMORY DEVICE INCLUDING FIRST AND SECOND PASS TRANSISTORS COUPLING GLOBAL WORD LINES TO LOCAL LINES
Claim Objections
Claim 7 is objected to because of the following informalities: The claim contains redundant language, specifically, line 19 “is coupled to any one of the plurality of first word line contacts and the first block select line contact in the first slimming region and the second slimming region,” made redundant by the further claim limitation “and is coupled to any one of the plurality of second word line contacts and the second block select line contact in the second slimming region.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11, and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2018/0268892; hereinafter known as Kim).
Regarding claim 1, Kim teaches (Fig. 4) a semiconductor memory device, comprising: a stacked body comprising a plurality of conductive lines (20, [0038]); and first pass transistors (PT1-PT3, [0053]) and second pass transistors (PT4-PT6, [0053]) configured to couple global word lines to local lines (LWL, [0024]), wherein any one of the plurality of conductive lines is a block select line (BLKWL1, [0054]), and gates of the first pass transistors and the second pass transistors are coupled to the block select line ([0054]).
Regarding claim 2, Kim teaches (Fig. 4) the semiconductor memory device according to claim 1, further comprising: a plurality of cell plugs (30, 32, 40, [0044]) extending in a direction vertical (VD) to a substrate (10, [0037]) in the stacked body.
Regarding claim 3, Kim teaches (Figs. 4-5) the semiconductor memory device according to claim 2, wherein both ends of the stacked body correspond to a first slimming region (SR1, [0046]) and a second slimming region (SR2, [0046]) in which the plurality of conductive lines (20, [0046]) have a stepped structure ([0046]).
Regarding claim 4, Kim teaches (Fig. 5) the semiconductor memory device according to claim 3, wherein the first pass transistors (PT1-3, [0053]) are disposed under the first slimming region (SR1, [0046]) and the second pass transistors (PT2-6, [0053]) are disposed under the second slimming region (SR2, [0053]). The pass transistors are shown disposed in a lower vertical direction than the slimming regions, and may be disposed in the memory block ([0054]).
Regarding claim 5, Kim teaches (Fig. 5) the semiconductor memory device according to claim 3, further comprising: a plurality of first word line contacts (CNT2, [0055]) and a first block select line contact (CNT1, [0054-0055]) coupled to the plurality of conductive lines (20, [0055]), respectively, in the first slimming region (SR1), wherein the first block select line contact and the plurality of first word line contacts extend in a direction vertical (VD) to the substrate (100).
Regarding claim 6, Kim in view of Kwon teaches (Kwon, Fig. 3C) the semiconductor memory device according to claim 5, further comprising: a plurality of second word line contacts (CNT5, [0055]) and a second block select line contact (CNT4, [0054-0055]) coupled to the plurality of conductive lines (20 [0047]), respectively, in the second slimming region (SR2), wherein the second block select line contact and the plurality of second word line contacts extend in the direction vertical (VD) to the substrate (100).
Regarding claim 7, Kim in view of Kwon teaches (Kwon, Fig. 3C) the semiconductor memory device according to claim 6, wherein each of the plurality of conductive lines (20, [0055]) is coupled to any one of the plurality of first word line contacts (CNT2, [0055]) and the first block select line contact (CNT1) in the first slimming region (SR1) and the second slimming region (SR2), and is coupled to any one of the plurality of second word line contacts (CNT5, [0055]) and the second block select line contact (CNT4) in the second slimming region (SR2).
Regarding claim 8, Kim teaches (Fig. 5) the semiconductor memory device according to claim 1, wherein the plurality of conductive lines are a plurality of word lines (WL, [0031]), a plurality of select lines (SSL, [0031]), and the block select line (BLKWL1, [0054]), respectively.
Regarding claim 9, Kim teaches (Fig. 5) the semiconductor memory device according to claim 8, wherein the block select line (BLKWL1, [0054]) is disposed adjacent to any one of the select lines (SSL, [0031]). The block select line is shown at least adjacent, though not explicitly in direct contact with the select lines.
Regarding claim 11, Kim teaches (Figs. 4-5) a semiconductor memory device, comprising: a stacked body including a plurality of conductive lines (20, [0038]), and including a stepped structure at a first end and a second end of the stacked body ([0046]); first pass transistors (PT1-PT3, [0053]) and second pass transistors (PT4-PT6, [0053]) configured to couple global word lines to local lines (LWL, [0024]); a plurality of first word line contacts (CNT2, [0055]) and a first block select line contact (CNT1, [0054-0055]) that are respectively coupled at the first end to conductive lines of a first group (LWL_G1, [0058]), among the plurality of conductive lines, and that extend in a direction vertical (VD) to a substrate; and a plurality of second word line contacts (CNT5, [0055]) and a second block select line contact (CNT4, [0054-0055]) that are respectively coupled at the second end to conductive lines of a second group (LWL_G1, [0058]), among the plurality of conductive lines, and that extend in the direction vertical (VD) to the substrate (100), wherein any one of the plurality of conductive lines is a block select line (BLKWL1, [0054]), and gates of the first pass transistors and the second pass transistors are coupled to the block select line (not pictured, [0054]).
Regarding claim 13, Kim teaches (Fig. 5) the semiconductor memory device according to claim 11, wherein the first group (LWL_G1, [0058]) includes conductive lines (CNT2, [0055]) disposed in an upper portion ([0058] among the plurality of conductive lines, and the second group (LWL_G2, [0058]) includes conductive lines disposed under the first group ([0058]).
Regarding claim 14, Kim teaches (Figs. 4-5) the semiconductor memory device according to claim 11, wherein: the first pass transistors (PT1-PT3, [0053]) are disposed under the plurality of first word line contacts (CNT5 and the first block select line contact, and the second pass transistors (PT2-PT6, [0053]) are disposed under the plurality of second word line contacts and the second block select line contact. The pass transistors are shown disposed in a lower vertical direction than the slimming regions, and may be disposed in the memory block ([0054]).
Regarding claim 15, Kim teaches (Figs. 4-5) the semiconductor memory device according to claim 11, wherein the plurality of conductive lines are a plurality of word lines (WL, [0031]) a plurality of select lines (SSL, [0031]), and the block select line (BLKWL1, [0054]), respectively.
Regarding claim 16, Kim teaches (Fig. 5) the semiconductor memory device according to claim 15, wherein the block select line (BLKWL1, [0054]) is disposed adjacent to any one of the select lines (SSL, [0031]). The block select line is shown at least adjacent, though not explicitly in direct contact with the select lines.
Regarding claim 17, Kim teaches (Fig. 4) the semiconductor memory device according to claim 11, further comprising: a plurality of cell plugs (30, 32, 40, [0044]) extending in a direction vertical (VD) to a substrate (10, [0037]) in the stacked body.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 1, 2, 11, and 17 above, and further in view of Shen et al. (US PGPub 2023/0106571; hereinafter known as Shen).
Regarding claim 10, Kim teaches (Fig. 4) the semiconductor memory device according to claim 2, wherein: each of the plurality of cell plugs includes a plurality of memory cells (30, coupled to word lines, [0042]), a plurality of select transistors (30, coupled to select line, [0042]), but does not explicitly teach and a dummy cell, and a gate of the dummy cell is coupled to the block select line.
Shen teaches (Fig. 2G) a dummy cell (144, [0058]) and a gate of the dummy cell is coupled to the block select line (conductive layer, 191, [0058]). Because Kim and Shen are both directed toward 3D NAND devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim and of Shen to include a dummy cell, and a gate of the dummy cell is coupled to the block select line, in order to prevent or reduce leakage current in the portion of the NOR memory structure buried in the conductive layers (Shen, [0058]).
Regarding claim 18, Kim teaches (Fig. 4) the semiconductor memory device according to claim 17, wherein: each of the plurality of cell plugs includes a plurality of memory cells (30, coupled to word lines, [0042]), a plurality of select transistors (30, coupled to select line, [0042]), but does not explicitly teach and a dummy cell, and a gate of the dummy cell is coupled to the block select line.
Shen teaches (Fig. 2G) a dummy cell (144, [0058]) and a gate of the dummy cell is coupled to the block select line (conductive layer, 191, [0058]). Because Kim and Shen are both directed toward 3D NAND devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim and of Shen to include a dummy cell, and a gate of the dummy cell is coupled to the block select line, in order to prevent or reduce leakage current in the portion of the NOR memory structure buried in the conductive layers (Shen, [0058]).
Regarding claim 19, Kim teaches (Fig. 4) a semiconductor memory device, comprising: a memory block (BLK1, [0023]) including a plurality of memory strings (CSTR, [0030]), each of the memory strings comprising a drain select transistor (DST, [0030]), a plurality of memory cells (MC, [0030]), and a source select transistor (SST, [0030]); first pass transistors (PT1-PT3, [0053]) disposed on a first side of the memory block, and configured to couple global word lines to local lines (LWL, [0024]) coupled to gates of the plurality of memory cells; and second pass transistors (PT4-6, [0053]) disposed on a second side of the memory block and configured to couple the global word lines to the local word lines (LWL, [0024]), wherein gates of the first pass transistors and the second pass transistors are coupled to one block select line (BLKWL1, [0054]).
Kim does not explicitly teach a dummy cell.
Shen teaches (Fig. 2G) a dummy cell (144, [0058])).
Because Kim and Shen are both directed toward 3D NAND devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim and of Shen to include a dummy cell, in order to prevent or reduce leakage current in the portion of the NOR memory structure buried in the conductive layers (Shen, [0058]).
Regarding claim 20, Kim in view of Shen teaches the semiconductor memory device according to claim 19, and a block select line, but does not explicitly teach wherein the one block select line is coupled to a gate of the dummy cell.
Shen further teaches wherein the gate of the dummy cell is coupled to a conductive line.
Because Kim in view of Shen are both directed toward 3D NAND devices it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Kim and Shen to include wherein the one block select line is coupled to a gate of the dummy cell in order to prevent or reduce leakage current in the portion of the NOR memory structure buried in the conductive layers
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 11 above, and further in view of Cho et al. (US PGPub 2008/0084729; hereinafter known as Cho).
Regarding claim 12, Kim teaches (Fig. 5) the semiconductor memory device according to claim 11, and teaches wherein the first group contains different among the plurality of conductive lines than the second group but does not explicitly teach wherein the first group includes odd-numbered conductive lines among the plurality of conductive lines, and the second group includes even-numbered conductive lines among the plurality of conductive lines.
Cho teaches wherein the first group (first odd wiring, [0065]) includes odd-numbered conductive lines (WLodd, [0065]) among the plurality of conductive lines (WL, [0065]) and the second group (first even wiring, [0065]) includes even-numbered conductive lines (WLeven, [0065]) among the plurality of conductive lines (WL).
Because Kim and Cho are both directed toward word line wiring, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim and of Cho in order to alternately control rows on opposite sides of the cell array region (Cho, [0062]).
Conclusion
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812