DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17 in the reply filed on 3/23/2026 is acknowledged.
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 11-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramanathan et al (U.S. Pub #2020/0194330).
With respect to claim 1, Ramanathan teaches a semiconductor package comprising:
a first chip (Figs. 2-3, 205 and Paragraph 28) including a first dummy region, a second dummy region (Fig. 2B, regions corresponding to 240B), and a plurality of first pads (Figs. 2-3, 372B and Paragraph 45) on a rear surface (Paragraph 25, the pads and thermal structures can be form on the back/bottom side of the chip) of the first chip in the first dummy region and the second dummy region; and
a second chip (Fig. 2-3, 215 and Paragraph 28) stacked on the rear surface of the first chip and including a plurality of bumps (Figs. 2-3, 130A and Paragraph 30) coupled to the plurality of first pads,
wherein each first pad of the plurality of first pads has a line shape (Fig. 3B, 372B) having a length coupled to at least two bumps (Fig. 3B, 130A) of the plurality of bumps.
With respect to claim 2, Ramanathan teaches the plurality of first pads (Fig. 2B, 130A; Fig. 3B, 372B) form at least one of a first line pattern, a second line pattern, or a third line pattern.
With respect to claim 3, Ramanathan teaches that at least one of the first line pattern, the second line pattern, and the third line pattern has a width of a bump of the plurality of bumps of the second chip (Fig. 3 and Paragraph 42).
With respect to claim 4, Ramanathan teaches that the first line pattern (e.g. Fig. 1, diagonal portions of 140) has a shape extending obliquely from a center of a side adjacent to an electrode region toward a corner of the first chip, wherein the electrode region separates the first dummy region and the second dummy region.
With respect to claim 5, Ramanathan teaches that the second line pattern (Fig. 3B, 372B) has a line shape that is parallel to a direction of a first side of the first chip (Fig. 3B, 205).
With respect to claim 6, Ramanathan teaches that the third line pattern (e.g. Fig. 1, 140) has a line shape that is parallel to a direction of a second side of the first chip.
With respect to claim 7, Ramanathan teaches that at least one of the first line pattern, the second line pattern, or the third line pattern includes at least one of one line formed as a line (Fig. 3B, 372B), a plurality of lines in a form of a dotted line, and a plurality of lines in a form of dashed-dotted line.
With respect to claim 8, Ramanathan teaches that at least one of the first line pattern (Fig. 3B, 372B), the second line pattern, and the third line pattern has a width of at least two bumps of the plurality of bumps (Fig. 3B, 130A).
With respect to claim 9, Ramanathan teaches the first chip includes an electrode region (Fig. 2B, corresponding to 120A), the first dummy region (Fig. 2B, 130A) is positioned at a first side (Fig. 2B, left side) of the electrode region, and the second dummy region (Fig. 2B, right side) is positioned at a second side of the electrode region, wherein the first side and the second side are opposite one another.
With respect to claim 11, Ramanathan teaches that the plurality of first pads comprise a surface layer (adhesion layer Paragraph 41; or passivation layer, Paragraph 31 and 43) covering an upper surface of the plurality of first pads.
With respect to claim 12, Ramanathan teaches that the surface layer includes at least one of a gold layer, an organic surface protection layer, or a silicon thin film layer, wherein the organic surface protection layer includes at least one of alkylbenzimidazole or diphenylimidazole, and wherein the silicon thin film layer includes at least one of silicon nitride or silicon dioxide (Paragraph 29, passivation layer).
With respect to claim 13, Ramanathan teaches that the second chip is stacked on the rear surface of the first chip using an adhesive layer provided therebetween, and the adhesive layer includes a non-conductive film (NCF) or an epoxy resin (Fig. 3, 150 and Paragraph 30).
With respect to claim 14, Ramanathan teaches that the plurality of first pads (Fig. 3, 372 and Paragraph 41) include at least one of copper, a nickel/gold alloy, a copper/nickel/gold alloy, a copper/nickel/tin alloy, or cobalt.
With respect to claim 15, Ramanathan teaches a second pad (Fig. 3A, 372A) on the rear surface of the first chip in an electrode region.
With respect to claim 16, Ramanathan teaches that the first chip includes a through silicon via (Fig. 3A, 165), and the second pad is connected to the through silicon via.
17. A semiconductor package comprising: a first chip including an electrode region, a first dummy region positioned at a first side of the electrode region, a second dummy region positioned at a second side of the electrode region, and a plurality of first pads positioned on a rear surface of the first chip in the first dummy region and the second dummy region; and a second chip stacked on the rear surface of the first chip and including a plurality of bumps coupled to the plurality of first pads, wherein a first line pattern of the plurality of first pads has a shape extending obliquely from a center of a side adjacent to the electrode region toward a corner of the first chip, and the first dummy region and the second dummy region each include two of the first line patterns symmetrically positioned in a direction of a first side of the first chip.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 17 is allowed.
The following is an examiner’s statement of reasons for allowance: the best prior art of record does not teach or fairly suggest, along with the other limitations:
a second chip stacked on the rear surface of the first chip and including a plurality of bumps coupled to the plurality of first pads,
wherein a first line pattern of the plurality of first pads has a shape extending obliquely from a center of a side adjacent to the electrode region toward a corner of the first chip, and
the first dummy region and the second dummy region each include two of the first line patterns symmetrically positioned in a direction of a first side of the first chip.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN P SANDVIK/ Primary Examiner, Art Unit 2812
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