DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-6, 9-14, and 16-23 are pending.
Claims 4 and 16 are amended.
Claims 7, 8, and 15 are cancelled.
Claim 23 is new.
Response to Arguments
Applicant's arguments, see pages 9-11, filed 07/17/2026 have been fully considered but they are not persuasive. Specifically, applicant’s argument in response to the rejections of claims 3 and 21 of 04/21/2026 under 35 U.S.C 112(a) does not overcome the rejection. One of ordinary skill in the art would not recognize what is being claimed by “wherein an amount of crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less.” See further details below.
Additionally, applicant’s arguments, see pages 11-13 in response to the rejections of claims 1, 2, 4-6, 9-14, 16-20, and 22 have been fully considered but they are not persuasive. The use of ion implantation and crystal directions in silicon carbide of Khlebnikov being directed toward remedying warpage does not preclude the use of Khlebnikov as prior art, as combination of Chen and Seok with Khlebnikov is sufficiently motivated. Khlebnikov teaches use of these crystal directions for beneficial use of electron mobility, and while this is done to reduce warpage of the resulting wafer, this does not discredit the reference as prior art, as Khlebnikov teaches a clear advantage to utilizing these crystal directions, as well as a benefit of reduction of interface dislocations in a wafer. The rejections of claim 1 and 11 are upheld. Accordingly, the rejections of dependent claims 2-6, 9, 10, 12-14, 16-20, and 22 are upheld.
Applicant’s argument against the prior art reference of Seok as unrelated to silicon carbide devices is not persuasive. Examiner notes that while Seok does not explicitly state use of silicon carbide as a substrate, this does not disqualify it as analogous prior art. Seok does teach use of “semiconductor substrates” for power devices, of which silicon carbide is a well-known option. Additionally, Seok is relied upon to teach a guard ring structure, of which use is applicable to any chosen semiconductor substrate for its disclosed benefit of providing reduction in leakage from a defect origin portion. The rejections of claims 1 and 11, and all dependent claims are upheld.
Applicant’s argument that Chen fails to teach a trench is not persuasive. In paragraph 0040, Chen teaches wherein the portion 142 may be an amorphous layer (ion-implanted region) or a trench. The rejection of claim 4 is upheld.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Specifically, regarding the claim limitation “wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less,” the specification describes an ion implantation region having a width, height, and depth, in which ion implantation is performed, in order to form crystal defects. Additionally, the extension prevention portion, which is formed by formation of crystal defects in the ion implantation region, and may be the ion implantation region having crystal defects ([0076]), has a width, height, and depth. The unit of measurement of the crystal defects, in this volumetric region, is denoted in terms of area (/cm2) in the claims and specification of the instant application, as opposed to the normal convention of a volumetric (/cm3) measurement, to denote a density of the crystal defects in the volumetric space. The instant application describes that the extension prevention portion is provided in the (11-20) direction of the semiconductor substrate, but does not describe wherein it is planar, nor does it describe wherein ion implantation is performed to provide two-dimensional crystal defects, nor that the crystal defects are, in fact, two-dimensional.
Additionally, applicant has provided three journal articles in alleged support of the claim language of claims 3 and 11:
1) "Carbon dangling-bond center (carbon Pb center) at 4H-SiC(0001)/SiO₂ interface," T. Umeda, et al., Applied Physics Letters (2020).
2) "Electron-spin-resonance and electrically detected-magnetic-resonance characterization on Ръс center in various 4H-SiC(0001)/SiO₂ interfaces," T. Umeda, et al., Journal of Applied Physics (2020).
3) "Differences between Polar-Face and Non-Polar Face 4H-SiC/SiO₂ Interfaces Revealed by Magnetic Resonance Spectroscopy," T. Umeda, et al., Defect and Diffusion Forum (2023).
Examiner does not find these references persuasive in regards to verifying that one of ordinary skill in the art would understand how to interpret claims 3 and 11. In, for example, reference 2 provided by the applicant “Electron-spin-resonance and electrically detected-magnetic-resonance characterization on Ръс center in various 4H-SiC(0001)/SiO₂ interfaces;” herein referred to as Ref 2, the authors discuss that the formation of the intrinsic interface defect was observed with “a spin density of 3-4x1012cm-2.” Spin density refers to the unpaired electron density in a molecule, representing the difference between the charge densities of electrons with alpha and beta spin. Examiner did not find substantial disclosure in Ref 2, the other provided references, nor through her own search, equating unpaired electron density 1:1 to an amount of crystal defects. Examiner would ask applicant for citation of direct correlation of these two quantities. Examiner additionally notes that, while three journal articles have been provided by applicant, they are all three written by the same set of authors, and do not necessarily show that one of ordinary skill in the art would understand the use of the claim language as provided as it does not appear to otherwise be well known in the art. Further disclosure is requested, in order to remedy this rejection, and examiner notes that applicant may contact the office for an interview regarding this subject.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, it is unclear how the phrase of claims 3 and 11 “wherein an amount of crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less,” is intended to be interpreted.
The extension prevention portion, which is formed by formation of crystal defects in the ion implantation region, and may be the ion implantation region having crystal defects ([0076]), has a width, height, and depth. The unit of measurement of the crystal defects, in this volumetric region, is denoted in terms of area (/cm2) in the claims and specification of the instant application, as opposed to the normal convention of a volumetric (/cm3) measurement, to denote a density of the crystal defects in the volumetric space. The instant application describes that the extension prevention portion is provided in the (11-20) direction of the semiconductor substrate, but does not describe wherein it is planar, nor does it describe wherein ion implantation is performed to provide two-dimensional crystal defects, nor that the crystal defects are, in fact, two-dimensional.
For purposes of examination, it will be interpreted that the claim is intended to read “5x1013/cm3 or more and 1x1016/cm3 or less.”
Claims 1, 2, 4, 9-13, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2022/0336650; herein known as Chen) in view of Seok (US PGPub 2021/0151598; herein known as Seok) and Khlebnikov et al. (US PGPub 2021/0198804; herein known as Khlebnikov).
Regarding claim 1, Chen teaches (Fig. 8) a silicon carbide semiconductor device which includes a semiconductor substrate (101, [0039]) made of silicon carbide ([0020]) and having an epitaxial region made of silicon carbide (100, [0019]) on a front surface, the silicon carbide semiconductor device comprising: an active portion (Ra, Rb, [0028]) which is provided on the semiconductor substrate wherein the element isolation portion includes an extension prevention portion (142, [0041]) which is provided to elongate along each of two opposing end sides (Fig. 8, 142 is shown extending along horizontal sides of active regions) on an upper surface of the epitaxial region (100) and wherein the extension prevention portion stops extension of interface dislocation ([0040]) of the semiconductor substrate in a (1-100 direction (Chen, 140) when the silicon carbide semiconductor device is in a wafer state (140 is provided in the horizontal and vertical substrate directions).
Chen does not explicitly teach a pressure resistant structure portion which is provided on an outer periphery of the active portion.
In analogous art, Seok teaches a pressure resistant structure portion (102, [0030]) which is provided on an outer periphery ([0030]) of the active portion (104, [0030]) on the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen and Seok in order to reduce leakage originating from defects within the active region ([0002]).
Chen in view of Seok does not explicitly teach wherein an elongation direction of the extension prevention portion is a (11-20) direction of the semiconductor substrate.
In analogous art, Khlebnikov teaches (Fig. 6A) wherein an elongation direction of the extension prevention portion is a (11-20) direction (Fig. 12, <1120>, horizontal direction, parallel to substrate) of the semiconductor substrate (11-20) direction (A-Plane 1120, parallel to 138, aligns with extension prevention portion [0076])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov in order to provide active devices along the 1120 plane, which is the plane in SiC with the highest electron mobility, which is beneficial in power devices ([0080]).
Regarding claim 2, Chen in view of Seok and Khlebnikov teaches (Chen, Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142, 0027]) includes an ion implantation region ([0027]) which has a thickness (annotated Fig. 8, t) in a depth direction (D3) of the semiconductor substrate, is provided to elongate along (Fig. 8, 142 is shown extending along horizontal sides active regions) each of the two opposing end sides on the upper surface of the epitaxial region (100), and has crystal defects (lattice structures are highly damaged to create an amorphous region, [0027]).
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Regarding claim 4, Chen in view of Seok and Khlebnikov teaches (Chen, Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142, [0027]) includes a trench structure (, [0027]) which has a thickness (annotated Fig. 8 above, t) in a depth direction (D3) of the semiconductor substrate and is provided to elongate along each the extension prevention portion (100, [0019]).
Regarding claim 9, Chen in view of Seok and Khlebnikov teaches (Chen, Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142) is provided to elongate from one end (E1) to another end (E2) of the end side (142 shown extending between edges of active areas).
Regarding claim 10, Chen in view of Seok and Khlebnikov teaches (Chen, annotated Fig. 8 above) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142) is provided on four sides (S1-S4) of the semiconductor substrate.
Regarding claim 11, Chen teaches (Fig. 8) method of manufacturing a silicon carbide semiconductor device comprising: providing a semiconductor substrate (101, [0039]) made of silicon carbide ([0020]) and having an epitaxial region made of silicon carbide on a front surface ([0019]); providing an active portion (Ra, Rb, [0028]) on the semiconductor substrate; and providing, in the element isolation portion, an extension prevention portion (142, [0041]), which stops extension of interface dislocation ([0040]), along each of two opposing end sides on an upper surface of an epitaxial region (100, [0019]) of the semiconductor substrate and wherein the extension prevention portion stops extension of the interface dislocation of the semiconductor substrate in a (1-100) direction of the semiconductor substrate when the silicon carbide semiconductor device is in a wafer state (140 is provided in the horizontal and vertical substrate directions).
Chen does not explicitly teach providing a pressure resistant structure portion on an outer periphery of the active portion.
In analogous art, Seok teaches a pressure resistant structure portion (102, [0030]) which is provided on an outer periphery ([0030]) of the active portion (104, [0030]) on the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen and Seok in order to reduce leakage originating from defects within the active region ([0002]).
Chen in view of Seok does not explicitly teach wherein the providing the extension prevention portion includes providing the extension prevention portion along a (11-20) direction of the semiconductor substrate.
In analogous art, Khlebnikov teaches (Fig. 6A A-Plane 1120 direction, parallel to 138, aligns with extension prevention portion [0076]) wherein the providing the extension prevention portion includes providing the extension prevention portion along a (11-20) direction of the semiconductor substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov in order to provide active devices along the 1120 plane, which is the plane in SiC with the highest electron mobility, which is beneficial in power devices ([0080]).
Regarding claim 12, Chen in view of Seok teaches the method of manufacturing the silicon carbide semiconductor device according to claim 11, but does not explicitly teach comprising performing activation annealing of the semiconductor substrate after the providing the extension prevention portion.
In analogous art, Khlebnikov teaches (Figs. 20A-C) comprising performing activation annealing ([0108]) of the semiconductor substrate after the providing the extension prevention portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov In order to maintain improved wafer shape characteristics.
Regarding claim 13, Chen in view of Seok and Khlebnikov teach the method of manufacturing the silicon carbide semiconductor device according to claim 12, wherein the performing activation annealing includes first performing activation annealing of the semiconductor substrate at 1500°C or higher after the providing the semiconductor substrate (Khlebnikov, [0106]).
Regarding claim 16, Chen in view of Seok and Khlebnikov teaches the method of manufacturing the silicon carbide semiconductor device according to claim 15, wherein the providing the extension prevention portion (Chen, 140) includes providing the extension prevention portion along a (1-100) direction of the semiconductor substrate (140 is provided in the horizontal and vertical substrate directions).
Regarding claim 18, Chen in view of Seok teaches the method of manufacturing the silicon carbide semiconductor device according to claim 18 but does not explicitly teach wherein the performing ion implantation includes performing ion implantation of at least one of Al ions and P ions.
In analogous art, Khlebnikov teaches wherein the performing ion implantation includes performing ion implantation ([0108]) of at least one of Al ions and P ions ([0108]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov in order to offset stress-related wafer deformation (Khlebnikov, [0108]).
Claims 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Seok and Khlebnikov as applied to claim 1, and further in view of Li et al. (Dislocations in 4H silicon carbide, Journal of Physics D; herein known as Li).
Regarding claim 3, Chen in view of Seok and Khlebnikov teach the silicon carbide semiconductor device according to claim 2, but do not explicitly teach wherein an amount of the crystal defects in the ion implantation region is 5×1013/cm2 or more and 1×1016/cm2 or less ([0031]).
In analogous art, Li teaches that the recited range is a result effective variable, dependent on the thermal stress and cooling time of the growth of the SiC crystal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and Khlebnikov and of Li to vary, through routine experimentation, the “the result effective variable of A (result effective at least insofar as B) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed C or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Seok and Khlebnikov as applied to claim 1 above, and further in view of Kitamura (US PGPub 2016/0254148), herein Kitamura.
Regarding claim 5, Chen in view of Seok and Khlebnikov teaches (Chen, annotated Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion has a thickness (t) which is larger than 0 but does not explicitly teach and is 50% or less of a thickness of the epitaxial region in a depth direction of the semiconductor substrate.
In analogous art, Kitamura teaches (not pictured, [0061]) a thickness of the epitaxial region (2, [0061]) in a depth direction of the semiconductor substrate (1, [0061]).
Kitamura does not explicitly teach a thickness 50% or less, however does teach that the recited range is a result effective variable, changing the implant depth of the extension prevention portion results in affecting the distribution of strain of the SiC device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of A (result effective at least insofar as B) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed C or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 6, Chen in view of Seok and Kitamura and Khlebnikov teaches (Chen, annotated Fig. 8 above) the silicon carbide device according to claim 5 but does not explicitly teach wherein the extension prevention portion has a thickness of 5um or less from the upper surface of the epitaxial region in the depth direction of the semiconductor substrate. Kitamura further teaches wherein the extension prevention portion (not pictured, [0061]) has a thickness of 5um (1um, [0061]) or less from the upper surface of the epitaxial region (2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Chen in view of Seok and Khlebnikov and of Kitamura in order to create a strain layer having an appropriate depth, without incurring additional costs due to repeated implantation steps (Kitamura, [0061]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Seok as applied to claim 11 above, and further in view of Kinoshita (US PGPub 2020/0295129), herein Kinoshita.
Regarding claim 14, Chen in view of Seok teaches the method of manufacturing the silicon
carbide semiconductor device according to claim 11, but does not explicitly teach comprising forming an
alignment mark on the semiconductor substrate before the providing the extension prevention portion.
In analogous art, Kinoshita teaches (not pictured) forming an alignment mark on the semiconductor substrate before the providing the extension prevention portion ([0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Kinoshita in order to indicate ion implantation positions (Kinoshita, [0028]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Seok, and further in view of Li.
Regarding claim 21, Chen teaches (Fig. 8) a silicon carbide semiconductor device which includes a semiconductor substrate (101, [0039]) made of silicon carbide ([0020]) and having an epitaxial region made of silicon carbide (100, [0019]) on a front surface, the silicon carbide semiconductor device comprising: an active portion (Ra, Rb, [0028]) which is provided on the semiconductor substrate; wherein the element isolation portion includes an extension prevention portion (142, [0041]) which is provided to elongate along each of two opposing end sides (Fig. 8, 142 is shown extending along horizontal sides of active regions) on an upper surface of the epitaxial region (100) and wherein the extension prevention portion stops extension of interface dislocation ([0040]) of the semiconductor substrate in a (1-100 direction (Chen, 140) when the silicon carbide semiconductor device is in a wafer state (140 is provided in the horizontal and vertical substrate directions), wherein the extension prevention portion (142, 0027]) includes an ion implantation region ([0027]) which has a thickness (annotated Fig. 8, t) in a depth direction (D3) of the semiconductor substrate, is provided to elongate along (Fig. 8, 142 is shown extending along horizontal sides active regions) each of the two opposing end sides on the upper surface of the epitaxial region (100), and has crystal defects (lattice structures are highly damaged to create an amorphous region, [0027]).
Chen does not explicitly teach a pressure resistant structure portion which is provided on an outer periphery of the active portion.
Seok teaches a pressure resistant structure portion (102, [0030]) which is provided on an outer periphery ([0030]) of the active portion (104, [0030]) on the semiconductor substrate.
Because Chen and Seok are both directed toward defect management of SiC die, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen and Seok in order to reduce leakage originating from defects within the active region ([0002]).
Chen in view of Seok does not explicitly teach wherein an amount of the crystal defects in the ion implantation region is 5×1013/cm2 or more and 1×1016/cm2 or less ([0031]).
In analogous art, Li teaches that the recited range is a result effective variable, dependent on the thermal stress and cooling time of the growth of the SiC crystal. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Li to vary, through routine experimentation, the “the result effective variable of A (result effective at least insofar as B) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed C or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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