DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-6, 9-14, and 16-22 are pending.
Claims 1, 11, and 16 are amended.
Claims 7, 8, and 15 are cancelled.
Claims 21 and 22 are new.
Interview Summary
In a phone call with Ourmazd Ojan on 03/26/2026, examiner and attorney discussed the claim limitation of claim 3 and new claim 21, “wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less” to determine whether the unit of the amount of crystal defects should be per-cm2, as written, or was a typographical error of per-cm3, as appears most commonly in the art. Attorney contacted the applicant for clarification and confirmed that the claim limitation is per-cm2, as written, with reasoning given that these types of defects are linear dislocations with units of length, therefore the amount would be given in an area unit, instead of a volumetric unit.
Response to Arguments
Applicant's arguments, see pages 8-11, filed 03/13/2026 regarding amended independent claims 1 and 11 have been fully considered but they are not persuasive. Specifically, amendment of the previous claims 7, 8, and 15 into claims 1 and 11, respectively, does not overcome the prior art rejection of record. Applicant argues that Chen in view of Seok and Khlebnikov fails to teach wherein an elongation direction of the extension prevention portion is a (11-20) direction of the semiconductor substrate and wherein the extension prevention portion stops extension of interface dislocation of the semiconductor substrate in a (1-100) direction of the semiconductor substrate when the silicon carbide semiconductor device is in a wafer state. Khlebnikov (US PGPub 2021/0198804) teaches an elongation direction of the extension prevention portion in a 11-20 direction and wherein the prevention portion stops extension of interface dislocation of the semiconductor substrate in a (1-100) direction of the substrate in a wafer. Khlebnikov teaches use of these crystal directions for beneficial use of electron mobility, and while this is done to reduce warpage of the resulting wafer, this does not discredit the reference as prior art, as Khlebnikov teaches a clear advantage to utilizing these crystal directions, as well as a benefit of reduction of interface dislocations in a wafer. The rejections of claim 1 and 11 are upheld. Accordingly, the rejections of dependent claims 2-6, 8-10, 12-14, and 16-19 are upheld.
Applicant’s arguments, see pages 8-11, filed 03/13/2026 regarding claim 3 and new independent claim 21 have been fully considered and are persuasive, therefore the rejection under 35 U.S.C 103 is withdrawn. Specifically, the argument regarding the claim limitation “wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less,” is persuasive. However, upon further consideration, a new rejection under 35 U.S.C. 112(a) has been made below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Specifically, regarding the claim limitation “wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less,” the specification describes an ion implantation region having a width, height, and depth, in which ion implantation is performed, in order to form crystal defects. Additionally, the extension prevention portion, which is formed by formation of crystal defects in the ion implantation region, and may be the ion implantation region having crystal defects ([0076]), has a width, height, and depth. The unit of measurement of the crystal defects, in this volumetric region, is denoted in terms of area (/cm2) in the claims and specification of the instant application, as opposed to the normal convention of a volumetric (/cm3) measurement, to denote a density of the crystal defects in the volumetric space. The instant application describes that the extension prevention portion is provided in the (11-20) direction of the semiconductor substrate, but does not describe wherein it is planar, nor does it describe wherein ion implantation is performed to provide two-dimensional crystal defects, nor that the crystal defects are, in fact, two-dimensional.
In light of conversation with the applicant, the claim will be examined as written: “wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 9-13, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2022/0336650; herein known as Chen) in view of Seok (US PGPub 2021/0151598; herein known as Seok) and Khlebnikov et al. (US PGPub 2021/0198804; herein known as Khlebnikov).
Regarding claim 1, Chen teaches (Fig. 8) a silicon carbide semiconductor device which includes a semiconductor substrate (101, [0039]) made of silicon carbide ([0020]) and having an epitaxial region made of silicon carbide (100, [0019]) on a front surface, the silicon carbide semiconductor device comprising: an active portion (Ra, Rb, [0028]) which is provided on the semiconductor substrate wherein the element isolation portion includes an extension prevention portion (142, [0041]) which is provided to elongate along each of two opposing end sides (Fig. 8, 142 is shown extending along horizontal sides of active regions) on an upper surface of the epitaxial region (100) and wherein the extension prevention portion stops extension of interface dislocation ([0040]) of the semiconductor substrate in a (1-100 direction (Chen, 140) when the silicon carbide semiconductor device is in a wafer state (140 is provided in the horizontal and vertical substrate directions).
Chen does not explicitly teach a pressure resistant structure portion which is provided on an outer periphery of the active portion.
Seok teaches a pressure resistant structure portion (102, [0030]) which is provided on an outer periphery ([0030]) of the active portion (104, [0030]) on the semiconductor substrate.
Because Chen and Seok are both directed toward defect management of SiC die, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen and Seok in order to reduce leakage originating from defects within the active region ([0002]).
Chen in view of Seok does not explicitly teach wherein an elongation direction of the extension prevention portion is a (11-20) direction of the semiconductor substrate.
Khlebnikov teaches (Fig. 6A) wherein an elongation direction of the extension prevention portion is a (11-20) direction (Fig. 12, <1120>, horizontal direction, parallel to substrate) of the semiconductor substrate (11-20) direction (A-Plane 1120, parallel to 138, aligns with extension prevention portion [0076])
Because Chen in view of Seok and Khlebnikov are related to ion implantation of SiC wafers, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov in order to provide active devices along the 1120 plane, which is the plane in SiC with the highest electron mobility, which is beneficial in power devices ([0080]).
Regarding claim 2, Chen in view of Seok and Khlebnikov teaches (Chen, Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142, 0027]) includes an ion implantation region ([0027]) which has a thickness (annotated Fig. 8, t) in a depth direction (D3) of the semiconductor substrate, is provided to elongate along (Fig. 8, 142 is shown extending along horizontal sides active regions) each of the two opposing end sides on the upper surface of the epitaxial region (100), and has crystal defects (lattice structures are highly damaged to create an amorphous region, [0027]).
PNG
media_image1.png
367
736
media_image1.png
Greyscale
Regarding claim 4, Chen in view of Seok and Khlebnikov teaches (Chen, Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142, [0027]) includes a trench structure (142, [0027]) which has a thickness (annotated Fig. 8 above, t) in a depth direction (D3) of the semiconductor substrate and is provided to elongate along each of the two opposing end sides on the upper surface of the epitaxial region (100, [0019]).
Regarding claim 9, Chen in view of Seok and Khlebnikov teaches (Chen, Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142) is provided to elongate from one end (E1) to another end (E2) of the end side (142 shown extending between edges of active areas).
Regarding claim 10, Chen in view of Seok and Khlebnikov teaches (Chen, annotated Fig. 8 above) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion (142) is provided on four sides (S1-S4) of the semiconductor substrate.
Regarding claim 11, Chen teaches (Fig. 8) method of manufacturing a silicon carbide semiconductor device comprising: providing a semiconductor substrate (101, [0039]) made of silicon carbide ([0020]) and having an epitaxial region made of silicon carbide on a front surface ([0019]); providing an active portion (Ra, Rb, [0028]) on the semiconductor substrate; and providing, in the element isolation portion, an extension prevention portion (142, [0041]), which stops extension of interface dislocation ([0040]), along each of two opposing end sides on an upper surface of an epitaxial region (100, [0019]) of the semiconductor substrate and wherein the extension prevention portion stops extension of the interface dislocation of the semiconductor substrate in a (1-100) direction of the semiconductor substrate when the silicon carbide semiconductor device is in a wafer state (140 is provided in the horizontal and vertical substrate directions).
Chen does not explicitly teach providing a pressure resistant structure portion on an outer periphery of the active portion.
Seok teaches a pressure resistant structure portion (102, [0030]) which is provided on an outer periphery ([0030]) of the active portion (104, [0030]) on the semiconductor substrate.
Because Chen and Seok are both directed toward defect management of SiC die, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen and Seok in order to reduce leakage originating from defects within the active region ([0002]).
Chen in view of Seok does not explicitly teach wherein the providing the extension prevention portion includes providing the extension prevention portion along a (11-20) direction of the semiconductor substrate.
Khlebnikov teaches (Fig. 6A A-Plane 1120 direction, parallel to 138, aligns with extension prevention portion [0076]) wherein the providing the extension prevention portion includes providing the extension prevention portion along a (11-20) direction of the semiconductor substrate.
Because Chen in view of Seok and Khlebnikov are both directed toward SiC devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov in order to provide active devices along the 1120 plane, which is the plane in SiC with the highest electron mobility, which is beneficial in power devices ([0080]).
Regarding claim 12, Chen in view of Seok teaches the method of manufacturing the silicon carbide semiconductor device according to claim 11, but does not explicitly teach comprising performing activation annealing of the semiconductor substrate after the providing the extension prevention portion.
Khlebnikov teaches (Figs. 20A-C) comprising performing activation annealing ([0108]) of the semiconductor substrate after the providing the extension prevention portion.
Because Chen in view of Seok and Khlebnikov are both directed toward ion implantation of SiC wafer, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov In order to maintain improved wafer shape characteristics.
Regarding claim 13, Chen in view of Seok and Khlebnikov teach the method of manufacturing the silicon carbide semiconductor device according to claim 12, wherein the performing activation annealing includes first performing activation annealing of the semiconductor substrate at 1500°C or higher after the providing the semiconductor substrate (Khlebnikov, [0106]).
Regarding claim 16, Chen in view of Seok and Khlebnikov teaches the method of manufacturing the silicon carbide semiconductor device according to claim 15, wherein the providing the extension prevention portion (Chen, 140) includes providing the extension prevention portion along a (1-100) direction of the semiconductor substrate (140 is provided in the horizontal and vertical substrate directions).
Regarding claim 18, Chen in view of Seok teaches the method of manufacturing the silicon carbide semiconductor device according to claim 18 but does not explicitly teach wherein the performing ion implantation includes performing ion implantation of at least one of Al ions and P ions.
Khlebnikov teaches wherein the performing ion implantation includes performing ion implantation ([0108]) of at least one of Al ions and P ions ([0108]).
Because Chen in view of Seok and Khlebnikov are both directed toward ion implantation of SiC wafer, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Khlebnikov in order to offset stress-related wafer deformation (Khlebnikov, [0108]).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Seok and Khlebnikov as applied to claim 1 above, and further in view of Kitamura (US PGPub 2016/0254148), herein Kitamura.
Regarding claim 5, Chen in view of Seok and Khlebnikov teaches (Chen, annotated Fig. 8) the silicon carbide semiconductor device according to claim 1, wherein the extension prevention portion has a thickness (t) which is larger than 0 but does not explicitly teach and is 50% or less of a thickness of the epitaxial region in a depth direction of the semiconductor substrate.
Kitamura teaches (not pictured, [0061]) a thickness of the epitaxial region (2, [0061]) in a depth direction of the semiconductor substrate (1, [0061]).
Kitamura does not explicitly teach a thickness 50% or less, however does teach that the recited range is a result effective variable, changing the implant depth of the extension prevention portion results in affecting the distribution of strain of the SiC device. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to vary, through routine experimentation, “the result effective variable of A (result effective at least insofar as B) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05).
Further, the specification contains no disclosure of either the critical nature of the claimed C or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 6, Chen in view of Seok and Kitamura and Khlebnikov teaches (Chen, annotated Fig. 8 above) the silicon carbide device according to claim 5 but does not explicitly teach wherein the extension prevention portion has a thickness of 5um or less from the upper surface of the epitaxial region in the depth direction of the semiconductor substrate. Kitamura further teaches wherein the extension prevention portion (not pictured, [0061]) has a thickness of 5um (1um, [0061]) or less from the upper surface of the epitaxial region (2).
Because Chen in view of Seok and Khlebnikov and Kitamura are directed toward silicon carbide devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Chen in view of Seok and Khlebnikov and of Kitamura in order to create a strain layer having an appropriate depth, without incurring additional costs due to repeated implantation steps (Kitamura, [0061]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Seok as applied to claim 11 above, and further in view of Kinoshita (US PGPub 2020/0295129), herein Kinoshita.
Regarding claim 14, Chen in view of Seok teaches the method of manufacturing the silicon
carbide semiconductor device according to claim 11, but does not explicitly teach comprising forming an
alignment mark on the semiconductor substrate before the providing the extension prevention portion.
Kinoshita teaches (not pictured) forming an alignment mark on the semiconductor substrate before the providing the extension prevention portion ([0028]).
Because Chen in view of Seok and Kinoshita are directed toward ion implantation of silicon carbide devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chen in view of Seok and of Kinoshita in order to indicate ion implantation positions (Kinoshita, [0028]).
Allowable Subject Matter
Claim 3 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 21 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the cited prior art of record does not teach or fairly suggest, along with the other claimed features the silicon carbide semiconductor device according to claim 1 wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less. Chen teaches wherein an ion implantation dosage is within the specified range, but does not teach wherein an amount of crystal defects is measured in /cm2, nor wherein it would be calculated in that range.
Regarding claim 21, the cited prior art of record does not teach or fairly suggest, along with the other claimed features a silicon carbide semiconductor device wherein an amount of the crystal defects in the ion implantation region is 5x1013/cm2 or more and 1x1016/cm2 or less. Chen teaches wherein an ion implantation dosage is within the specified range, but does not teach wherein an amount of crystal defects is measured in /cm2, nor wherein it would be calculated in that range.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY FARMER/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights