DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF

Application No. 18/473,317

• Filed: Sep 25, 2023
• Priority: Nov 09, 2022 — TW 111142755
• Examiner: ANDERSON, ERIK ARTHUR
• Art Unit: 2812
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: Winbond Electronics Corp.
• OA Round: 2 (Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Claim Objections
Claim 19 objected to because of the following informality: on line 2, “one of the isolation structure” should be “one of the isolation structures”. Appropriate correction is required.

Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.

Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0228702 A1 (Wu).

Regarding claim 9, Wu discloses, A method ([0002]) for manufacturing a dynamic random access memory (DRAM) (dynamic random access memory (DRAM) (100); FIG. 2; [0148]-[0150]), comprising:

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forming a plurality of isolation structures (plurality of isolation structures (15); FIG 15A; [0156]) in a substrate (substrate (1); FIG. 2; [0150]) to define a plurality of active areas (plurality of active areas (1A); FIG. 2; [0150]) in the substrate (1);

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forming a plurality of bit line structures (bit line structures (27); FIGs. 1 and 2; [0150]) on the substrate (1), wherein each of the bit line structures (27) comprises:
a conductive structure (conductive structure (25); FIG. 24A; [0220]) including a bit line contact structure (bit line contact structure (27A); FIG. 2; [0156]) electrically connected to a corresponding one of the active areas (1A), and a bit line (27) on the bit line contact structure (27A);
an insulating cover layer (insulating cover layer (26); FIG. 24A; [0220]) disposed on the conductive structure (25);

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an insulating layer (insulating layer (20A); FIG. 2; [0156]) disposed between the conductive structure (25) and the substrate (1) except at a location where the bit line contact structure (27A) is located (annotated FIG. 24A, above); and
a spacer (spacer (30); FIG. 26A; [0222]) disposed on a side wall (first annotated FIG. 32A, below) of the insulating layer (20A), a side wall (annotated FIG. 26A, below) of the conductive structure (25) and a side wall (annotated FIG. 26A, below) of the insulating cover layer (26);

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forming a capacitor contact opening (first annotated FIG. 32A, below) between the bit line structures (27), wherein the capacitor contact opening (first annotated FIG. 32A, below) includes:

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(a) an upper opening region (first annotated FIG. 32A, above) located between a first one of the bit line structures (27) at a location where the spacer (30) is disposed on the side wall (first annotated FIG. 32A, above) of the insulating layer (20A); and
(b) a lower opening region (first annotated FIG. 32A, above) located below the upper opening region (first annotated FIG. 32A, above) and below a portion of the spacer (30) of the first one of the bit line structures (27), wherein the lower opening region (first annotated FIG. 32A, above) exposes:
(i) a recessed portion (recessed portion (37); FIG. 32A; [0174]) of the active area (1A) located beneath the portion of the spacer (30), and
(ii) a portion (first annotated FIG. 32A, above) of one of the isolation structures (15) adjacent to the bit line contact structure (27A);
and,
forming a capacitor contact (capacitor contact (44); FIG. 2; [0156]) in the capacitor contact opening (first annotated FIG. 32A, above), wherein the capacitor contact (44) includes a protruding portion (protruding portion (39b); FIG. 2; [0160]) extending laterally beneath the portion (first annotated FIG. 32A, above) of the spacer (30) that is disposed on the side wall (first annotated FIG. 32A, above) of the insulating layer (20A).

But, Wu does not appear to explicitly disclose, the upper opening region located between a second one of the bit line structures at a location where the bit line contact structure is electrically connected to the corresponding one of the active areas.

However, one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Wu before hm/her would have recognized that the location of the upper opening region of Wu between a second one of the bit line structures at a location where the bit line contact structure is electrically connected to the corresponding one of the active areas was an obvious matter of design choice that would not modify the method of Wu because an opening for the capacitor contact would still need to be formed regardless of its location and there is nothing recited in claim 9 which provides that the step of forming the capacitor contact opening differs or is modified based on its location. Please see, MPEP 2144.04(VI)(C).

Regarding claim 10, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein forming the capacitor contact opening (first annotated FIG. 32A, above) comprises:
forming a groove (groove (37); first annotated FIG. 32A, above; [0174]) between the bit line structures (27);
performing an etch-back process ([0204]) to increase a depth of the groove (37) (compare annotated FIG. 29A, below, to first annotated FIG. 32A, above)1, thereby exposing a side wall (first annotated FIG. 32A, above) of the active area (1A) below the spacer (30) and exposing a side wall (first annotated FIG. 32A, above) of the portion of one of the isolation structures (15) adjacent to the bit line contact structure (27A);

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performing an oxidation process to oxidize a portion (oxidized portion (2A); FIG. 29A; [0192]) of the substrate (1) exposed in the groove (37); and
removing the oxidized portion (2A) ([0204]; FIG. 32A—oxidized portion (2A) does not appear in FIG. 32A).

Regarding claim 11, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein a surface (second annotated FIG. 32A, below) of the recessed portion (37) of the active area (1A) is lower than a surface (second annotated FIG. 32A, below) of the portion of one of the isolation structures (15) adjacent to the bit line contact structure (27A) (second annotated FIG. 32A, below, and FIG. 21A).

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Regarding claim 12, Wu discloses, The method ([0002] for manufacturing the DRAM (100) according to claim 9, wherein a bottom surface of the capacitor contact opening has a step-shaped cross section (second annotated FIG. 32A, above).

Regarding claim 13, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein the capacitor contact opening has a first width (third annotated FIG. 32A, below), a second width (third annotated FIG. 32A, below), and a third width (third annotated FIG. 32A, below), the first width (third annotated FIG. 32A, below) is farthest from the substrate, the third width is the closest to the substrate (1), and the second width (third annotated FIG. 32A, below) is located between the first width (third annotated FIG. 32A, below) and the third width (third annotated FIG. 32A, below).

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But, Wu does not appear to explicitly disclose, and the second width is greater than the first width and the third width.

However, there are a finite number of predicable solutions regarding the second width of the capacitor contact opening relative to the first and third widths of the capacitor contact opening—i.e., (i) the second width can be greater than or equal to the first width and less than or equal to the third width, (ii) the second width can be greater than the third width and less than the first width, (iii) the second width can be less than the first width and the third width, or (iv) the second width can be greater than the first width and the third width and, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Wu before him/her to try each of these widths with a reasonable expectation of success one of which is the second width is greater than the first width and the third width, as recited in claim 13. See, MPEP 2143(E)—“Obvious To Try” – Choosing From a Finite Number of Identified, Predicable Solutions, With a Reasonable Expectation of Success.

Regarding claim 14, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein the protruding portion (39b) of the capacitor contact (44) extends laterally beneath the portion of the spacer (30) disposed on the side wall (first annotated FIG. 32A, above) of the insulating layer (20A) to a greater extent (annotated FIG. 2, above) than beneath the spacer (30) disposed on an opposite side of the capacitor contact (44).

Regarding claim 15, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein the capacitor contact (44) is embedded (FIG. 2) in the substrate (1).

Regarding claim 16, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein the protruding portion (39b) of the capacitor contact (44) touches (FIG. 2) the recessed portion (37) of the active area (1A), and wherein the recessed portion (37) of the active area (1A) has an L- shaped cross section in across-sectional view (third annotated FIG. 32A, above).

Regarding claim 17, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9,wherein the recessed portion (37) of the active area (1A) includes a surface (fourth annotated FIG. 32A, below) of the active area (1A) at a bottom of the recessed portion (37) and a vertical sidewall (fourth annotated FIG. 32A, below) extending upward from the surface, and
wherein a lower portion (lower portion 39(A); FIG. 2; [0158]) of the capacitor contact (44) has two opposite sidewalls (annotated FIG. 2, above), one of the opposite sidewalls (annotated FIG. 2, above) contacting the vertical sidewall (fourth annotated FIG. 32A, below) of the recessed portion (37) of the active area (1A), and the other of the opposite sidewalls (annotated FIG. 2, above) contacting a sidewall (fourth annotated FIG. 32A, below) of one of the isolation structures (15).

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Regarding claim 18, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein the capacitor contact (44) comprises a first portion (first portion (43A); FIG. 2; [0158]) and a second portion (second portion (39A); FIG. 2; [0158]), the first portion (43A) is formed on the second portion (39A), and a material of the first portion (43A) is different from that of the second portion (39A) ([0159]).

Regarding claim 19, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 9, wherein an edge (annotated FIG. 2, above) of one of the isolation structure (15) is located within the capacitor contact (44).

Regarding claim 20, Wu discloses, The method ([0002]) for manufacturing the DRAM (100) according to claim 11, further comprising:
forming a capacitor (capacitor (48); FIG. 2; [0152]) disposed above the capacitor contact (44).

Response to Amendments and Arguments
Applicant’s amendment of claims 11, 16, 17, 19, and 20 and remarks on pages nine (9)-ten (10) of the “Amendment And Response To Office Action” filed on May 6, 2026 (hereinafter the “Response”) have been fully considered and have overcome the rejections of claims 11, 16, 17, 19, and 20 under 35 U.S.C. 112(b) in the Office Action dated February 6, 2026 (hereinafter the “Office Action”). Also, Applicant’s amendment of claim 9 and remarks on pages ten (10)-eleven (11) of the Response regarding the rejection of claim 9 under 35 U.S.C. 102(a)(1) as being anticipated by Wu in the Office Action have been fully considered. However, amended claim 9 is now rejected under 35 U.S.C. 103 as being unpatentable over Wu, for at least the reasons detailed above in this Final Office Action.

Additionally, Applicant’s amendment of claims 10 and 17 and remarks on pages 12-13 of the Response regarding the rejection thereof under 35 U.S.C. 102(a)(1) as being anticipated by Wu in the Office Action, as well as Applicant’s amendment of claim 13 and remarks on pages 12-13 of the Response regarding the rejection thereof under 35 U.S.C. 103 as being unpatentable based on Wu in the Office Action, have been fully considered. However, amended claims 10 and 17 are now rejected under 35 U.S.C. 103 as being unpatentable over Wu, and claim 13 remains rejected under 35 U.S.C. 103 as being unpatentable over Wu, for at least the reasons detailed above in this Final Office Action.

Notwithstanding the above, to advance prosecution, the Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed claim amendments to overcome the rejection of claims 9-20 before filing a written response to this Final Office Action. For example, perhaps Applicant to could please consider amending claim 9 to include recited step limitations which provide details as to how the step of forming the capacitor contact opening differs or is modified based on its location relative to the spacer versus it location relative to one of the bit line structures. The Examiner would welcome such a discussion and is available at the telephone number provided below.

Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).

A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this Final Action. In the event a first reply is filed within TWO MONTHS of the mailing date of this Final Action and the Advisory Action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the Advisory Action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the Advisory Action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this Final Action.

Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is [phone]. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).

Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.

If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].

Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at [phone] (toll-free). If you would like assistance from a USPTO Customer Service Representative, call [phone] (IN USA OR CANADA) or [phone].

/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812

1 Please also see, Srinivasan et al., Quartz Etch Process To Improve Etch Depth Linearity And Uniformity Using Mask Etcher IV, 2004, 24th Annual BACUS Symposium on Photomask Technology, Proceedings of SPIE Vol. 5567, pages 176-182 (Year: 2004), cited below in the Examiner’s cited references, which discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention to perform an etch-back process to control/increase depth of a groove.

Prosecution Timeline

• Sep 25, 2023: Application Filed
• Feb 06, 2026: Non-Final Rejection mailed — §103
• May 06, 2026: Response Filed
• Jun 25, 2026: Final Rejection mailed — §103
• Jul 06, 2026: Interview Requested