DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20040036068) in view of Liu et al. (US 20020180026) and further in view of KIM et al. (US 20200386786 A1)
Regarding claim 1, Li discloses that a memory tile with a probe pad arrangement, comprising:
a first surface L1 and a second surface opposite to the first surface L4 (Fig. 2);
a first probe pad set 24-32, having a plurality of first probe pads and provided on the first surface L1 (Fig. 2);
a second probe pad set 24-32, having a plurality of second probe pads and provided on the second surface L4 (Fig. 2) and a first test signal pattern of the first probe pad set viewed from the first surface L1 is the same as a second test signal pattern of the second probe pad set viewed from the second surface L2 (Fig. 2).
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Li fails to discloses that a plurality of first conductive connections, each of the plurality of first conductive connections is electrically connected to a corresponding first probe pad among the first probe pad set;
a plurality of second conductive connections, each of the plurality of second conductive connections is electrically connected to a corresponding first conductive connection among the plurality of first conductive connections; a plurality of third conductive connections, each of the plurality of third conductive connections is electrically connected to a corresponding second conductive connection among the plurality of second conductive connections; and a plurality of fourth conductive connections, each of the plurality of fourth conductive connections is electrically connected to a corresponding third conductive connection among the plurality of third conductive connections and is electrically connected to a corresponding second probe pad among the second probe pad set, wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set, the plurality of first probe pads of the first probe pad set each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set each receives a corresponding second test signal to form a second test signal arrangement pattern, and the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface, such that a same probe card is applied to the first probe pad set and the second probe pad set to test the first surface or the second surface of the memory tile.
However, Liu suggests that configuration of bond pads & test pads including a plurality of first conductive connections, each of the plurality of first conductive connections is electrically connected to a corresponding first probe pad among the first probe pad set;
a plurality of second conductive connections, each of the plurality of second conductive connections is electrically connected to a corresponding first conductive connection among the plurality of first conductive connections;
a plurality of third conductive connections, each of the plurality of third conductive connections is electrically connected to a corresponding second conductive connection among the plurality of second conductive connections; and
a plurality of fourth conductive connections, each of the plurality of fourth conductive connections is electrically connected to a corresponding third conductive connection among the plurality of third conductive connections and is electrically connected to a corresponding second probe pad among the second probe pad set, wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set (Fig. 8-9).
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Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Li with a plurality of first conductive connections, each of the plurality of first conductive connections is electrically connected to a corresponding first probe pad among the first probe pad set;
a plurality of second conductive connections, each of the plurality of second conductive connections is electrically connected to a corresponding first conductive connection among the plurality of first conductive connections;
a plurality of third conductive connections, each of the plurality of third conductive connections is electrically connected to a corresponding second conductive connection among the plurality of second conductive connections; and
a plurality of fourth conductive connections, each of the plurality of fourth conductive connections is electrically connected to a corresponding third conductive connection among the plurality of third conductive connections and is electrically connected to a corresponding second probe pad among the second probe pad set, wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set as taught by Liu in order to enhance extendibility of test pads and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Li & Liu fail to teach that the plurality of first probe pads of the first probe pad set each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set each receives a corresponding second test signal to form a second test signal arrangement pattern, and the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface, such that a same probe card is applied to the first probe pad set and the second probe pad set to test the first surface or the second surface of the memory tile.
However, Kim suggests that the plurality of first probe pads of the first probe pad set 211 each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set 221 each receives a corresponding second test signal to form a second test signal arrangement pattern, and the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface (para. 0041, same voltage), such that a same probe card 300 is applied to the first probe pad set 211 and the second probe pad set 221 to test the first surface (Fig. 2-8) or the second surface of the memory tile 210 & 220.
Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide A with the plurality of first probe pads of the first probe pad set each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set each receives a corresponding second test signal to form a second test signal arrangement pattern, and the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface, such that a same probe card is applied to the first probe pad set and the second probe pad set to test the first surface or the second surface of the memory tile as taught by Kim in order to enhance a process of testing on each semiconductor device to reduce defects or increasing productivity also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art.
Reclaim 2, Li, Liu, & Kim disclose that test signal pattern of the plurality of third conductive connections viewed from the first surface of the memory tile and a test signal pattern of the plurality of third conductive connections viewed from the second surface of the memory tile are a mirror symmetry (Li in view of Liu, Fig. 8-9, Li discloses top surface of the test pad can be the same as bottom test pads. Liu suggests that pattern of test pad can be shown in Fig. 8-9, therefore, it will be a mirror symmetry).
Reclaim 3, Li, Liu, & Kim disclose that each of the plurality of first conductive connections is a redistribution layer, and each of the plurality of fourth conductive connections is a redistribution layer (Fig. 7, Liu).
Reclaim 4, Li , Liu, & Kim disclose that each of the plurality of third conductive connections is a through silicon via (TSV)(Li, Fig. 2).
Reclaim 5, Li , Liu, & Kim disclose that each of the plurality of second conductive connections is constructed by at least one internal metal layer provided in the memory tile (Fig. 2 in view of Liu Fig. 8-9, note: a chip).
Reclaim 6, Li , Liu, & Kim disclose that the plurality of first probe pads is arranged in two rows along a central line of the first arrangement pattern of the first probe pad set, and the plurality of second probe pads is arranged in two rows along a central line of the second arrangement pattern of the second probe pad set (Fig. 2 in view of Liu Fig. 8-9, note: a chip).
Reclaim 7, Li , Liu, & Kim disclose that the memory tile is a DRAM tile (Fig. 2 in view of Liu Fig. 8-9, note: a chip can be a DRAM).
Regarding claim 8, Li , Liu, & Kim disclose that a stacked memory device, comprising:
a memory chip (para. 0007, a chip), having a plurality of memory tiles;
a logic chip (para. 0007, a chip), bonded to the memory chip in a face-to face manner and configured to control the memory chip, wherein each of the plurality of memory tiles further comprises:
a first surface and a second surface opposite to the first surface (Li, Fig. 2);
a first probe pad set 24-32 (Fig. 2) L1, having a plurality of first probe pads and provided on the first surface;
a second probe pad set 24-32 (Fig. 2), having a plurality of second probe pads and provided on the second surface L4 (Li Fig. 2);
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a plurality of first conductive connections, each of the plurality of first conductive connections is electrically connected to a corresponding first probe pad among the first probe pad set;
a plurality of second conductive connections, each of the plurality of second conductive connections is electrically connected to a corresponding first conductive connection among the plurality of first conductive connections; a plurality of third conductive connections, each of the plurality of third conductive connections is electrically connected to a corresponding second conductive connection among the plurality of second conductive connections; and a plurality of fourth conductive connections, each of the plurality of fourth conductive connections is electrically connected to a corresponding third conductive connection among the plurality of third conductive connections and is electrically connected to a corresponding second probe pad among the second probe pad set (Liu, Fig. 8-9 above), wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set (Li disclose top test pads and bottom test pads can be identical), the plurality of first probe pads of the first probe pad set 211 (Kim, Fig. 2-8) each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set 221 each receives a corresponding second test signal to form a second test signal arrangement pattern, and the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface (Kim, para. 0041, same voltage), such that a same probe card 300 is applied to the first probe pad set 211 and the second probe pad set 221 to test the first surface (Kim, Fig. 2-8) or the second surface of the memory tile 210 & 220 (Kim, Fig. 2-8).
Reclaim 9, Li , Liu, & Kim disclose that a test signal pattern of the plurality of third conductive connections viewed from the first surface of the memory tile and a test signal pattern of the plurality of third conductive connections viewed from the second surface of the memory tile are a mirror symmetry (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 10, Li , Liu, & Kim disclose that each of the plurality of first conductive connections is a redistribution layer, and each of the plurality of fourth conductive connections is a redistribution layer (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 11, Li , Liu, & Kim disclose that each of the plurality of third conductive connections is a through silicon via (TSV) (Li, Fig. 2)
Reclaim 12, Li , Liu, & Kim disclose that each of the plurality of second conductive connections is constructed by at least one internal metal layer provided in the memory tile (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 13, Li , Liu, & Kim disclose that the plurality of first probe pads is arranged in two rows along a central line of the first arrangement pattern of the first probe pad set, and the plurality of second probe pads is arranged in two rows along a central line of the second arrangement pattern of the second probe pad set (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 14, Li , Liu, & Kim disclose that the memory tile is a DRAM tile (Li Fig. 2 in view of Fig. 8-9, Liu).
Regarding claim 15, Li , Liu, & Kim disclose that a memory tile with a probe pad arrangement, comprising:
a first surface L1 and a second surface L2opposite to the first surface L1 (Li, Fig. 2);
a first probe pad set 24-32, having a plurality of first probe pads and provided on the first surface L1 (Fig. 2);
a second probe pad set 24-32, having a plurality of second probe pads and provided on the second surface L4; and
a plurality of connection structures, each of the plurality of connection structures being electrically connected to a corresponding first probe pad among the plurality of first probe pads and to a corresponding second probe pad among the plurality of second probe pads (Liu, Fig. 8-9), wherein a first arrangement pattern of the first probe pad set is the same as a second arrangement pattern of the second probe pad set (Li Fig. 2 in view of Fig. 8-9, Liu), the plurality of first probe pads of the first probe pad set 211 (Kim, Fig. 2-8) each receives a corresponding first test signal to form a first test signal arrangement pattern, and the plurality of second probe pads of the second probe pad set 221 each receives a corresponding second test signal to form a second test signal arrangement pattern, and the first test signal arrangement pattern on the first surface is the same as the second test signal arrangement pattern on the second surface (Kim, para. 0041, same voltage), such that a same probe card 300 is applied to the first probe pad set 211 and the second probe pad set 221 to test the first surface (Kim, Fig. 2-8) or the second surface of the memory tile 210 & 220 (Kim, Fig. 2-8).
Reclaim 16, Li, Liu, & Kim disclose that each of the plurality of connection structures comprises: a first redistribution layer, electrically connected to the corresponding first probe pad; an interconnection, electrically connected to the first redistribution layer; a through silicon via (TSV), electrically connected to the interconnection; and a second redistribution layer, electrically connected to the TSV and to the corresponding second probe pad (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 17, Li , Liu, & Kim disclose that the interconnection comprises a plurality of internal metal layers provided in the memory tile (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 18, Li , Liu, & Kim disclose that a test signal pattern of the TSVs viewed from the first surface of the memory tile and a test signal pattern of the TSVs viewed from the second surface of the memory tile are a mirror symmetry (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 19, Li , Liu, & Kim disclose that the plurality of first probe pads is arranged in two rows along a central line of the first arrangement pattern of the first probe pad set, and the plurality of second probe pads is arranged in two rows along a central line of the second arrangement pattern of the second probe pad set (Li Fig. 2 in view of Fig. 8-9, Liu).
Reclaim 20, Li , Liu, & Kim disclose that the memory tile is a DRAM tile (Li Fig. 2 in view of Fig. 8-9, Liu).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SU C KIM/ Primary Examiner, Art Unit 2899