DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Anticipation Rejection and Obviousness Rejections, filed 2/25/2026, with respect to the rejection(s) of claim(s) 1 and 17 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nakazawa, Seiya et al. (Pub No. JP 6664445 B2) (hereinafter, Nakazawa).
Re claims 1 and 17, Nakazawa ¶[0263] is found to disclose the breakdown voltage adjusting region is located near 171, i.e. local to diode region 181 per Figs 18 and 22, and the region becomes a floating state as the regions 171 are not connected to a fixed potential and determined by surrounding charge dynamics, therefore region 171 is in an electrically open state or isolated from the source voltage. Additionally, per ¶[0248], the inner diode comprising source electrode layer 157 is supplied by a source voltage, therefore the source voltage/potential is not supplied to region 171 of Fig 18.
6. Applicant’s arguments with respect to claim(s) 1 and 3-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument, i.e. the limitations as taught by Shinsho, Kohei (Pub No. US 20180226400 A1) (hereinafter, Shinsho) from cancelled claim 2.
7. Applicant’s arguments, see Objection to the Title, filed 2/25/2026, with respect the objection of the Title have been fully considered and are persuasive. The objection of the Title has been withdrawn.
8. Applicant’s arguments, see Objection to the Specification, filed 2/25/2026, with respect the objection of the Specification have been fully considered and are persuasive. The objection of the Specification has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1, 3-10, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakazawa, Seiya et al. (Pub No. JP 6664445 B2) (hereinafter, Nakazawa).
Re Claim 1 (Currently Amended), Nakazawa teaches a semiconductor device comprising:
a chip (Semiconductor device; 101; Fig 16; ¶[00172]) which has a main surface (First main surface; 103; Fig 14; ¶[0171]);
a first region (High concentration region/SiC semiconductor layer; 108/102; Fig 19; ¶[0186]; Note: Per Fig 19 SiC semiconductor layer 102 comprises of high concentration region 108) of a first conductivity type (N-type; ¶[0089]) which is formed in a surface layer portion (Region on first main surface 103 side; ¶[0186]) of the main surface;
Nakazawa, Fig 16: Plan-view of chip and main surface
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a second region (Deep well region/Active main surface/Field Limit Structure/Body region/Diode region; 165/171/183/141/181; Figs 18/19/20/22; ¶[0267]) of a second conductivity type (P-type; ¶[0267]) which is formed in a surface layer portion (Surface layer portion of first main surface 103; ¶[0263]) of the first region;
Nakazawa, Figs 18 & 19: Close-up of plan-view of region 111 and 112 & cross-section of XXI from Fig 17
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Nakazawa, Fig 20: Cross-section illustrating first and second regions and lower/upper electrodes
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a trench separation structure (Contact trench portion/Gate fingers; 144/117; Figa 25/18; ¶[0192]) which penetrates through (Penetrates through 171; Fig 18) the second region, surrounds an interior of the second region, and demarcates (Creates boundary between inner and outer p-type regions; Fig 18) an inner region (Active region/Inner p-type region; 111/171; Figs 18/22) at an inner side (Inner side of p-type region 171; Fig 18) of the second region and an outer region (Outer region of 171/Outer Region; 112; Figs 18/22) at an outer side (Far side of gate finger 117; Fig 18) of the second region in the main surface;
a trench gate structure (Source/Main/Gate electrodes; 157/149/207; Figs 19/20; ¶[0244]) which is formed in the inner region so as to penetrate (157 penetrates into 165; Fig 19) through the second region;
an inner diode (PN junction diode structure near deep well regions 165 and high concentration region 108; Fig 18; ¶¶[0268, 0276]) which includes the first region and the second region that are positioned in the inner region; and
an outer diode (PN junction diode in diode region 181; Dpn; Fig 22; ¶[0314]) which includes the first region serving as a cathode (SiC semiconductor layer 102 serves as a cathode; ¶[0311]) and the second region serving as an anode (Diode region 181 of the second region serves as an anode, i.e. within region 112; Figs 18/22; ¶[0311]) that are positioned in the outer region and is electrically separated from the inner diode and the trench gate structure and the inner diode by the trench separation structure (Trench separation structure 144/117 of Fig 18 electrically separates the outer region comprising the anode in diode region 181 of Fig 22 from the inner diode around deep well regions 165 of Fig 18).
wherein the second region serving as the anode if the outer diode is electrically opened, such that the outer diode is constituted of a floating diode formed in an electrically floating state (Per ¶[0263] the breakdown voltage adjusting region is located near 171 and the region becomes a floating state as the regions 171 are not connected to a fixed potential and determined by surrounding charge dynamics, therefore region 171 is electrically open or isolated from the source voltage).
Nakazawa, Fig 22: Cross-section of outer regions 112 including outer diode
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Re Claim 3 (Original), Nakazawa teaches the semiconductor device according to Claim 1,
wherein the outer diode (PN junction diode in diode region 181; Dpn; Fig 22; ¶[0314]) surrounds the trench separation structure (Contact trench portion/Gate fingers; 144/117; Figa 25/18; ¶[0192]) in plan view (Per Figs 18 & 25, PN junction diode Dpn is in region 112 which surrounds contact trench portion 144 in region 111) .
Re Claim 4 (Original), Nakazawa teaches the semiconductor device according to Claim 1,
wherein the chip (Semiconductor device; 101; Fig 22; ¶[00172]) has a side surface (Right side of Fig 22), and
the outer diode (PN junction diode in diode region 181; Dpn; Fig 22; ¶[0314]) is exposed from (Side surface includes layer 108 which is in contact with Dpn, therefore the side surface broadly exposes Dpn; Fig 22) the side surface of the chip.
Re Claim 5 (Original), Nakazawa teaches the semiconductor device according to Claim 1,
wherein the trench gate structure (Source/Main/Gate electrodes; 157/149/207; Figs 19/20; ¶[0244]) has a multi-electrode structure (Main/gate electrodes; 149/207; Fig 20; ¶¶[0340,0352]) which includes a lower electrode (Gate electrode layer; 149; Fig 20; ¶[0340]) and an upper electrode (Main electrode layer; 207; Fig 20; ¶[0352]) that are separated and embedded in an up/down direction inside a gate trench (Active trench portion; 143; Fig 20; ¶[0393]), and
the second region (Deep well region/Active main surface/Field Limit Structure; 165/171/183; Figs 18/19/22; ¶[0267]) of the inner diode (PN junction diode structure near deep well regions 165 and high concentration region 108; ¶¶[0268, 0276]) is electrically connected (Gate electrode 149 is connected by gate wiring layer 150 to SiC semiconductor layer 102, comprising of p-type body region 141; Fig 20; ¶[0237]) to the lower electrode.
Re Claim 6 (Original), Nakazawa teaches the semiconductor device according to Claim 1,
wherein the trench gate structures (Source/Main/Gate electrodes; 157/149/207; Figs 19/20; ¶[0244]) are arrayed as a stripe shape (Stripe shaped in regions 111/112; Figs 16/18) in the inner region (Active region/Inner p-type region; 111/171; Figs 18/22).
Re Claim 7 (Original), Nakazawa teaches the semiconductor device according to Claim 1,
wherein the trench separation structure (Contact trench portion/Gate fingers; 144/117; Figa 25/18; ¶[0192]) includes a separation electrode (Contact trench portion; 144; Fig 25; ¶[0217]) which is embedded inside a separation trench (Gate trench; 142; Fig 25; ¶[0219]), and
the second region (Deep well region/Active main surface/Field Limit Structure/Body region; 165/171/183/141; Figs 18/19/20/22; ¶[0267]) of the inner diode (PN junction diode structure near deep well regions 165 and high concentration region 108; ¶¶[0268, 0276]) is electrically connected (Contact trench portion 144 comes in contact with deep well region 165 which comprises the inner diode; Fig 25) to the separation electrode.
Re Claim 8 (Original), Nakazawa teaches the semiconductor device according to Claim 7,
wherein the trench separation structure (Contact trench portion/Gate fingers; 144/117; Figa 25/18; ¶[0192]) has a single electrode structure (Embodiment of Fig 18, the single electrode is the contact trench 144) which includes the single separation electrode (Contact trench portion; 144; Fig 18; ¶[0217]; Note: Contact trench portion 144 is considered a single electrode such that it is distinct from peripheral deep well region 166 per Fig 18) .
Re Claim 9 (Original), Nakazawa teaches the semiconductor device according to Claim 1, further comprising:
an impurity region (N-type source region; 163; Fig 18; ¶[0253]) of the first conductivity type (N-type; ¶[0089]) which is formed in a surface layer portion (Surface of p-type layer 165; Fig 19) of the second region (Deep well region/Active main surface/Field Limit Structure/Body region; 165/171/183/141; Figs 18/19/20/22; ¶[0267]) so as to be in contact with the trench gate structure (Source/Main/Gate electrodes; 157/149/207; Figs 19/20; ¶[0244]) in the inner region (Active region/Inner p-type region; 111/171; Figs 18/22).
Re Claim 10 (Original), Nakazawa teaches the semiconductor device according to Claim 9,
wherein the impurity region (N-type source region; 163; Fig 18; ¶[0253]) is formed at an interval (163 is separated by p-type region directly above from 144; Fig 18) from the trench separation structure (Contact trench portion/Gate fingers; 144/117; Figa 25/18; ¶[0192]) so as not to be in contact with the trench separation structure.
Re Claim 17 (Currently Amended), Nakazawa teaches a semiconductor device comprising:
a chip (Semiconductor device; 101; Fig 16; ¶[00172]) which has a main surface (First main surface; 103; Fig 14; ¶[0171]);
at least one trench separation structure (Contact trench portion/Gate fingers; 144/117; Fig 25/18; ¶[0192]) which is formed in the main surface so as to extend in a first direction (Y-direction; Fig 18);
a trench gate structure (Source/Main/Gate electrodes; 157/149/207; Figs 19/20; ¶[0244]) which is formed in the main surface so as to extend in a second direction (X-direction; Fig 18) that intersects the first direction and demarcates a mesa portion (Portions between gate electrodes 149 comprising 163 and 157; Fig 18) with the at least one trench separation structure;
a first body region (Region within mesa portions; Fig 18) which is formed in a surface layer portion (Surface layer is the plan-view of Fig 18) of the main surface inside the mesa portion; and
a second body region (Active main surface; 171; Fig 18; ¶[0267]) which is formed in a surface layer portion (Surface layer is the plan-view of Fig 18) of the main surface outside (Beyond the mesa portion; Fig 18) the mesa portion and electrically separated from the first body region and the trench gate structure by the at least one trench separation structure.
wherein a source potential (Source voltage is supplied to source electrode layer 157; ¶[0248]) is to be imparted to the first body region, and
the second body region is electrically opened and formed in an electrically floating state (Per ¶[0263] the breakdown voltage adjusting region is located near 171 and the region becomes a floating state as the regions 171 are not connected to a fixed potential and determined by surrounding charge dynamics, therefore region 171 is electrically open or isolated from the source voltage).
Re Claim 19 (Currently Amended), Nakazawa teaches the semiconductor device according to Claim 17,
wherein the at least one trench separation structure includes a pair of trench separation structures (Top and Bottom Contact trench portion/Gate fingers;144; Note: 144 from Fig 18 extends around the loop from Fig 16) are arrayed in the main surface (First main surface; 103; Fig 14; ¶[0171]) at an interval (Top and Bottom contact trench portions separated in the x-direction according to Figs 16/18) in the second direction (X-direction; Fig 18) ,
the trench gate structure (Source/Main/Gate electrodes; 157/149/207; Figs 19/20; ¶[0244]) is formed in a region (Within lower region of 111; Fig 18) which is sandwiched between the pair of trench separation structures and demarcates the mesa portion (Portions between gate electrodes 149 comprising 163 and 157; Fig 18) with the pair of trench separation structures, and
the second body region (Active main surface; 171; Fig 18; ¶[0267]) is in contact (Surrounds top and bottom contact trench portions 144; Figs 16/18) with both of the pair of trench separation structures outside the mesa portion.
Re Claim 20 (Original), Nakazawa teaches the semiconductor device according to Claim 17,
wherein the chip (Semiconductor device; 101; Fig 16; ¶[00172]) has a side surface (Side of outer region 112; Figs 16/18; ¶[0188]), and
the second body region (Active main surface; 171; Fig 18; ¶[0267]) is exposed from the side surface.
Allowable Subject Matter
11. Claims 11-16 are allowed.
Regarding claim 11, the closest prior art Nakazawa, Seiya et al. (Pub No. JP 6664445 B2) (hereinafter, Nakazawa) and Hirler, Franz et al. (Pub No. US 20150333168 A1) (hereinafter, Hirler) either singularly or in combination fails to anticipate or render obvious
“The semiconductor device according to Claim 1, further comprising:
a dummy trench structure which is formed at a region between the trench separation structure and the trench gate structure in the inner region so as to penetrate through the second region and electrically separated from the trench gate structure,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, Re claim 11, Hirler discloses most of the said limitations of the semiconductor device in the broadest reasonable interpretation, with the exception of the dummy trench structure (Idle gate electrode; 155a) being electrically separated from the trench gate structure (Gate electrode; 155). Per ¶[0042] of Hirler, they are electrically and structurally connected. Further, Nakazawa in view of Hirler cannot form a predictable result if each invention were combined, due to semiconductor device of Nakazawa not comprising of a dummy trench structure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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