Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-10) in the reply filed on 2/7/2026 is acknowledged. Claims 11-20 have been withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20200212207 A1) in view of Tsai (US 20100207174 A1).
Regarding claim 1, Huang discloses a junction field effect transistor device, comprising: a substrate (Fig. 2D, 21) having a first conductivity type (para. 23 "a substrate 21 is provided, which for example has a conductivity type of P-type"); a well region (22) embedded in the substrate (Shown in fig. 2D) and having a second conductivity type that is different from the first conductivity type (Para. 21 "The channel region 22 for example has a conductivity type of N-type which is opposite to the conductivity type of the substrate 21"); a first top layer (Fig. 2F, 23) embedded in the well region (Shown in Fig. 2F, 23) and having the first conductivity type (Para. 25 "the ion implantation process step implants P-type impurities in the defined region in the form of accelerated ions..., to form the field region 23"); a plurality of source/drain regions (Fig. 2J, 25 and 26) disposed on a top surface of the well region (Shown in fig. 2J); a first isolation structure (rightmost 28) adjacent to one of the source/drain regions (26); a gate (24) disposed on a top surface of the first top layer (Shown in fig. 2J); and a first well slot (27) disposed below the gate (shown in fig. 2J), wherein a second-conductivity-type dopant concentration of the first well slot is lower than a second-conductivity-type dopant concentration of the well region (Shown in fig. 2K, Para. 26 "The N-type impurity concentration of the lightly doped region 27 is lower than the N-type impurity concentration of the channel region 22"). However, Huang does not disclose wherein the first well slot comprises a plurality of first well slots.
On the other hand, Tsai discloses wherein the first well slot comprises a plurality of first well slots (Fig. 8, 20A; para. 18 "a dopant concentration of the N-type channel region 20A' is substantially smaller than a dopant concentration of the N-type well region 20"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang according to the teachings of Tsai such that the first well slot would comprise a plurality of first well slots, in order to further increase the breakdown voltage.
Regarding claim 8, Huang further discloses a second isolation structure (leftmost 28) disposed between one of the source/drain regions and the gate (Fig. 2J shows leftmost 28 disposed between source/drain regions 25 and gate 24) and across an edge of the first top layer (Fig 2J shows leftmost 28 disposed across an edge of the first top layer 23).
Regarding claim 9, Huang and Tsai are discussed above. Huang fails to disclose the junction FET, wherein a spacing between of the first well slots is in a range of about 1 µm to about 3 µm.
However, Tsai discloses wherein a spacing between two of the first well slots is less than 20 μm (Fig. 5; para. 24 "the separated distances S of the adjacent N-type bar doped regions 20A may be smaller than 10 µm"). Nonetheless, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang in view of Tsai such that the spacing between two of the first well slots would be in a range of about 1 µm to about 3 µm as a design choice intended to tune the device to a desired breakdown voltage. Furthermore, “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, F.2d 454, 456, 105 USPQ 223, 235 (CCPA 1955).
Regarding claim 10, Huang and Tsai are discussed above. Huang fails to disclose the junction field effect transistor device, wherein a width of one of the first well slots is in a range of about 1 µm to about 2 µm.
However, Tsai discloses wherein a width of one of the first well slots is larger than 0.5 µm (Fig. 5; para. 24 "The thicknesses W of the N-type bar doped regions 20A may be bigger than 0.5 µm"). Nonetheless, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang in view of Tsai such that the width of one of the first well sots would be in a range of about 1 µm to about 2 µm as a design choice intended to tune the device to a desired breakdown voltage. Furthermore, “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, F.2d 454, 456, 105 USPQ 223, 235 (CCPA 1955).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20200212207 A1) in view of Tsai (US 20100207174 A1) as applied to claims 1 and 8-10 above, and further in view of Chan (US 20170005205 A1).
Regarding claim 3, Huang in view of Tsai discloses the junction field effect transistor device as claimed in claim 1. However, Huang in view of Tsai still does not disclose a second top layer disposed below the first isolation structure and having the first conductivity type, wherein the first top layer and the second top layer are separated by a distance.
On the other hand, Chan discloses a second top layer (Fig. 3, 116) disposed below the first isolation structure (10c) and having the first conductivity type (Para. 46 "a substrate 100 of a second conductivity type, a well region 102 of a first conductivity type…"; para. 51 "a top doped region 116 of the second conductivity type"; 116 has the opposite conductivity type to the well, but Chan labels conductivity types differently than Applicant). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang in view of Tsai according to the teachings of Chan such that a second top layer would be disposed below the first isolation structure and have the first conductivity type, and wherein the first top layer and the second top layer would be separated by a distance, in order to increase the breakdown voltage.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20200212207 A1) in view of Tsai (US 20100207174 A1) as applied to claims 1 and 8-10 above, and further in view of Chen (US 20060071247 A1).
Regarding claim 4, Huang in view of Tsai disclose the junction field effect transistor device as claimed in claim 1. However, Huang in view of Tsai does not disclose a gate field plate extending from the top surface of the first top layer to a top surface of the first isolation structure.
On the other hand, Chen discloses a gate field plate (Fig. 2B, center field plate 280 over gate 240). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang in view of Tsai according to the teachings of Chen such that the JFET device of claim 1 would further comprise a gate field plate extending from the top surface of the first top layer to a top surface of the first isolation structure, in order to reduce the peak electric field thereby increasing the breakdown voltage. Additionally, it would have been obvious to arrange said field plate such that the gate field plate would extend from the top surface of the first top layer to a top surface of the first isolation structure in order to simplify manufacturing by simply depositing a conductive layer over top of the first top layer and first isolation structure of Huang.
Regarding claim 5, Chen further discloses wherein the gate field plate is adjacent to the gate (Fig. 2B shows 280 adjacent to gate 240).
Regarding claim 6, Huang in view of Tsai discloses the junction field effect transistor device as claimed in claim 1. However, Huang in view of Tsai does not disclose a source/drain field plate disposed over a top surface of the first isolation structure and electrically connected to one of the source/drain regions.
On the other hand, Chen discloses a source/drain field plate (Fig. 2B, rightmost field plate 280 over drain region 265) electrically connected to one of the source/drain regions (Shown in Fig 2B). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang in view of Tsai according to the teachings of Chen such that a source/drain field plate would be disposed over a top surface of the first isolation structure and electrically connected to one of the source/drain regions, in order to reduce the peak electric field thereby increasing the breakdown voltage. Additionally, it would have been obvious to arrange said field plate such that he source/drain field plate would be disposed over a top surface of the first isolation structure in order to simplify manufacturing by simply depositing a conductive layer over top of the first isolation structure.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20200212207 A1) in view of Tsai (US 20100207174 A1) as applied to claims 1 and 8-10 above, and further in view of Huang (US 20140315358 A1), hereinafter referred to as Huang '2014.
Regarding clam 7, Huang ‘2020 in view of Tsai disclose the junction field effect transistor device as claimed in claim 1, and wherein the second well slots is a plurality of second well slots (Tsai: Fig. 8, 20A; para. 18 "a dopant concentration of the N-type channel region 20A' is substantially smaller than a dopant concentration of the N-type well region 20"). However, Huang ‘2020 in view of Tsai does not disclose a second well slot disposed below the first isolation structure, wherein a second-conductivity-type dopant concentration of the second well slots is lower than the second-conductivity-type dopant concentration of the well region.
On the other hand, Huang ‘2014 discloses a second well slot (Fig. 2L, 27) disposed below the first isolation structure (28), wherein a second-conductivity-type dopant concentration of the second well slots is lower than the second-conductivity-type dopant concentration of the well region (Para. 30 "the lightly doped region 27 has an N-type impurity concentration which is lower than an N-type impurity concentration of the channel region 22"). It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Huang ‘2020 in view of Tsai according to the teachings of Huang ‘2014 such that the device of claim 1 would further comprise a second well slot disposed below the first isolation structure, wherein a second-conductivity-type dopant concentration of the second well slots is lower than the second-conductivity-type dopant concentration of the well region, and wherein the second well slot is a plurality of second well slots, in order to improve the uniformity of the electric field along the drift region.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record does not disclose wherein the first well slots pass through the first top layer.
Conclusion
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/S.J.S./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817