DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/25/2023, 5/28/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimomura (US 2019/0252541).
Regarding claim 1, Shimomura discloses, in at least figures 1-6D and related text, a semiconductor device comprising:
a chip (100, [30]) having a main surface (upper surface of S, substrate, [54], figures);
a groove structure (structure of 11/10/12/14/15/35, [34], figures) including a groove (T1, [54]) formed at the main surface (upper surface of S, substrate, [54], figures), a source electrode (10, [34]) that is embedded in the groove (T1, [54]) at a bottom side of the groove (T1, [54]) and that has a projection portion on one side (portion of 10 on one side of both sides of 14 in lateral, y, direction, figures 1, 3B) and a projection portion on the other side (portion of 10 on the other side of both sides of 14 in lateral, y, direction, figures 1, 3B) both of which protrude toward an opening side (upper side of T1, figures) of the groove (T1, [54]), and a gate electrode (14, [34]) embedded between a pair of the projection portions (portion of 10 on both sides of 14 in lateral, y, direction, figure 3B) at the opening side of the groove (T1, [54]); and
a source via electrode (42, [32], figure 3B) on one side (one side of both sides of 14 in lateral, y, direction, figures 1, 3B) and a source via electrode (42, [32], figure 3B) on the other side (the other side of both sides of 14 in lateral, y, direction, figures 1, 3B) that are connected to the projection portion on the one side (portion of 10 on one side of both sides of 14 in lateral, y, direction, figures 1, 3B) and the projection portion on the other side (portion of 10 on the other side of both sides of 14 in lateral, y, direction, figures 1, 3B), respectively, on the groove structure (structure of 11/10/12/14/15/35, [34], figures).
Regarding claim 2, Shimomura discloses the semiconductor device according to Claim 1 as described above.
Shimomura further discloses, in at least figures 1-6D and related text, the semiconductor device does not have a gate via electrode connected to the gate electrode (14, [34]) on the groove structure (structure of 11/10/12/14/15/35, [34], figures).
Claim(s) 1, 12, 14 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zitouni (US 2016/0064546).
Regarding claim 1, Zitouni discloses, in at least figures 1-9 and related text, a semiconductor device comprising:
a chip (100, [38]) having a main surface (upper surface of 106/202, [43], figures);
a groove structure (structure of 210/130/212/125/214, [43]) including a groove (114-117, [39]) formed at the main surface (upper surface of 106/202, [43], figures), a source electrode (130, [49]) that is embedded in the groove (114-117, [39]) at a bottom side of the groove (114-117, [39]) and that has a projection portion on one side (portion of 130 on one side of both sides of 125 in lateral, y direction, figure 2) and a projection portion on the other side (portion of 130 on the other side of both sides of 125 in lateral, y direction, figure 2) both of which protrude toward an opening side (upper side of 114-117, figures) of the groove (114-117, [39]), and a gate electrode (125, [49]) embedded between a pair of the projection portions (portion of 130 on both sides of 125 in lateral, y direction, figure 2) at the opening side of the groove (114-117, [39]); and
a source via electrode (224, [44]) on one side (one side of both sides of 125 in lateral, y direction, figure 2) and a source via electrode (224, [44]) on the other side (the other side of both sides of 125 in lateral, y direction, figure 2) that are connected to the projection portion on the one side (portion of 130 on one side of both sides of 125 in lateral, y direction, figure 2) and the projection portion on the other side (portion of 130 on the other side of both sides of 125 in lateral, y direction, figure 2), respectively, on the groove structure (structure of 210/130/212/125/214, [43]).
Regarding claim 12, Zitouni discloses, in at least figures 1-9 and related text, a semiconductor device comprising:
a chip (100, [38]) having a main surface (upper surface of 106/202, [43], figures);
a first groove structure (structure of 210/130/212/125/214 in 115, [39], [43]) including a first groove (115, [39]) formed at the main surface (upper surface of 106/202, [43], figures), a first source electrode (130 in 115, [49]) that is embedded in the first groove (115, [39]) at a bottom side of the first groove (115, [39]) and that has a first projection portion on one side (portion of 130 in 115 on one side of both sides of 125 in lateral, y direction, figure 2) and a first projection portion on the other side (portion of 130 in 115 on the other side of both sides of 125 in lateral, y direction, figure 2) both of which protrude toward an opening side (upper side of 115, figures) of the first groove (115, [39]), and a first gate electrode (125 in 115, [49]) embedded between a pair of the first projection portions (portion of 130 in 115 on both sides of 125 in lateral, y direction, figure 2) at the opening side (upper side of 115, figures) of the first groove (116, [39]);
a second groove structure (structure of 210/130/212/125/214 in 114, [39], [43]) including a second groove (114, [39]) that adjoins the first groove (115, [39]) and that is formed at the main surface (upper surface of 106/202, [43], figures), a second source electrode (130 in 114, [49]) that is embedded in the second groove (114, [39]) at a bottom side of the second groove (114, [39]) and that has a second projection portion on one side (portion of 130 in 114 on one side of both sides of 125 in lateral, y direction, figure 2) and a second projection portion on the other side (portion of 130 in 114 on the other side of both sides of 125 in lateral, y direction, figure 2) both of which protrude toward an opening side (upper side of 114, figures) of the second groove (114, [39]), and a second gate electrode (125 in 114, [49]) embedded between a pair of the second projection portions (portion of 130 in 114 on both sides of 125 in lateral, y direction, figure 2) at the opening side (upper side of 114, figures) of the second groove (114, [39]);
a first source via electrode (224, [44]) connected to the first projection portion on the one side (portion of 130 in 115 on one side of both sides of 125 in lateral, y direction, figure 2) on the first groove structure (structure of 210/130/212/125/214 in 115, [39], [43]);
a second source via electrode (224, [44]) on one side (one side of both sides of 125 in lateral, y direction, figure 2) and a second source via electrode (224, [44]) on the other side (the other side of both sides of 125 in lateral, y direction, figure 2) that are connected to the second projection portion on the one side (portion of 130 in 114 on one side of both sides of 125 in lateral, y direction, figure 2) and the second projection portion on the other side (portion of 130 in 114 on the other side of both sides of 125 in lateral, y direction, figure 2), respectively, on the second groove structure (structure of 210/130/212/125/214 in 114, [39], [43]); and
a gate via electrode (220, [44]) connected to the first gate electrode (125 in 115, [49]) on the first groove structure (structure of 210/130/212/125/214 in 115, [39], [43]).
Regarding claim 14, Zitouni discloses the semiconductor device according to Claim 12 as described above.
Zitouni further discloses, in at least figures 1-9 and related text, a gate wiring (218, [44]) that is arranged above the first groove structure (structure of 210/130/212/125/214 in 115, [39], [43]) so as to overlap with the first gate electrode (125 in 115, [49]) in a plan view and that is connected to the gate via electrode (220, [44]); and
a source wiring (222, [44]) that is arranged above the first groove structure (structure of 210/130/212/125/214 in 115, [39], [43]) and above the second groove structure (structure of 210/130/212/125/214 in 114, [39], [43]) so as to overlap with the first projection portion on the one side (portion of 130 in 115 on one side of both sides of 125 in lateral, y direction, figure 2) and with the pair of the second projection portions (portion of 130 in 114 on the other side of both sides of 125 in lateral, y direction, figure 2) in a plan view and that is connected to the first source via electrode (224, [44]) and to a pair of the second source via electrodes (224, [44]).
Regarding claim 19, Zitouni discloses the semiconductor device according to Claim 12 as described above.
Zitouni further discloses, in at least figures 1-9 and related text, the second projection portion on the one side (portion of 130 in 114 on the other side of both sides of 125 in lateral, y direction, figure 2) faces the first projection portion on the one side (portion of 130 in 115 on the other side of both sides of 125 in lateral, y direction, figure 2) across a part of the chip (100, [38]), and
the second projection portion on the other side (portion of 130 in 114 on the other side of both sides of 125 in lateral, y direction, figure 2) faces the first projection portion on the other side (portion of 130 in 115 on the other side of both sides of 125 in lateral, y direction, figure 2) and the first gate electrode (125 in 115, [49]) across a part of the chip (100, [38]).
Regarding claim 20, Zitouni discloses the semiconductor device according to Claim 19 as described above.
Zitouni further discloses, in at least figures 1-9 and related text, the second source via electrode (224, [44]) on the other side (the other side of both sides of 125 in lateral, y direction, figure 2) is connected to the second projection portion on the other side (portion of 130 in 114 on the other side of both sides of 125 in lateral, y direction, figure 2) at a position close to the second gate electrode (125 in 114, [49]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shimomura (US 2019/0252541) in view of Kachi (US 2006/0157779).
Regarding claim 6, Shimomura discloses the semiconductor device according to Claim 1 as described above.
Shimomura does not explicitly disclose a groove connection structure including a connection groove formed at the main surface so as to communicate with the groove and a gate connection electrode embedded in the connection groove so as to be connected to the gate electrode.
Kachi teaches, in at least figures 3-4, 15, and related text, the device comprising a groove connection structure (19, [73]) including a connection groove (trench of 19, figures) formed at the main surface so as to communicate with the groove (trench of Qc, [62]) and a gate connection electrode (9E of 19, [73]) embedded in the connection groove (trench of 19, figures) so as to be connected to the gate electrode (9E of Qc, [63]), for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9]).
Shimomura and Kachi are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Shimomura with the specified features of Kachi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Shimomura to have the groove connection structure including a connection groove formed at the main surface so as to communicate with the groove and a gate connection electrode embedded in the connection groove so as to be connected to the gate electrode, as taught by Kachi, for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9], Kachi).
Regarding claim 7, Shimomura in view of Kachi discloses the semiconductor device according to Claim 6 as described above.
Kachi further teaches, in at least figures 3-4, 15, and related text, the gate connection electrode (9E of 19, [73]) imparts a gate potential to the gate electrode (9E of Qc, [63]), for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9]).
Regarding claim 8, Shimomura in view of Kachi discloses the semiconductor device according to Claim 6 as described above.
Kachi further teaches, in at least figures 3-4, 15, and related text, a source connection electrode (7E of 19, [73]) embedded in the connection groove (trench of 19, figures) at a bottom side of the connection groove (trench of 19, figures) so as to be connected to the source electrode (7E of Qc, [63]); wherein the gate connection electrode (9E of 19, [73]) is embedded in the connection groove (trench of 19, figures) at an opening side of the connection groove (trench of 19, figures), for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9]).
Regarding claim 9, Shimomura in view of Kachi discloses the semiconductor device according to Claim 8 as described above.
Kachi further teaches, in at least figures 3-4, 15, and related text, the gate connection electrode (9E of 19, [73]) faces a whole area of the source connection electrode (7E of 19, [73]) in a plan view (figures), for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9]).
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zitouni (US 2016/0064546) in view of Kachi (US 2006/0157779).
Regarding claim 17, Zitouni discloses the semiconductor device according to Claim 12 as described above.
Zitouni does not explicitly disclose a groove connection structure including a connection groove formed at the main surface so as to communicate with the first groove and with the second groove and a gate connection electrode embedded in the connection groove so as to be connected to the first gate electrode and to the second gate electrode.
Kachi teaches, in at least figures 3-4, 15, and related text, the device comprising a groove connection structure (19, [73]) including a connection groove (trench of 19, figures) formed at the main surface so as to communicate with the first groove (trench of one of Qc, [62]) and with the second groove (trench of the other of Qc, [62]) and a gate connection electrode (9E of 19, [73]) embedded in the connection groove (trench of 19, figures) so as to be connected to the first gate electrode (9E of one of Qc, [63]) and to the second gate electrode (9E of the other one of Qc, [63]), for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9]).
Zitouni and Kachi are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Zitouni with the specified features of Kachi because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Zitouni to have the groove connection structure including a connection groove formed at the main surface so as to communicate with the first groove and with the second groove and a gate connection electrode embedded in the connection groove so as to be connected to the first gate electrode and to the second gate electrode, as taught by Kachi, for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9], Kachi).
Regarding claim 18, Zitouni in view of Kachi discloses the semiconductor device according to Claim 17 as described above.
Kachi further teaches, in at least figures 3-4, 15, and related text, a source connection electrode (7E of 19, [73]) embedded in the connection groove (trench of 19, figures) at a bottom side of the connection groove (trench of 19, figures) so as to be connected to the first gate electrode (9E of one of Qc, [63]) and to the second gate electrode (9E of the other one of Qc, [63]); wherein the gate connection electrode (9E of 19, [73]) is embedded in the connection groove (trench of 19, figures) at an opening side of the connection groove (trench of 19, figures), for the purpose of provide a technique that makes it possible to reduce the on-resistance of a semiconductor device having a field-effect transistor with a trench gate structure ([9]).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 3 that recite "a gate wiring arranged above the groove structure so as not to overlap with the gate electrode in a plan view; a source wiring that is arranged above the groove structure so as to overlap with the pair of the projection portions and with the gate electrode in a plan view and that is connected to a pair of the source via electrodes" in combination with other elements of the base claims 1 and 3.
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 10 that recite "the projection portion on the other side is longer than the projection portion on the one side" in combination with other elements of the base claims 1 and 10.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 12 and 13 that recite "the semiconductor device does not have a gate via electrode connected to the second gate electrode on the second groove structure" in combination with other elements of the base claims 12 and 13.
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 12, 14, and 15 that recite "the gate wiring does not overlap with the second gate electrode in a plan view, and the source wiring overlaps with the first gate electrode and with the second gate electrode in a plan view" in combination with other elements of the base claims 12, 14, and 15.
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 12, 14, and 16 that recite "the source wiring overlaps with a whole area of the second gate electrode in a plan view" in combination with other elements of the base claims 12, 14, and 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811