DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jennings et al. (US 20210376834).
Regarding claim 1, Jennings discloses that a semiconductor device, comprising:
a first chip 132 and a second chip 138 that are joined together, a plurality of power domains 144, 146, being configured in the first chip 132, wherein: the first chip 132 includes a plurality of individual switches 11, 12, 21, (para. 0029, note: microprocess memories - - logic functions as switch) and a first connection terminal , the plurality of individual switches being provided in respective correspondence with the plurality of power domains 144, 146, each of the individual switches switching between a state of supplying a power supply voltage to the power domain (para. 0029) and a state of not supplying the power supply voltage, and the first connection terminal being connected in common to the plurality of individual switches 184, 186, 188 (a Mux is the switch in general), and the second chip 138 includes a second connection terminal 154 and a common switch 184, 186, 188, the second connection terminal being connected to the first connection terminal 158, the common switch being provided between a power supply and the second connection terminal (Fig. 1A-1B), and the common switch switching between a state of supplying the power supply voltage in common to the plurality of power domains and a state of not supplying the power supply voltage.
Jennings is silent that leakage currents being smaller in the second chip than in the first chip.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain amount of leakage current in the first and second chip, because it would have been to obtain a certain amount of leakage current in the first and second chip to achieve effectively operate power domains (if leakage current is larger in a regulator, effective supply of voltage cannot be achieved).
Reclaim 2, Jennings fails to specify that the first chip is formed with a first process size, and the second chip is formed with a second process size that is larger than the first process size.
However, notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization.
Before effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use a certain size of chip, because it would have been to obtain a certain size of chip to achieve effective controlling of power domains (more regulator can be implemented on the second chips to individually controlling each power domain).
Reclaim 3, Jennings discloses that the first chip includes an external connection terminal that connects from outside the first chip to between the first connection terminal and the plurality of individual switches (Fig. 1A-1B).
Conclusion
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/SU C KIM/ Primary Examiner, Art Unit 2899
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