Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/09/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17 is rejected under 35 U.S.C. 102(a)(1)/ 102(a)(2) as being anticipated by Xie et al. (U.S. 2022/0399224 A1, hereinafter refer to Xie).
Regarding Claim 17: Xie discloses a semiconductor device (see Xie, Figs.9 and 19 as shown below and ¶ [0003]) comprising:
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a semiconductor substrate (102/104/106) including a first side and a second side that are opposite to each other in a first direction (see Xie, Fig.9 as shown above);
a fin-shaped pattern (107) protruding from the first side of the substrate (102/104/106) in the first direction and extending in a second direction (see Xie, Fig.9 as shown above);
a source/drain pattern (116) on the fin-shaped pattern (107) and connected to the fin- shaped pattern (107) (see Xie, Fig.9 as shown above);
a source/drain contact (118) on the source/drain pattern (116) and connected to the source/drain pattern (116) (see Xie, Fig.9 as shown above);
a back wiring line (backside power/242) on the second side of the substrate (102/104/106) (see Xie, Figs.9 and 19 as shown above and ¶ [0043]);
a contact connecting via connected to the source/drain contact (116) and extending in the first direction (see Xie, Fig.9 as shown above); and
a buried conductive pattern (130) inside the semiconductor substrate (102/104/106) and connecting the contact connecting via and the back wiring line (backside power/242) (see Xie, Figs.9 and 19 as shown above and ¶ [0043]),
wherein the buried conductive pattern (130) includes a first portion and a second portion (see Xie, Fig.9 as shown above),
the second portion of the buried conductive pattern (130) is between the first portion of the buried conductive pattern (130) and the contact connecting via (see Xie, Fig.9 as shown above),
the first portion of the buried conductive pattern (130) has a line shape extending in the second direction longer than a length in the first direction of the second portion (see Xie, Fig.9 as shown above), and
the second portion of the buried conductive pattern (130) protrudes from the first portion of the buried conductive pattern (130) in the first direction (see Xie, Fig.9 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2022/0399224 A1, hereinafter refer to Xie) in view of CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO).
Regarding Claim 1: Xie discloses a semiconductor device (see Xie, Figs.9 and 19 as shown below and ¶ [0003]) comprising:
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a semiconductor substrate (102/104/106) including a first side and a second side that are opposite to each other in a first direction (see Xie, Fig.9 as shown above);
a fin-shaped pattern (107) protruding from the first side of the substrate (102/104/106) in the first direction, and extending in a second direction (see Xie, Fig.9 as shown above);
a source/drain pattern (116) on the fin-shaped pattern (107) and connected to the fin- shaped pattern (107) (see Xie, Fig.9 as shown above);
a source/drain contact (118) on the source/drain pattern (116) and connected to the source/drain pattern (116) (see Xie, Fig.9 as shown above);
a back wiring line (backside power/242) on the second side of the substrate (102/104/106) (see Xie, Figs.9 and 19 as shown above and ¶ [0043]);
a contact connecting via connected to the source/drain contact (118), and extending in the first direction (see Xie, Fig.9 as shown above); and
a buried conductive pattern (130) inside the semiconductor substrate (102/104/106), and connecting the contact connecting via and the back wiring line (backside power/242) (see Xie, Figs.9 and 19 as shown above),
wherein the buried conductive pattern (130) includes a first portion and a second portion (see Xie, Figs.9 and 19 as shown above),
the second portion of the buried conductive pattern (130) is between the first portion of the buried conductive pattern (130) and the contact connecting via (see Xie, Figs.9 and 19 as shown above),
at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern (130) decreases, as the buried conductive pattern goes toward the back wiring line (backside power/242) (see Xie, Figs.9 and 19 as shown above),
at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern (130) increases, as the buried conductive pattern goes away from the back wiring line (backside power/242) (see Xie, Figs.9 and 19 as shown above),
the first portion of the buried conductive pattern has a line shape extending in the second direction longer than a length in the first direction of the second portion (see Xie, Fig.9 as shown above), and
the second portion of the buried conductive pattern protrudes from the first portion of the buried conductive pattern in the first direction (see Xie, Fig.9 as shown above).
Xie is silent upon explicitly disclosing wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown below and ¶ [0143]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and CHO to enable the width of the first portion of the buried conductive pattern Xie’s to decreases in third direction, as the buried conductive pattern goes away from the back wiring line as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 2: Xie as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Xie and CHO further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Regarding Claim 3: Xie as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Xie and CHO further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Fig.9A as shown below and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction is constant (see CHO, Fig.9A as shown below and ¶ [0143]).
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Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 6: Xie as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Xie and CHO further teaches wherein a field insulating film (112) which on the first side of the substrate (102/104/106) and covering side walls of the fin-shaped pattern (107), wherein a part of the contact connecting via is inside the field insulating film (112) (see Xie, Fig.9 as shown above).
Regarding Claim 7: Xie as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Xie and CHO further teaches wherein the contact connecting via at least partly overlaps the source/drain contact (118) in the third direction (see Xie, Fig.9 as shown above).
Regarding Claim 8: Xie as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Xie and CHO further teaches wherein a front wiring structure (144/146) on the first side of the substrate (150) (see CHO, Figs.9A and 12 as shown above),
wherein the front wiring structure (144/146) includes a front wiring line (144/146) extending in the second direction, and connecting the source/drain contact (140) and the contact connecting via (137) (see CHO, Figs.9A and 12 as shown above).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2022/0399224 A1, hereinafter refer to Xie) and CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO) as applied to claim 1 above, and further in view of HSU et al. (U.S. 2017/0222008 A1, hereinafter refer to HSU).
Regarding Claim 5: Xie as modified teaches a semiconductor device as applied to claim 1 above. The combination of Xie and CHO is silent upon explicitly disclosing wherein a connecting via silicide film between the buried conductive pattern and the contact connecting via.
For support see HSU, which teaches wherein a connecting via silicide film (80) between the conductive pattern (110) and the contact connecting via (75) (see HSU, Fig.9 and ¶ [0065]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie, CHO, and HSU to enable connecting via silicide film between the buried conductive pattern and the contact connecting via of Xie’s as taught by HSU in order to functions as a passivation layer that can protect the underlying metal layer (e.g., Co) from being oxidized or damaged in air or during subsequent manufacturing operations and it function as an etch stop layer when the contact opening for a via plus is formed, thereby preventing the via from passing to the underlying layer.
Claim(s) 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2022/0399224 A1, hereinafter refer to Xie) in view of CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO) and HSU et al. (U.S. 2017/0222008 A1, hereinafter refer to HSU).
Regarding Claim 11: Xie discloses a semiconductor device (see Xie, Figs.9 and 19 as shown above and ¶ [0003]) comprising:
a semiconductor substrate (102/104/106) including a first side and a second side that are opposite to each other in a first direction (see Xie, Fig.9 as shown above);
a fin-shaped pattern (107) protruding from the first side of the substrate (102/104/106) in the first direction and extending in a second direction (see Xie, Fig.9 as shown above);
a source/drain pattern (116) on the fin-shaped pattern (107) and connected to the fin- shaped pattern (107) (see Xie, Fig.9 as shown above);
a source/drain contact (118) on the source/drain pattern (116) and connected to the source/drain pattern (116) (see Xie, Fig.9 as shown above);
a back wiring line (backside power/242) on the second side of the substrate (102/104/106) (see Xie, Figs.9 and 19 as shown above and ¶ [0043]);
a contact connecting via connected to the source/drain contact (116) and extending in the first direction (see Xie, Fig.9 as shown above);
a buried conductive pattern (130) inside the semiconductor substrate (102/104/106), and connecting the contact connecting via and the back wiring line (backside power/242) (see Xie, Figs.9 and 19 as shown above and ¶ [0043]); and
wherein the buried conductive pattern (130) includes a first portion and a second portion (see Xie, Fig.9 as shown above),
the second portion of the buried conductive pattern (130) is between the first portion of the buried conductive pattern (130) and the contact connecting via (see Xie, Fig.9 as shown above),
at the first portion of the buried conductive pattern (130), a width in a third direction of the buried conductive pattern (130) is constant (see Xie, Fig.9 as shown above),
the first portion of the buried conductive pattern (130) has a line shape extending in the second direction longer than a length in the first direction of the second portion (see Xie, Fig.9 as shown above), and
the second portion of the buried conductive pattern (130) protrudes from the first portion of the buried conductive pattern (130) in the first direction (see Xie, Fig.9 as shown above).
Xie is silent upon explicitly disclosing wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and CHO to enable the second portion of the buried conductive pattern of Xie’s to have the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
The combination of Xie and CHO is silent upon explicitly disclosing wherein a connecting via silicide film between the buried conductive pattern and the contact connecting via.
For support see HSU, which teaches wherein a connecting via silicide film (80) between the conductive pattern (110) and the contact connecting via (75) (see HSU, Fig.9 and ¶ [0065]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie, CHO, and HSU to enable connecting via silicide film between the buried conductive pattern and the contact connecting via of the combination of Xie’s and CHO’s as taught by HSU in order to functions as a passivation layer that can protect the underlying metal layer (e.g., Co) from being oxidized or damaged in air or during subsequent manufacturing operations and it function as an etch stop layer when the contact opening for a via plus is formed, thereby preventing the via from passing to the underlying layer.
Regarding Claim 12: Xie as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Xie, CHO, and HSU further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 13: Xie as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Xie, CHO, and HSU further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Fig.9A as shown above and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction is constant (see CHO, Fig.9A as shown above and ¶ [0143]).
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 15: Xie as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Xie, CHO, and HSU further teaches wherein the contact connecting via at least partly overlaps the source/drain contact (118) in the third direction (see Xie, Fig.9 as shown above).
Regarding Claim 16: Xie as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Xie, CHO, and HSU further teaches wherein a front wiring structure (144/146) disposed on the first side of the substrate (150), wherein the front wiring structure (144/146) includes a front wiring line (144/146) extending in the second direction (see CHO, Figs.9A and 12 as shown above), and
the front wiring line (144/146) connects the source/drain contact (140) and the contact connecting via (137) (see CHO, Figs.9A and 12 as shown above).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2022/0399224 A1, hereinafter refer to Xie) as applied to claim 17 above, and further in view of HSU et al. (U.S. 2017/0222008 A1, hereinafter refer to HSU).
Regarding Claim 18: Xie discloses a semiconductor device as applied to claim 17 above. Xie is silent upon explicitly disclosing wherein a connecting via silicide film between the buried conductive pattern and the contact connecting via.
For support see HSU, which teaches wherein a connecting via silicide film (80) between the conductive pattern (110) and the contact connecting via (75) (see HSU, Fig.9 and ¶ [0065]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and HSU to enable connecting via silicide film between the buried conductive pattern and the contact connecting via of Xie’s as taught by HSU in order to functions as a passivation layer that can protect the underlying metal layer (e.g., Co) from being oxidized or damaged in air or during subsequent manufacturing operations and it function as an etch stop layer when the contact opening for a via plus is formed, thereby preventing the via from passing to the underlying layer.
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (U.S. 2022/0399224 A1, hereinafter refer to Xie) as applied to claim 17 above, and further in view of CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO).
Regarding Claim 19: Xie discloses a semiconductor device as applied to claim 17 above. Xie is silent upon explicitly disclosing wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line, and
at the second portion of the buried conductive pattern, the width in the third direction increases of the buried conductive pattern, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]), and
at the second portion of the buried conductive pattern, the width in the third direction increases of the buried conductive pattern, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and CHO to enable the know configuration of buried conductive pattern as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 20: Xie discloses a semiconductor device as applied to claim 17 above. Xie teaches wherein at the first portion of the buried conductive pattern (130), a width in a third direction of the buried conductive pattern is constant (see Xie, Fig.9 as shown above); however, Xie is silent upon explicitly disclosing wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Xie and CHO to enable the know configuration of buried conductive pattern as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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