Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line" in lines 19-21. Claim 1 further recites a limitation of “the first portion of the buried conductive pattern has a line shape extending in the second direction” in lines 25-26. It is unclear how “first portion of the buried conductive pattern” has a line shape while the “the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line.”
Claims 2-3 and 5-10 are rejected as if depending on rejected claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki et al. (U.S. 2020/0365509 A1, hereinafter refer to Sasaki).
Regarding Claim 17: Sasaki discloses a semiconductor device (see Sasaki, Fig.2B as shown below and ¶ [0004]) comprising:
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a substrate (SL) including a first side and a second side that are opposite to each other in a first direction (see Sasaki, Fig.2B as shown above);
a fin-shaped pattern (FN) protruding from the first side of the substrate (SL) in the first direction and extending in a second direction (see Sasaki, Fig.2B as shown above);
a source/drain pattern (SD) on the fin-shaped pattern (FN) and connected to the fin- shaped pattern (FN) (see Sasaki, Fig.2B as shown above);
a source/drain contact (BP) on the source/drain pattern (SD) and connected to the source/drain pattern (SD) (see Sasaki, Fig.2B as shown above);
a back wiring line (PON) on the second side of the substrate (SL) (see Sasaki, Fig.2B as shown above);
a contact connecting via (EP) connected to the source/drain contact (BP) and extending in the first direction (see Sasaki, Fig.2B as shown above); and
a buried conductive pattern (TV/POR) inside the substrate (SL) and connecting the contact connecting via (EP) and the back wiring line (TV/POR) (see Sasaki, Fig.2B as shown above),
wherein the buried conductive pattern (TV/POR) includes a first portion (TV) and a second portion (POR) (see Sasaki, Fig.2B as shown above),
the second portion of the buried conductive pattern (POR) is between the first portion of the buried conductive pattern (TV) and the contact connecting via (EP) (see Sasaki, Fig.2B as shown above),
the first portion of the buried conductive pattern (TV) has a line shape extending in the second direction (see Sasaki, Fig.2B as shown above), and
the second portion of the buried conductive pattern (POR) protrudes from the first portion of the buried conductive pattern (TV) in the first direction (see Sasaki, Fig.2B as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (U.S. 2020/0365509 A1, hereinafter refer to Sasaki) in view of CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO).
Regarding Claim 1: Sasaki discloses a semiconductor device (see Sasaki, Fig.2B as shown below and ¶ [0004]) comprising:
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a substrate (SL) including a first side and a second side that are opposite to each other in a first direction (see Sasaki, Fig.2B as shown above);
a fin-shaped pattern (FN) protruding from the first side of the substrate (SL) in the first direction, and extending in a second direction (see Sasaki, Fig.2B as shown above);
a source/drain pattern (SD) on the fin-shaped pattern (FN) and connected to the fin- shaped pattern (FN) (see Sasaki, Fig.2B as shown above);
a source/drain contact (BP) on the source/drain pattern (SD) and connected to the source/drain pattern (SD) (see Sasaki, Fig.2B as shown above);
a back wiring line (PON) on the second side of the substrate (SL) (see Sasaki, Fig.2B as shown above);
a contact connecting via (EP) connected to the source/drain contact (BP), and extending in the first direction (see Sasaki, Fig.2B as shown above); and
a buried conductive pattern (TV/POR) inside the substrate (SL), and connecting the contact connecting via (EP) and the back wiring line (PON) (see Sasaki, Fig.2B as shown above),
wherein the buried conductive pattern (TV/POR) includes a first portion (TV) and a second portion (POR) (see Sasaki, Fig.2B as shown above),
the second portion of the buried conductive pattern (POR) is between the first portion of the buried conductive pattern (TV) and the contact connecting via (EP) (see Sasaki, Fig.2B as shown above),
the first portion of the buried conductive pattern (TV) has a line shape extending in the second direction (see Sasaki, Fig.2B as shown above), and
the second portion of the buried conductive pattern (POR) protrudes from the first portion of the buried conductive pattern (TV) in the first direction (see Sasaki, Fig.2B as shown above).
Sasaki is silent upon explicitly disclosing wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line, and
at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown below and ¶ [0143]), and
at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown below and ¶ [0143]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki and CHO to enable the know configuration of buried conductive pattern as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 2: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Regarding Claim 3: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Fig.9A as shown below and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction is constant (see CHO, Fig.9A as shown below and ¶ [0143]).
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Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 6: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein a field insulating film (ST) which on the first side of the substrate (SL) and covering side walls of the fin-shaped pattern (FN), wherein a part of the contact connecting via (EP) is inside the field insulating film (ST) (see Sasaki, Fig.2B as shown above).
Regarding Claim 7: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein the contact connecting via (EP) at least partly overlaps the source/drain contact (BP) in the third direction (see Sasaki, Fig.2B as shown above).
Regarding Claim 8: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein a front wiring structure (UML/UV) on the first side of the substrate (SL) (see Sasaki, Fig.2B as shown above),
wherein the front wiring structure (UML/UV) includes a front wiring line (UV) extending in the second direction, and connecting the source/drain contact (BP) and the contact connecting via (EP) (see Sasaki, Fig.2B as shown above and Fig.3).
Regarding Claim 9: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein the substrate (SL) includes a semiconductor substrate (see Sasaki, Fig.2B as shown above and ¶ [0017]).
Regarding Claim 10: Sasaki as modified teaches a semiconductor device as set forth in claim 1 as above. The combination of Sasaki and CHO further teaches wherein the substrate (SL) comprises a semiconductor substrate (SL) and an insulating substrate (LIL1), and the semiconductor substrate comprises the first side of the substrate (see Sasaki, Fig.2B as shown above).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (U.S. 2020/0365509 A1, hereinafter refer to Sasaki) and CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO) as applied to claim 1 above, and further in view of HSU et al. (U.S. 2017/0222008 A1, hereinafter refer to HSU).
Regarding Claim 5: Sasaki as modified teaches a semiconductor device as applied to claim 1 above. The combination of Sasaki and CHO is silent upon explicitly disclosing wherein a connecting via silicide film between the buried conductive pattern and the contact connecting via.
For support see HSU, which teaches wherein a connecting via silicide film (80) between the conductive pattern (110) and the contact connecting via (75) (see HSU, Fig.9 and ¶ [0065]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki, CHO, and HSU to enable connecting via silicide film between the buried conductive pattern and the contact connecting via of Sasaki as taught by HSU in order to functions as a passivation layer that can protect the underlying metal layer (e.g., Co) from being oxidized or damaged in air or during subsequent manufacturing operations and it function as an etch stop layer when the contact opening for a via plus is formed, thereby preventing the via from passing to the underlying layer.
Claim(s) 11-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (U.S. 2020/0365509 A1, hereinafter refer to Sasaki) in view of CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO) and HSU et al. (U.S. 2017/0222008 A1, hereinafter refer to HSU).
Regarding Claim 11: Sasaki discloses a semiconductor device (see Sasaki, Fig.2B as shown above and ¶ [0004]) comprising:
a substrate (SL) including a first side and a second side that are opposite to each other in a first direction (see Sasaki, Fig.2B as shown above);
a fin-shaped pattern (FN) protruding from the first side of the substrate (SL) in the first direction and extending in a second direction (see Sasaki, Fig.2B as shown above);
a source/drain pattern (SD) on the fin-shaped pattern (FN) and connected to the fin- shaped pattern (FN) (see Sasaki, Fig.2B as shown above);
a source/drain contact (BP) on the source/drain pattern (SD) and connected to the source/drain pattern (SD) (see Sasaki, Fig.2B as shown above);
a back wiring line (PON) on the second side of the substrate (SL) (see Sasaki, Fig.2B as shown above);
a contact connecting via (EP) connected to the source/drain contact (BP) and extending in the first direction (see Sasaki, Fig.2B as shown above);
a buried conductive pattern (TV/POR) inside the substrate (SL), and connecting the contact connecting via (EP) and the back wiring line (PON) (see Sasaki, Fig.2B as shown above); and
wherein the buried conductive pattern (TV/POR) includes a first portion (TV) and a second portion (POR) (see Sasaki, Fig.2B as shown above),
the second portion of the buried conductive pattern (POR) is between the first portion of the buried conductive pattern (TV) and the contact connecting via (EP) (see Sasaki, Fig.2B as shown above),
at the first portion of the buried conductive pattern (TV), a width in a third direction of the buried conductive pattern is constant (see Sasaki, Fig.2B as shown above), and
the first portion of the buried conductive pattern (TV) has a line shape extending in the second direction (see Sasaki, Fig.2B as shown above), and
the second portion of the buried conductive pattern (POR) protrudes from the first portion of the buried conductive pattern (TV) in the first direction (see Sasaki, Fig.2B as shown above).
Sasaki is silent upon explicitly disclosing wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki and CHO to enable the second portion of the buried conductive pattern of Sasaki to have the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
The combination of Sasaki and CHO is silent upon explicitly disclosing wherein a connecting via silicide film between the buried conductive pattern and the contact connecting via.
For support see HSU, which teaches wherein a connecting via silicide film (80) between the conductive pattern (110) and the contact connecting via (75) (see HSU, Fig.9 and ¶ [0065]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki, CHO, and HSU to enable connecting via silicide film between the buried conductive pattern and the contact connecting via of the combination of Sasaki and CHO as taught by HSU in order to functions as a passivation layer that can protect the underlying metal layer (e.g., Co) from being oxidized or damaged in air or during subsequent manufacturing operations and it function as an etch stop layer when the contact opening for a via plus is formed, thereby preventing the via from passing to the underlying layer.
Regarding Claim 12: Sasaki as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Sasaki, CHO, and HSU further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 13: Sasaki as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Sasaki, CHO, and HSU further teaches wherein the buried conductive pattern (174/156) further comprises a third portion between the second portion of the buried conductive pattern and the contact connecting via (137) (see CHO, Fig.9A as shown above and ¶ [0143]), and
at the third portion of the buried conductive pattern, the width of the buried conductive pattern in the third direction is constant (see CHO, Fig.9A as shown above and ¶ [0143]).
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 15: Sasaki as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Sasaki, CHO, and HSU further teaches wherein the contact connecting via (EP) at least partly overlaps the source/drain contact (BP) in the third direction (see Sasaki, Fig.2B as shown above).
Regarding Claim 16: Sasaki as modified teaches a semiconductor device as set forth in claim 11 as above. The combination of Sasaki, CHO, and HSU further teaches wherein a front wiring structure (UV/UML) disposed on the first side of the substrate (SL), wherein the front wiring structure (UV/UML) includes a front wiring line (UV/UML) extending in the second direction (see Sasaki, Fig.2B as shown above), and
the front wiring line (UV/UML) connects the source/drain contact (BP) and the contact connecting via (EP) (see Sasaki, Fig.2B as shown above).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (U.S. 2020/0365509 A1, hereinafter refer to Sasaki) as applied to claim 17 above, and further in view of HSU et al. (U.S. 2017/0222008 A1, hereinafter refer to HSU).
Regarding Claim 18: Sasaki discloses a semiconductor device as applied to claim 17 above. Sasaki is silent upon explicitly disclosing wherein a connecting via silicide film between the buried conductive pattern and the contact connecting via.
For support see HSU, which teaches wherein a connecting via silicide film (80) between the conductive pattern (110) and the contact connecting via (75) (see HSU, Fig.9 and ¶ [0065]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki and HSU to enable connecting via silicide film between the buried conductive pattern and the contact connecting via of Sasaki as taught by HSU in order to functions as a passivation layer that can protect the underlying metal layer (e.g., Co) from being oxidized or damaged in air or during subsequent manufacturing operations and it function as an etch stop layer when the contact opening for a via plus is formed, thereby preventing the via from passing to the underlying layer.
Claim(s) 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (U.S. 2020/0365509 A1, hereinafter refer to Sasaki) as applied to claim 17 above, and further in view of CHO et al. (U.S. 2021/0305130 A1, hereinafter refer to CHO).
Regarding Claim 19: Sasaki discloses a semiconductor device as applied to claim 17 above. Sasaki is silent upon explicitly disclosing wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line, and
at the second portion of the buried conductive pattern, the width in the third direction increases of the buried conductive pattern, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern decreases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]), and
at the second portion of the buried conductive pattern, the width in the third direction increases of the buried conductive pattern, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki and CHO to enable the know configuration of buried conductive pattern as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Regarding Claim 20: Sasaki discloses a semiconductor device as applied to claim 17 above. Sasaki teaches wherein at the first portion of the buried conductive pattern, a width in a third direction of the buried conductive pattern is constant (see Sasaki, Fig.2B as shown above); however, Sasaki is silent upon explicitly disclosing wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line.
For support see CHO, which teaches wherein at the second portion of the buried conductive pattern, the width in the third direction of the buried conductive pattern increases, as the buried conductive pattern goes away from the back wiring line (LWL) (see CHO, Figs.9A and 12 as shown above and ¶ [0143]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sasaki and CHO to enable the know configuration of buried conductive pattern as taught by CHO in order to obtain an integrated circuit semiconductor device in which a TSV is reliably formed.
Note: the configuration of the claimed buried conductive pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed buried conductive pattern was significant.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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