DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election filed 24 March 2026. Claims 1-17 are pending in this application, and Claims 18-21 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A, Subspecies A-1, B-1 B-1-3, C-1, D-1, E-1, F-1, Modifications A-2, B-2, C-2, D-2, E-4, F-2, G-2, H-1, I-2, J1 in the reply filed on 24 March 2026 is acknowledged.
Regarding Applicants arguments regarding Subspecies B: Applicant is correct that the restriction mistakenly says Figs. 4B-C correspond to Subspecies B-2. This should say Figs. 4A-B. However, this does not affect the validity of the restriction. Applicant’s specification says (in paragraph [0138]):
“FIGS. 4 A and 4B illustrate an example in which the insulating layer 107a and the insulating layer 131 illustrated in FIGS. 2B and 2C are changed to an insulating layer 130 and the insulating layer 133, the insulating layer 135, and the insulating layer 137 illustrated in FIGS. 2B and 2C are changed to an insulating layer 134.”
This is the arrangement described in Subspecies B-2 as “where the conductive layers (115a, b) are not covered by insulating layers (107a,b) and the conductive layer (115a) covered directly by insulating layer (131) and the first and second conductive layers are separated by a portion of the insulating layer (134).”
Therefore, the restriction is maintained. However, Examiner notes that applicant’s claims are currently generic to both Subspecies B-1 and B-2, and have the potential for rejoinder should allowed claims be generic to both Subspecies.
Regarding Applicants arguments regarding Subspecies C: Applicant is correct that the properties described are also the openings (121a). Examiner was referring to the top surface of the conductive layer (111a) as shown in Fig. 3A3, 6A3, 7A3, which is in the opening (121a) ([0102] The bottom of the opening portion 121a includes a top surface of the conductive layer 111a.) The shape of the top surface of the conductive layer (111a) appears to conform to the shape of the opening (121a) in the images. Furthermore, Applicant clearly understood the feature to which examiner was referring.
Therefore, the restriction is maintained. However, Examiner notes that applicant’s claims are currently generic to both Subspecies C1-3, and have the potential for rejoinder should allowed claims be generic to both Subspecies.
Regarding Applicants arguments regarding Subspecies D: Examiner concedes that the images relating to Figs. 16A, 19A-30A are not assigned to the correct subspecies. However, the restriction is based on the conductive layer 115 which has clearly different shapes as shown in the B Figs. The restriction clearly articulates the mutually exclusive characteristic is the shape of the conductive layer 115. This is the basis for the restriction, and Applicant has not articulated why the different shapes of the conductive layer 115 are not mutually exclusive. The listing of the Figs. is merely meant to be a tool to aid the Applicant in better understanding what the restriction described is referring to. Any mistake in labelling Figs. does not invalidate the underlying mutually exclusive characteristics described in each of the Subspecies.
Therefore, the restriction is maintained. However, Examiner notes that applicant’s claims are currently generic to both Subspecies D1-6, and have the potential for rejoinder should allowed claims be generic to both Subspecies.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 12-13, 17 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Atanasov et. al (US 2022/0189913 A1)
Regarding Claim 1, Atanasov discloses (as shown in Fig. 1) A semiconductor device comprising:
a capacitor ([0016 capacitors 106); a first transistor ([0016] transistors 104); and a first insulating layer ([0016] interlayer dielectric 116),
wherein the capacitor (106) comprises a first conductive layer ([0019] capacitor plate 110), a second conductive layer ([0019] capacitor plate 108), and a second insulating layer ([0019] high-k dielectric 112),
wherein the second insulating layer (112) comprises a region in contact with a side surface of the first conductive layer (110), (See Fig. 1, showing the high-k dielectric 112 on the sidewalls of the capacitor plate 110)
wherein the second conductive layer (108) covers at least part of the side surface of the first conductive layer (110) (See Fig. 1, showing the capacitor plate 108 along sidewalls of the capacitor plate 110) with the second insulating layer (112) therebetween, ([0019] The capacitors 106 of the IC structures 100 of FIGS. 1-3 may include a capacitor plate 108 spaced apart from a capacitor plate 110 by a high-k dielectric 112)
wherein the first transistor (104) comprises a third conductive layer (See An. Fig. 1, CL3), a fourth conductive layer ([0017] first memory control line 126), a fifth conductive layer ([0017] gate electrode 124), a first semiconductor layer ([0017] channel material 120), and a third insulating layer ([0017] gate dielectric 122),
wherein the third conductive layer (An. Fig. 1, CL3) comprises a region in contact with a top surface of the first conductive layer (110), (see An. Fig. 1)
wherein the first insulating layer (116) is over the third conductive layer (An. Fig. 1, CL3), (See An. Fig. 1)
wherein the fourth conductive layer (126) is over the first insulating layer (116), (See Fig. 1)
wherein the first insulating layer (116) and the fourth conductive layer (126) comprise a first opening portion reaching the third conductive layer (An. Fig. 1, CL3), (See An. Fig. 1, showing the channel material 120, gate dielectric 122, and gate electrode 124 pass through the first memory control line 126 and interlayer dielectric 116 to reach the top of the third conductive layer CL3)
wherein the first semiconductor layer (120) comprises a region in contact with the third conductive layer (An. Fig. 1, CL3), ([0019] The capacitor plate 110 of a capacitor 106 in a memory cell 102 may be in contact with the channel material 120 of the transistor 104 of the memory cell 102, as shown.) a region in contact with the fourth conductive layer (126) (See Fig. 1, showing the first memory control line 126 in contact with the channel material 120), and a region positioned inside the first opening portion, (See An. Fig. 1, showing the channel material 120 pass through the first memory control line 126 and interlayer dielectric 116 to reach the top of the third conductive layer CL3)
wherein the third insulating layer (122) is over the first semiconductor layer (120) (See Fig. 1, showing the gate dielectric 122 on the channel material 120) and comprises a region positioned inside the first opening portion, (See An. Fig. 1, showing the gate dielectric 122 pass through the first memory control line 126 and interlayer dielectric 116 to reach the top of the third conductive layer CL3)
and wherein the fifth conductive layer (124) comprises a region facing the first semiconductor layer (120) with the third insulating layer (122) therebetween ([0017] For example, FIG. 1 illustrates an embodiment in which a gate dielectric 122 is disposed around a central gate electrode 124, and a channel material 120 is disposed around the gate dielectric 122), inside the first opening portion. (See An. Fig. 1, showing the gate electrode 124 pass through the first memory control line 126 and interlayer dielectric 116 to reach the top of the third conductive layer CL3)
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Regarding Claim 12, Atanasov further discloses (as shown in Fig. 1) wherein the first semiconductor layer (120) comprises a metal oxide. ([0020] he channel material 120 may include a semiconductor material (e.g., an oxide semiconductor material).)
Regarding Claim 13, Atanasov further discloses (as shown in Fig. 1) wherein the metal oxide comprises one or more selected from indium, zinc, and an element M, and wherein the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, ([0020] In some embodiments, the channel material 120 may include indium, gallium, zinc, and oxygen (e.g., in the form of indium gallium zinc oxide (IGZO)). In some embodiments, the channel material 120 may … indium, tin, and oxygen (e.g., in the form of indium tin oxide) …)
Regarding Claim 17, Atanasov further discloses (as shown in Fig. 1, 18) the semiconductor device according to claim 1 and a camera ([0076] The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device.)
Alternatively, Claim(s) 1, 12-13, 17 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Yamazaki et. al (US 2025/0015194 A1)
Regarding Claim 1, Yamazaki disclose (as shown in Fig. 22A-C) A semiconductor device ([0711] A structure of a memory device including a transistor and a capacitor is described with reference to FIGS. 22A to 22C) comprising:
a capacitor ([0713] The memory cell 150 includes the capacitor 100); a first transistor ([0723] and the transistor 202 over the capacitor 100); and a first insulating layer ([0712] the insulating layer 280a),
wherein the capacitor (100) comprises a first conductive layer ([0714] and the conductive layer 220a over the insulating layer 130), a second conductive layer ([0714] The capacitor 100 includes a conductive layer 115), and a second insulating layer ([0714] an insulating layer 130 over the conductive layer 115),
wherein the second insulating layer (130) comprises a region in contact with a side surface of the first conductive layer (220a), (See Fig. 22B, showing the insulating layer 130 contacting the inner sidewalls of the conductive layer 220a)
wherein the second conductive layer (115) covers at least part of the side surface of the first conductive layer (220a) with the second insulating layer (130) therebetween, (See Fig. 22B, showing the conductive layer 220a is in the middle between the two sidewalls of the conductive layer 115 with the insulating layer 130 in between)
wherein the first transistor (202) comprises a third conductive layer ([0720] The transistor 202 includes … the conductive layer 220b), a fourth conductive layer ([0720] the conductive layer 240), a fifth conductive layer ([0720] the conductive layer 260), a first semiconductor layer ([0720] the oxide semiconductor layer 230), and a third insulating layer ([0720] the insulating layer 250),
wherein the third conductive layer (220b) comprises a region in contact with a top surface of the first conductive layer (220a), ([0720] the conductive layer 220b over the conductive layer 220a) (See Fig. 22B)
wherein the first insulating layer (280a) is over the third conductive layer (220b), (See Fig. 22B, showing the insulating layer 280a covers the conductive layer 220b)
wherein the fourth conductive layer (240) is over the first insulating layer (280a), (See Fig. 22B, showing the conductive layer 240 is over the insulating layer 280a)
wherein the first insulating layer (280a) and the fourth conductive (240) layer comprise a first opening portion reaching the third conductive layer (220b), (See Fig. 22B, showing an opening in in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a which reaches the conductive layer 220b)
wherein the first semiconductor layer (230) comprises a region in contact with the third conductive layer (220b), a region in contact with the fourth conductive layer (240), and a region positioned inside the first opening portion, (See Fig. 22B, showing the oxide semiconductor 230 extending in the opening from the top of the conducive layer 220b to the top of the conductive layer 240)
wherein the third insulating layer (250) is over the first semiconductor layer (230) and comprises a region positioned inside the first opening portion, (See Fig. 22B, showing the insulating layer 250 over the oxide semiconductor 230 in the opening)
and wherein the fifth conductive layer (260) comprises a region facing the first semiconductor layer (230) with the third insulating layer (250) therebetween, inside the first opening portion. (See Fig. 22B, showing the conductive layer 260 in the opening, separated from the oxide semiconductor 230 by the insulating layer 250)
Regarding Claim 12, Yamazaki further discloses (as shown in Figs. 22A-C) wherein the first semiconductor layer (230) comprises a metal oxide. ([0191] The transistor 200 includes a metal oxide functioning as a semiconductor (also referred to as an oxide semiconductor) in the oxide semiconductor layer 230 including a channel formation region)
Regarding Claim 13, Yamazaki further discloses (as shown in Figs. 22A-C) wherein the metal oxide (230) comprises one or more selected from indium, zinc, and an element M, and wherein the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. ([0599] The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), particularly preferably contains indium as its main component. Here, the metal oxide contains indium as its main component, and can further contain an element M. The metal oxide preferably contains two or three selected from indium, the element M, and zinc, and particularly preferably contains indium and zinc as its main components. Here, the metal oxide contains indium and zinc as its main components, and can further contain the element M. The element M is a metal element or metalloid element that has a high bonding energy with oxygen, such as a metal element or metalloid element whose bonding energy with oxygen is higher than that of In. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.)
Regarding Claim 17, Yamazaki further discloses (as shown in Figs. 22A-C) ([1076] A display device including the semiconductor device of one embodiment of the present invention can be used for a display portion of any of a variety of electronic devices…[1077] Examples of the electronic devices include a digital camera, a digital video camera)
Alternatively, Claim 1 can be rejected under an alternate embodiment of Yamazaki (as shown in Figs. 3, 32, 40C-D)
Claim(s) 1-3, 12-17 is/are rejected under 35 U.S.C. 102a(2) as being anticipated by Yamazaki et. al (US 2025/0015194 A1)
Regarding Claim 1, Yamazaki disclose (as shown in Fig. 3, 32) A semiconductor device ([0793] The memory device illustrated in FIG. 32 includes the insulating layer 140 over a substrate (not illustrated), the memory cell 150) comprising:
a capacitor ([0794] the capacitor 100A ); a first transistor ([0794] the transistor 203E1 over the capacitor 100A); and a first insulating layer ([0793] the insulating layer 280a),
wherein the capacitor (100A) comprises a first conductive layer ([0795] the conductive layer 115), a second conductive layer ([0795] the conductive layers 165a and 165b), and a second insulating layer ([0758] the insulating layer 130),
wherein the second insulating layer (130) comprises a region in contact with a side surface of the first conductive layer (115), (See Fig. 32, showing the insulating layer 130 contacting the inner sidewalls of the conductive layer 115)
wherein the second conductive layer (165) covers at least part of the side surface of the first conductive layer (115) with the second insulating layer (130) therebetween, (See Fig. 32, showing the conductive layer 165 is in the middle between the two sidewalls of the conductive layer 115 with the insulating layer 130 in between)
wherein the first transistor (203E1) comprises a third conductive layer ([0290] FIG. 3 illustrates an example where the conductive layer 220 has a three-layer structure of a conductive layer 220al, a conductive layer 220a2 over the conductive layer 220al, and the conductive layer 220b over the conductive layer 220a2.), a fourth conductive layer ([0291] FIG. 3 illustrates the example where the conductive layer 240 has a two-layer structure of the conductive layer 240a and the conductive layer 240b over the conductive layer 240a.), a fifth conductive layer ([0382] the conductive layer 260), a first semiconductor layer ([0214] As described above, the oxide semiconductor layer 230 includes the channel formation region. ), and a third insulating layer ([0166] the insulating layer 250),
wherein the third conductive layer (220) comprises a region in contact with a top surface of the first conductive layer (115), ([0796] The conductive layer 115 is electrically connected to the conductive layer 220a1 through a conductive layer 166a and a conductive layer 166b that are embedded in the insulating layer 180b.)
wherein the first insulating layer (280a) is over the third conductive layer (220), (See Fig. 32, showing the insulating layer 280a covers the conductive layer 220)
wherein the fourth conductive layer (240) is over the first insulating layer (280a), (See Fig. 32, showing the conductive layer 240 is over the insulating layer 280a)
wherein the first insulating layer (280a) and the fourth conductive (240) layer comprise a first opening portion reaching the third conductive layer (220b), (See Fig. 32, showing an opening in in the conductive layer 240, the insulating layer 280b, the conductive layer 255, and the insulating layer 280a which reaches the conductive layer 220b)
wherein the first semiconductor layer (230) comprises a region in contact with the third conductive layer (220), a region in contact with the fourth conductive layer (240), and a region positioned inside the first opening portion, (See Fig. 32, showing the oxide semiconductor 230 extending in the opening from the top of the conducive layer 220 to the top of the conductive layer 240)
wherein the third insulating layer (250) is over the first semiconductor layer (230) and comprises a region positioned inside the first opening portion, (See Fig. 32, showing the insulating layer 250 over the oxide semiconductor 230 in the opening)
and wherein the fifth conductive layer (260) comprises a region facing the first semiconductor layer (230) with the third insulating layer (250) therebetween, inside the first opening portion. (See Fig. 32, showing the conductive layer 260 in the opening, separated from the oxide semiconductor 230 by the insulating layer 250)
Regarding Claim 2, Yamazaki further discloses (as shown in Figs. 32, 40C-D) a second transistor ([0792] the transistor 200e),
wherein the second transistor (200e) is under the capacitor (100A),
and wherein the first conductive layer (115) is electrically connected to a gate electrode of the second transistor (200e). ([0796] Accordingly, the source or the drain of the transistor 203E1, one electrode of the capacitor 100A, and the gate of the transistor 200e are electrically connected to each other.) (See Fig. 32)
Regarding Claim 3, Yamazaki further discloses (as shown in Figs. 32, 40C-D) a second transistor ([0792] the transistor 200e) and a fourth insulating layer ([0793] the insulating layer 161a),
wherein the second transistor (200e) comprises a sixth conductive layer ([0746] A conductive layer 120a and a conductive layer 120b included in the transistor 200a can have structures similar to those usable for the conductive layer 220a and the conductive layer 220b, respectively.), a seventh conductive layer ([0746] A conductive layer 145 can have a structure similar to that usable for the conductive layer 240), an eighth conductive layer ([0784] A conductive layer 164 can have a structure similar to that usable for the conductive layer 260.), a second semiconductor layer ([0795] The description of the transistor 200 in Embodiment 2 (FIGS. 2A1 to 2E and FIG. 3) can be referred to for the transistor 200e; thus, the detailed description thereof is omitted) ([0720] the oxide semiconductor layer 230) (See Fig. 32, showing 130 in the lower transistor 200e is the equivalent to the oxide semiconductor 230 in the upper transistor 200E1), and a fifth insulating layer ([0746] the insulating layer 151),
Prior art clarification Note: the number 130 is used to represent two different things, an insulating layer and an oxide semiconducting layer. Based on the disclosure that the lower transistor is the same as the upper transistor ([0795] The description of the transistor 200 in Embodiment 2 (FIGS. 2A1 to 2E and FIG. 3) can be referred to for the transistor 200e; thus, the detailed description thereof is omitted) it is clear that the 130 in transistor 200e is equivalent to the oxide semiconductor 230 in transistor 200E1.
wherein the fourth insulating layer (161a) is over the sixth conductive layer (120), (See Fig. 32, showing the insulating layer 161a is over the conductive layer 120)
wherein the seventh conductive layer (145) is over the fourth insulating layer (161a), (See Fig. 32, showing the conductive layer 145 is over the insulating layers 161)
wherein the fourth insulating layer (161a) and the seventh conductive layer (145) comprise a second opening portion reaching the sixth conductive layer (120), See Fig. 32, showing an opening in in the conductive layer 145, the insulating layers 161, the conductive layer 155, and the insulating layer 161a which reaches the conductive layer 120b)
wherein the second semiconductor layer (130) comprises a region in contact with the sixth conductive layer (120), a region in contact with the seventh conductive layer (145), and a region positioned inside the second opening portion, (See Fig. 32, showing the oxide semiconductor 130 extending in the opening from the top of the conducive layer 120 to the top of the conductive layer 145)
wherein the fifth insulating layer (151) is over the second semiconductor layer (230) and comprises a region positioned inside the second opening portion, (See Fig. 32, showing the insulating layer 151 over the oxide semiconductor 130 in the opening)
wherein the eighth conductive layer (164) comprises a region facing the second semiconductor layer (130) with the fifth insulating layer (151) therebetween, inside the second opening portion, (See Fig. 32, showing the conductive layer 164 in the opening, separated from the oxide semiconductor 130 by the insulating layer 151)
and wherein a top surface of the eighth conductive layer (164) comprises a region in contact with the first conductive layer (115). ([0796] The conductive layer 115 is electrically connected to the conductive layer 164 through a conductive layer 110a and a conductive layer 110b that are embedded in the insulating layer 185.)
Claim Interpretation note: Under BRI the claim limitation “wherein a top surface of the eighth conductive layer comprises a region in contact with the first conductive layer” can be interpreted as either physical or electrical contact.
Regarding Claim 12, Yamazaki further discloses (as shown in Figs. 32, 40C-D) wherein the first semiconductor layer (230) comprises a metal oxide. ([0191] The transistor 200 includes a metal oxide functioning as a semiconductor (also referred to as an oxide semiconductor) in the oxide semiconductor layer 230 including a channel formation region) ([0795] The description of the transistor 200 in Embodiment 2 (FIGS. 2A1 to 2E and FIG. 3) can be referred to for the transistor 200e; thus, the detailed description thereof is omitted)
Regarding Claim 13, Yamazaki further discloses (as shown in Figs. 32, 40C-D) wherein the metal oxide (230) comprises one or more selected from indium, zinc, and an element M, and wherein the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. ([0599] The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), particularly preferably contains indium as its main component. Here, the metal oxide contains indium as its main component, and can further contain an element M. The metal oxide preferably contains two or three selected from indium, the element M, and zinc, and particularly preferably contains indium and zinc as its main components. Here, the metal oxide contains indium and zinc as its main components, and can further contain the element M. The element M is a metal element or metalloid element that has a high bonding energy with oxygen, such as a metal element or metalloid element whose bonding energy with oxygen is higher than that of In. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.)
Regarding Claim 14, Yamazaki further discloses (as shown in Figs. 32, 40C-D) wherein the first semiconductor layer (230) and the second semiconductor layer (130) comprise a metal oxide. ([0191] The transistor 200 includes a metal oxide functioning as a semiconductor (also referred to as an oxide semiconductor) in the oxide semiconductor layer 230 including a channel formation region) ([0795] The description of the transistor 200 in Embodiment 2 (FIGS. 2A1 to 2E and FIG. 3) can be referred to for the transistor 200e; thus, the detailed description thereof is omitted)
Regarding Claim 15, Yamazaki further discloses (as shown in Figs. 32, 40C-D) wherein the metal oxide (230) comprises one or more selected from indium, zinc, and an element M, and wherein the element M is one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. ([0599] The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), particularly preferably contains indium as its main component. Here, the metal oxide contains indium as its main component, and can further contain an element M. The metal oxide preferably contains two or three selected from indium, the element M, and zinc, and particularly preferably contains indium and zinc as its main components. Here, the metal oxide contains indium and zinc as its main components, and can further contain the element M. The element M is a metal element or metalloid element that has a high bonding energy with oxygen, such as a metal element or metalloid element whose bonding energy with oxygen is higher than that of In. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.)
Regarding Claim 17, Yamazaki further discloses (as shown in Figs. 22A-C) ([1076] A display device including the semiconductor device of one embodiment of the present invention can be used for a display portion of any of a variety of electronic devices…[1077] Examples of the electronic devices include a digital camera, a digital video camera)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki as applied to claim 3 above.
Regarding Claim 16, Yamazaki fails to disclose wherein a capacitance of the capacitor (100A) is more than or equal to double a capacitance of a capacitor formed by the seventh conductive layer (145), the fifth insulating layer (151), and the eighth conductive layer (164).
Yamazaki teaches that the capacitance generated between the gate wiring and the source/drain electrode can slow the transistor operation, thus it is desirable to reduce the parasitic capacitance between the gate and the source/drain.
([0150] Large capacitance generated between a gate wiring and the source electrode or the drain electrode might slow the transistor operation and degrade the frequency characteristics of a circuit including the transistor.
[0151] In view of the above, in the transistor of one embodiment of the present invention, parasitic capacitance generated between the third conductive layer and the fourth conductive layer is preferably reduced. In this case, high-speed operation of the transistor can be achieved. A semiconductor device with favorable electrical characteristics can be provided.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to reduce the capacitance between the gate and source/drain in order to achieve a faster switching speed. Therefore, it would be obvious to optimize have the capacitance between the capacitor (100A) be more than or equal to double a capacitance of a capacitor formed by the seventh conductive layer (145), the fifth insulating layer (151), and the eighth conductive layer (164) because it would be obvious to reduce the capacitance between the seventh conductive layer (145), the fifth insulating layer (151), and the eighth conductive layer (164) as much as possible in order to increase the switching speed of the transistor.
Allowable Subject Matter
Claims 4-11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 4, Yamazaki further discloses (as shown in Figs. 32, 40C-D) a memory portion, wherein the memory portion comprises memory cells arranged in a matrix, ([0803] The memory cells 150 are arranged in a matrix three-dimensionally, whereby a memory cell array can be formed.)
wherein each of the memory cells comprises the first transistor, the second transistor, and the capacitor, ([0798] The memory cell 953 includes the transistor M2, the transistor M3, and a capacitor CB.)
However, Yamazaki fails to disclose wherein the sixth conductive layer (120) and the seventh conductive layer (145) are shared by the memory cells arranged in a first direction.
Because the Claim includes limitation that are not found in the prior art, Claim 4 contains allowable subject matter.
Regarding Claims 5-8, Claims 5-8 depend from Claim 4 and contain allowable subject matter for the same reasons.
Regarding Claim 9, Yamazaki fails to disclose wherein the second conductive layer (either 220a or 115 depending on which interpretation above is used) comprises a region extending in a first direction and a region extending in a second direction that is perpendicular to the first direction, and wherein the second conductive layer (220a or 115) comprises a third opening portion in a region where the region extending in the first direction and the region extending in the second direction intersect with each other.
Atanasov also fails to disclose wherein the second conductive layer (108) comprises a region extending in a first direction and a region extending in a second direction that is perpendicular to the first direction, and wherein the second conductive layer (108) comprises a third opening portion in a region where the region extending in the first direction and the region extending in the second direction intersect with each other.
Because the Claim includes limitation that are not found in the prior art, Claim 9 contains allowable subject matter.
Regarding Claim 10, Claim 10 depends from Claim 9 and contain allowable subject matter for the same reasons.
Regarding Claim 11, Yamazaki further discloses (as shown in Figs. 32, 39, 40C-D) a memory portion ([0848] memory array 920), a first driver circuit ([0855] a column driver 924), and a second driver circuit ([0855] a row driver 923),
wherein the memory portion (920) comprises memory cells ([0794] The memory cell 150) arranged in a matrix, ([0848] the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.)
wherein each of the memory cells (950) comprises the first transistor (203E1), the second transistor (200e), and the capacitor (100A), ([0794] The memory cell 150 includes the transistor 200e over the insulating layer 140, the capacitor 100A over the transistor 200e, and the transistor 203E1 over the capacitor 100A.)
wherein a constant potential is supplied to the second conductive layer (165), ([0864] The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA)
wherein the first driver circuit is configured to write data to the memory cells and read the data, ([0856] The column driver 924 has a function of writing data to the memory cell 950, reading data from the memory cell 950, and retaining the read data, for example.)
and wherein the second driver circuit is configured to supply a signal to the seventh conductive layer and thereby control reading of the data. ([0856] The row driver 923 has a function of selecting the row specified by the row decoder 941.)
wherein the sixth conductive layer (120) is electrically connected to the first driver circuit (824), ([0765] The other of the source and the drain of the transistor M1 is connected to the wiring BIL)
wherein the seventh conductive layer (145) is electrically connected to the second driver circuit (923), ([0765] The gate of the transistor M1 is connected to the wiring WOL)
However, Yamazaki fails to disclose:
wherein the second conductive layer (165) comprises a region extending in a first direction and a region extending in a second direction that is perpendicular to the first direction,
wherein the second conductive layer (165) comprises a third opening portion in a region where the region extending in the first direction and the region extending in the second direction intersect with each other,
Because the Claim includes limitation that are not found in the prior art, Claim 11 contains allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Juengling (US 2019/0067288 A1): Juengling discloses (as shown in Fig. 3) a 2t-1c transistor with the first transistor (TU) vertically stacked on the capacitor (14) which is stacked on a second transistor (TL)
The following prior art are made of record and relevant to the applicant’s claims, but may be eligible for an exception under 35 USC 102(b)(2)(c).
Saito et. al (US 2026/0101500 A1): Saito discloses (as show in Figs. 1A-C) a 1t-1c memory cell with the transistor (200) vertically stacked on the capacitor (100). The transistor (200) includes a semiconductor portion ([0074] an oxide semiconductor 230) extending from an electrode ([0074] the conductor 120) of the capacitor to a conductive layer ([0074] conductor 240) with the semiconducting portion (230) separated from a conductive layer ([0074] conductor 260) by an insulating layer ([0074] insulator 250) in an opening of the insulating layer ([0073] insulator 280)
Miyairi et. al (US 2024/0298435 A1): Miyairi discloses (as show in Figs. 5A-E, 17A) a 1t-1c memory cell with the transistor (200) vertically stacked on the capacitor (100). The transistor (200) includes a semiconductor portion ([0196] an oxide 230) ([0212] At least part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region) extending from an conductor ([0196] conductor 242a), connected to an electrode ([0477] he conductor 120 functions as the upper electrode of the capacitor 100) of the capacitor, to a conductive layer ([0190] conductor 246) with the semiconducting portion (230) separated from a conductive layer ([0196] conductor 260) by an insulating layer ([0196] insulator 250a).
Yamazaki et. al (US 2026/0089921 A1): Yamazaki discloses (as shown in Figs. 2A-2D) a 1t-1c memory cell with the transistor (200) vertically stacked on the capacitor (100). The transistor (200) includes a semiconductor portion ([0086] an oxide semiconductor 230) extending from a capacitor ([0087] the conductor 120), serving as both an electrode of the capacitor and a S/D of the transistor (See [0086-0087]), to a conductive layer ([0087] conductor 240) with the semiconducting portion (230) separated from a conductive layer ([0087] conductor 260), functioning as a gate electrode, by an insulating layer ([0087] insulator 250), functioning as a gate insulator, in an opening of the insulating layer ([0087] insulator 280).
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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