Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1, 3-9, and 11-18 are rejected under 35 U.S.C. 103 as being unpatentable over Galatage (PGPub No. 20240204060).
Regarding claim 1, Galatage teaches an electronic device having one or more non-planar transistors (Fig. 1 points to an IC device 100 comprising a nanoribbon transistor 100.), at least one of the one or more non-planar transistors comprising: one or more gate structures (Id. points to a gate stack 106.); and one or more gate spacers respectively associated with each of the one or more gate structures, at least one gate spacer of the one or more gate spacers having a multi-layer dielectric structure comprising a first dielectric structure comprising a first dielectric material, the first dielectric structure forming an interior wall disposed next to a respective gate structure of the one or more gate structures, a second dielectric structure comprising a second dielectric material, the second dielectric structure forming an exterior wall spaced apart from the interior wall, and a third dielectric structure comprising a third dielectric material, the third dielectric structure extending between and separating the interior wall from the exterior wall, wherein a dielectric constant of the third dielectric material is lower than a dielectric constant of the first dielectric material and lower than a dielectric constant of the second dielectric material ([0026] and [0040] point to alternative embodiments where the gate stack 106 is surrounded by a gate spacer comprising air gaps (third dielectric structure) that separate portions (first dielectric structure; second dielectric structure).).
Regarding claim 3, Galatage teaches wherein: the first dielectric material and the second dielectric material are a same dielectric material ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material).).
Regarding claim 4, Galatage teaches wherein: the third dielectric material comprises an air gap ([0040] points to a gate spacer comprising air gaps (third dielectric material) surrounded by a low-k dielectric material.).
Regarding claim 5, Galatage teaches wherein the one or more gate spacers further comprise: an upper wall of a fourth dielectric material overlying the third dielectric material and extending between the interior wall and the exterior wall; and a lower wall of a fifth dielectric material below the third dielectric material and extending between the interior wall and the exterior wall ([0040] points to a gate spacer (upper wall; lower wall) comprising air gaps surrounded by a low-k dielectric material (fourth dielectric material; fifth dielectric material).).
Regarding claim 6, Galatage teaches wherein: the first dielectric material, the second dielectric material, the fourth dielectric material, and the fifth dielectric material are a same dielectric material ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material; fourth dielectric material; fifth dielectric material).).
Regarding claim 7, Galatage teaches wherein: the third dielectric material extends from an interior surface of the interior wall and an interior surface of the exterior wall ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material; fourth dielectric material; fifth dielectric material).).
Regarding claim 8, Galatage teaches wherein the electronic device comprises at least one of: a music player; a video player; an entertainment unit; a navigation device; a communications device; a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed location terminal; a tablet computer, a computer; a wearable device; a laptop computer; a server; an internet of things (IoT) device; or a device in an automotive vehicle (FIG. 7 and [0101] point to a block diagram of an example computing device 2400 that may include one or more components including one or more nanoribbon stacks and may have any desire form factor such as a handheld or mobile computing device.).
Regarding claim 9, Galatage teaches a non-planar transistor comprising: one or more gate structures (Fig. 1 points to a transistor 110 comprising a gate stack 106 (gate structure).); and one or more gate spacers respectively associated with each of the one or more gate structures, at least one gate spacer of the one or more gate spacers having a multi-layer dielectric structure comprising a first dielectric structure comprising a first dielectric material, the first dielectric structure forming an interior wall disposed next to a respective gate structure of the one or more gate structures, a second dielectric structure comprising a second dielectric material, the second dielectric structure forming an exterior wall spaced apart from the interior wall, and a third dielectric structure comprising a third dielectric material, the third dielectric structure extending between and separating the interior wall from the exterior wall, wherein a dielectric constant of the third dielectric material is lower than a dielectric constant of the first dielectric material and lower than a dielectric constant of the second dielectric material ([0026] and [0040] point to alternative embodiments where the gate stack 106 is surrounded by a gate spacer comprising a low-k dielectric material such as silicon dioxide (first dielectric material; second dielectric material), which may further include air gaps (third dielectric material).).
Regarding claim 11, Galatage teaches wherein: the first dielectric material and the second dielectric material are a same dielectric material ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material).).
Regarding claim 12, Galatage teaches wherein: the third dielectric material comprises an air gap ([0040] points to a gate spacer comprising air gaps (third dielectric material) surrounded by a low-k dielectric material.).
Regarding claim 13, Galatage teaches wherein the one or more gate spacers further comprise: an upper wall of a fourth dielectric material overlying the third dielectric material and extending between the interior wall and the exterior wall; and a lower wall of a fifth dielectric material below the third dielectric material and extending between the interior wall and the exterior wall ([0040] points to a gate spacer (upper wall; lower wall) comprising air gaps surrounded by a low-k dielectric material (fourth dielectric material; fifth dielectric material).).
Regarding claim 14, Galatage teaches wherein: the first dielectric material, the second dielectric material, the fourth dielectric material, and the fifth dielectric material are a same dielectric material ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material; fourth dielectric material; fifth dielectric material).).
Regarding claim 15, Galatage teaches wherein: the third dielectric material extends from an interior surface of the interior wall and an interior surface of the exterior wall ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material; fourth dielectric material; fifth dielectric material).).
Regarding claim 16, Galatage teaches a method of forming a fin field effect transistor (FinFET), comprising: forming a channel structure having a semiconductor channel between a source and a drain of the FinFET (Fig. 1 points to a transistor 110 comprising a nanoribbon 104 (channel structure) and S/D regions 114-1 and 114-2 (a source and a drain). [0035] further points to the transistor 110 being formed via “layer transfer”, which allows for the forming of non-planar transistors such as FinFETs or nanoribbon transistors. In light of this, it is considered obvious that one of ordinary skill in the art could form the transistor 110 according to a FinFET structure rather than a nanoribbon structure.); forming a gate structure overlying the semiconductor channel (Fig. 1 points to a gate stack 106.); and forming at least one gate spacer associated with the gate structure, wherein the forming the at least one gate spacer comprises forming a first dielectric structure comprising a first dielectric material, the first dielectric structure forming an interior wall next to the gate structure, forming a second dielectric structure comprising a second dielectric material, the second dielectric structure forming an exterior wall spaced apart from the interior wall, and forming a third dielectric structure comprising a third dielectric material, the third dielectric structure extending between and separating the interior wall from the exterior wall disposed between the interior wall and the exterior wall, wherein a dielectric constant of the third dielectric material is lower than a dielectric constant of the first dielectric material and lower than a dielectric constant of the second dielectric material ([0026] and [0040] point to alternative embodiments where the gate stack 106 is surrounded by a gate spacer comprising a low-k dielectric material such as silicon dioxide (first dielectric material; second dielectric material), which may further include air gaps (third dielectric material).).
Regarding claim 17, Galatage teaches a method of forming a gate-all-around (GAA) transistor, comprising: forming a plurality of channel structures between a source and a drain of the GAA transistor (Fig. 1 points to a nanoribbon 104 (channel structure) and S/D regions 114-1 and 114-2 (a source and a drain). [0024] further points to alternative embodiments where multiple nanoribbons 104 (plurality of channel structures) are arranged.); forming a gate structure associated with the plurality of channel structures (Fig. 1 points to a gate stack 106.); and forming at least one gate spacer associated with the gate structure, wherein the forming the at least one gate spacer comprises forming a first dielectric structure comprising a first dielectric material, the first dielectric structure forming an interior wall next to the gate structure, forming a second dielectric structure comprising a second dielectric material, the second dielectric structure forming an exterior wall spaced apart from the interior wall, and forming and a third dielectric structure comprising a third dielectric material, the third dielectric structure extending between and separating the interior wall from the exterior wall, wherein a dielectric constant of the third dielectric material is lower than a dielectric constant of the first dielectric material and lower than a dielectric constant of the second dielectric material ([0026] and [0040] point to alternative embodiments where the gate stack 106 is surrounded by a gate spacer comprising a low-k dielectric material such as silicon dioxide (first dielectric material; second dielectric material), which may further include air gaps (third dielectric material).).
Regarding claim 18, Galatage teaches wherein: the first dielectric material and the second dielectric material are a same dielectric material ([0040] points to a gate spacer comprising air gaps surrounded by a low-k dielectric material (first dielectric material; second dielectric material).).
Claim(s) 2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Galatage in further view of Chanemougame (PGPub No. 20180204927).
Regarding claim 2, Chanemougame teaches wherein: the interior wall is disposed adjacent a gate dielectric layer of the respective gate structure (Fig. 8A points to an integrated circuit structure comprising a gate sidewall spacer 240 (interior wall) and a gate dielectric layer 261). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Galatage and Chanemougame, such that a gate dielectric layer is formed between the interior wall and the gate structure in order to achieve desired work functions given the conductivity type of the FET.
Regarding claim 10, Chanemougame teaches wherein: the interior wall is disposed adjacent a gate dielectric layer of the respective gate structure (Fig. 8A points to an integrated circuit structure comprising a gate sidewall spacer 240 (interior wall) and a gate dielectric layer 261). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Galatage and Chanemougame, such that a gate dielectric layer is formed between the interior wall and the gate structure in order to achieve desired work functions given the conductivity type of the FET.
Response to Arguments
Applicant's arguments filed 03/16/2026 have been fully considered but they are not persuasive. Specifically, Applicant argues that the newly amended claims 1, 9, 16, and 17 overcome the previous rejections under 35 U.S.C. §103 made in view of references Galtange and Chanemougame. Examiner argues that not only do the amendments fail to overcome the previous rejection, but also that Applicant incorrectly applies the teachings of Chanemougame in their argument(s).
Regarding the first point, Examiner argues that the amendments made to said claims do nothing to actually change the structure that was previously rejected: since each of the newly added first-third “dielectric structure(s)” are solely comprised of the corresponding first-third dielectric material(s), the amendments simply act as a redefining of terms rather than a disclosure of new subject matter. As discussed in the previous rejections, [0026] and [0040] of Galatage point to a gate spacer/multi-layer dielectric structure comprising a low-k dielectric material including air gaps, said air gaps requiring the formation and separation of at least two portions of the low-k dielectric material in order to exist. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejections.
Regarding the second point, Examiner argues that Applicant’s use and analysis of Chanemougame is inaccurate. Applicant states that Chanemougame was relied on as the primary reference used for the spacer structure in the rejections made towards claims 1, 9, 16, and 17 (see pg. 2 of Remarks, second paragraph), but in fact only the rejections of claims 2 and 10 used this reference; the rejections of claims 1, 9, 16, and 17 relied solely on the teachings of reference Galtage. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the previous rejections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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