Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on January 20, 2026, regarding the application filed September 25, 2023.
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-10, in the reply filed on January 20, 2026 is acknowledged. Claims 11-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-20 are pending, with claims 11-20 currently withdrawn from consideration.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on Chinese Patent Application No. 202211223425X filed on October 8, 2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings filed with the application on September 25, 2023 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sheridan et al., US 2010/0148186 A1 (hereinafter Sheridan) in view of Chang et al., US 2021/0376090 A1 (hereinafter Chang).
Regarding claim 1, Sheridan discloses: A vertically conductive semiconductor structure, comprising: a heavily doped layer (Sheridan, FIG. 2, substrate, N-type, doping concentration greater than 1E19/cm3, [0036; 0052-0055]; Applicant’s specification defines heavily doped as greater than 1E19/cm3, [0102]), a first semiconductor layer (Sheridan, FIG. 2, N-type drift layer, [0036; 0054]), and a second semiconductor layer (Sheridan, FIG. 2, channel layer, [0036; 0054]) that are arranged from bottom to top (Sheridan, see FIG. 2), wherein conductivity types of the heavily doped layer and the first semiconductor layer are same (Sheridan, FIG. 2, N-type substrate [the heavily doped layer] and N-type drift layer [the first semiconductor layer] have same conductivity type, [0036; 0054]), (Sheridan, “Group III nitride compounds (e.g., gallium nitride GaN),” [0052]); and an ion implanted region in the second semiconductor layer (Sheridan, FIG. 2, P-type gate region, [0037-0041]), wherein conductivity types of the ion implanted region and the second semiconductor layer are opposite (Sheridan, FIG. 2, P-type gate region [the ion implanted region] and N-type channel layer [the second semiconductor layer] have opposite conductivity type, [0041; 0054]), the ion implanted region comprises a first end (Sheridan, FIG. 2, upper surface of raised portion of P-type gate region, shown co-planar with top surface of channel) and a second end that are opposite to each other in a thickness direction (Sheridan, FIG. 2, lower boundary of channel), wherein the first end is flush with a surface of the second semiconductor layer far from the first semiconductor layer (Sheridan, FIG. 2 shows upper surface of raised portion of channel [the first end] flush with upper surface of channel layer [the second semiconductor layer] far from N-type drift layer [the first semiconductor layer]), and the second end connects the first semiconductor layer (Sheridan, see FIG. 2, “a conducting channel is formed between drain and source,” i.e., electrically connected, [0035]), and a width of the ion implanted region from bottom to top varies (Sheridan, FIG. 2 shows width of P-type gate region [the ion implanted region], indicated by Wch, varies from bottom to top, “the sidewalls can be sloped sufficiently to insure that the channel width (Wch) at the source end of the channel is smaller than Wch at the drain end of the channel,” [0037]).
Sheridan is silent regarding conductivity types of the first semiconductor layer and the second semiconductor layer are opposite.
However, Chang, in the same field of endeavor, teaches that the conductivity type of each layer may be selected according to the desired device functionality, e.g. a p-type layer may be arranged on an n-type layer, or vice versa (Chang, [0015-0017]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan with the teachings of Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation because a person having ordinary skill would have pursued the finite number of known potential options with a reasonable expectation of success. The motivation for doing so would be, as recognized by Chang, to control mobility of charge carriers, thereby improving performance of the device.
Regarding claim 2, Sheridan in view of Chang teaches: The structure according to claim 1, wherein from bottom to top, the width of the ion implanted region periodically varies, gradually increases (Sheridan, FIG. 2 shows width of P-type gate region [the ion implanted region], indicated by Wch, gradually increases from bottom to top, “the sidewalls can be sloped sufficiently to insure that the channel width (Wch) at the source end of the channel [the top end] is smaller than Wch at the drain end of the channel [the bottom end],” [0037]), gradually decreases, first increases and then decreases, or first decreases and then increases.
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Sheridan include one or more of Applicant’s claimed alternative elements, for example: from bottom to top, the width of the ion implanted region gradually increases.
Regarding claim 4, Sheridan in view of Chang teaches: The structure according to claim 1, wherein at least one of: from bottom to top, a concentration of doped ions in the ion implanted region is unchanged (Sheridan, FIG. 1A, “uniformly doped sidewalls,” [0031], i.e., a concentration of doped ions in the ion implanted region is unchanged), from bottom to top, a concentration of doped ions in the ion implanted region periodically varies, from bottom to top, a concentration of doped ions in the ion implanted region gradually increases, or from bottom to top, a concentration of doped ions in the ion implanted region gradually decreases (Sheridan, FIG. 3, “the p-type implant concentration [the concentration of doped ions in the ion implanted region] and hence the implant damage can be reduced at the gate-source junction,” [0043], i.e., from bottom to top, a concentration of doped ions in the ion implanted region gradually decreases).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Sheridan include one or more of Applicant’s claimed alternative elements, as discussed above.
Regarding claim 5, Sheridan in view of Chang teaches: The structure according to claim 1, further comprising: a source electrode connecting the first end of the ion implanted region (Sheridan, FIG. 2, source terminal shown connected to upper surface of raised portion of P-type gate region [the first end of the ion implanted region]); a gate electrode at both sides of the source electrode (Sheridan, FIG. 2, gate terminals shown at both sides of source terminal), wherein the gate electrode connects the second semiconductor layer at both sides of the ion implanted region (Sheridan, FIG. 2 shows gate terminal connected to channel layer [the second semiconductor layer] at both sides of P-type gate region [the ion implanted region]); and a drain electrode connecting a surface of the heavily doped layer far from the first semiconductor layer (Sheridan, FIG. 2 shows drain terminal connected to lower surface of substrate [the heavily doped layer], i.e., far from the N-type drift layer [the first semiconductor layer]) .
Regarding claim 6, Sheridan in view of Chang teaches: The structure according to claim 1, further comprising: a first electrode connecting the second semiconductor layer adjacent to the ion implanted region and the ion implanted region (Sheridan, FIG. 2 shows gate terminal [the first electrode] connected to channel layer [the second semiconductor layer] adjacent to P-type gate region [the ion implanted region]); and a second electrode connecting the heavily doped layer (Sheridan, FIG. 2 shows drain terminal [the second electrode] connected to lower surface of substrate [the heavily doped layer]).
Regarding claim 7, Sheridan in view of Chang teaches: The structure according to claim 1, wherein the ion implanted region (Sheridan, FIG. 2, P-type gate region) further comprises a heavily doped region far from the first semiconductor layer (Sheridan, FIG. 2 shows ion implanted P-type gate region [the heavily doped region] on opposite side of structure from N-type drift layer [the first semiconductor layer], i.e., far from the first semiconductor layer; implanted P-type gate region has doping concentration greater than 5E18/cm3, i.e., heavily doped, [0054]), wherein conductivity types of the heavily doped region and the second semiconductor layer are opposite (Sheridan, ion implanted P-type gate region [the heavily doped region] has conductivity of P-type, channel layer [the second semiconductor layer] has conductivity of N-type, i.e., opposite, [0036]).
Regarding claim 8, Sheridan in view of Chang teaches: The structure according to claim 1, further comprising a buffer layer between the heavily doped layer and the first semiconductor layer (Sheridan, FIG. 2 shows buffer layer between substrate [the heavily doped layer] and N-type drift layer [the first semiconductor layer], [0036]).
Regarding claim 10, Sheridan teaches nearly every element of claim 10 but is silent regarding: wherein the second semiconductor layer comprises a first doped layer and a second doped layer that are stacked, wherein the first doped layer is close to the first semiconductor layer, and the second doped layer is far from the first semiconductor layer, and a conductive-ion doping concentration of the first doped layer is lower than a conductive-ion doping concentration of the second doped layer.
However, Chang, in the same field of endeavor, discloses a vertical group III-V device structure and teaches that the active layer 106, analogous to the channel layer of Sheridan [the second semiconductor layer], comprises a first doped layer (Chang, FIG. 3B, second doped region 108, [0034]) and a second doped layer that are stacked (Chang, FIG. 3B, contact region 303, [0034]), wherein the first doped layer is close to the first semiconductor layer (Chang, FIG. 3B shows second doped region 108 [the first doped layer] close to the bottom of the structure, [0034]), and the second doped layer is far from the first semiconductor layer (Chang, FIG. 3B shows contact region 303 [the second doped layer] far from the bottom of the structure, [0034]), and a conductive-ion doping concentration of the first doped layer is lower than a conductive-ion doping concentration of the second doped layer (Chang, “contact region 303 [the second doped layer] may comprise the second doping type (e.g., n-type) with a higher doping concentration than the first doped region 105 and/or the second doped region 108 [the first doped layer], i.e., the conductive-ion doping concentration of the first doped layer is lower than a conductive-ion doping concentration of the second doped layer, [0034]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan with the teachings of Chang, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Chang, to control the formation of the conductive channel between the upper contacts and the bottom electrode, thereby providing for improved device functionality.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Sheridan in view of Chang and further in view of Derluyn et al., US 2008/0006845 A1 (hereinafter Derluyn).
Regarding claim 3, Sheridan in view of Chang teaches nearly every element of claim 3 but is silent regarding: a passivated layer on the surface of the second semiconductor layer far from the first semiconductor layer, wherein a material of the passivated layer is AlGaN, and a content of Al in the AlGaN increases from bottom to top in the thickness direction of the passivated layer.
However, Derluyn, in the same field of endeavor, teaches a passivated layer on the surface of the active layers, analogous to the claimed surface of the second semiconductor layer, and that the thickness and concentration of Al in an AlGaN passivation layer create or enhance a 2 DEG layer, resulting in high 2 DEG density (Derluyn, [000043-0044]). Derluyn teaches that the aluminum content can be varied from 30% over 35% to 40% (Derluyn, [0066]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan in view of Chang with the teachings of Derluyn, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Derluyn, to obtain a high 2 DEG density for very thin AlGaN layers, thereby improving device performance and reliability.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Sheridan in view of Chang and further in view of Sun et al., US 2017/0236951 A1 (hereinafter Sun).
Regarding claim 9, Sheridan in view of Chang teaches: The structure according to claim 1, wherein the first semiconductor layer comprises a first surface facing away from the heavily doped layer (Sheridan, FIG. 2, upper surface of N-type drift layer, [0036; 0054]), (Sheridan, FIG. 2, upper surface of channel layer, [0036; 0054]) is provided with a plurality of second protrusions corresponding to the plurality of the first protrusions in position (Sheridan, FIG. 2 shows upper surface of channel layer [the second semiconductor layer] is provided with a raised region, i.e., protrusion, [0036]), or a surface of the second semiconductor layer facing away from the first semiconductor layer is flat.
Sheridan in view of Chang is silent regarding: wherein the first surface is provided with a plurality of first protrusions, and the ion implanted region is above each of the plurality of the first protrusions.
However, Sun, in the same field of endeavor, discloses a vertical semiconductor transistor wherein the first surface is provided with a plurality of first protrusions (Sun, FIG. 10 shows protrusions on upper surface of drift region 1008, analogous to the drift layer taught by Sheridan [the first semiconductor layer], [0076]), and the ion implanted region is above each of the plurality of the first protrusions (Sun, FIG. 10 shows gate regions 1006, analogous to the P-type gate region taught by Sheridan [the ion implanted region] is above the protrusions on upper surface of drift region 1008 [the first protrusions]). Sun teaches that this structural arrangement reduces the magnitude of the electric field at the intersection of the channel 1004, gate 1006, and drift region 1008, results in higher breakdown voltage, and thereby improves reliability of the vertical transistor, [0075-0076].
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sheridan in view of Chang with the teachings of Sun, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Sun, to control and shape the electric field within the vertical transistor, resulting in a higher breakdown voltage, thereby improving device performance and reliability.
Conclusion
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/D.L.N./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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