Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment and Request for Reconsideration filed May 11, 2026. Applicant’s amendments to the claims and drawings have been entered. Claims 1-3, 8-11, 14, 15 and 18-20 have been amended.
Claims 1-20 are pending, with claims 14-19 currently withdrawn from consideration.
Drawings
The drawings were objected to in the Non-Final Office Action filed February 10, 2026. The replacement drawing sheets, filed May 11, 2026, are acceptable, therefore the objection to the drawings has been withdrawn.
Response to Amendment
The amendments to the claims filed May 11, 2026 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Non-Final Office Action filed February 10, 2026.
Response to Arguments
Applicant's arguments filed May 11, 2026 have been fully considered but they are not persuasive.
Applicant argues on pages 9-11 that Son does not describe an isolation structure located between the barrier layer and the tunneling layer. This argument is not persuasive because, as explained in the rejection of claims below, FIGs. 2-3 of Son show reinforcing patterns 36 [the plurality of isolation structures] located between the first dielectric layer 38 [the barrier layer] and the second dielectric layer 42 [the tunneling layer] of adjacent vertical structures 50 [the channel columns] in the X-direction [the second direction]).
Note that Applicant’s amended independent claims remain sufficiently broad so as to encompass the structural arrangement disclosed by Son, wherein the isolation structure of one of the channel structures is located between the barrier layer and the tunneling layer of adjacent channel structures, as shown in the annotated FIG. 2 of Son shown on the following page.
Applicant argues on pages 10-11 that Son does not teach or suggest that the plurality of isolation structures are located between the dielectric layers and the tunneling layer in the second direction. This argument is not persuasive because, as explained in the rejection of claims below, FIGs. 2-3 of Son show reinforcing patterns 36 [the plurality of isolation structures] located between the interlayer insulating layers 22 [the dielectric layers] and the second dielectric layer 42 [the tunneling layer] in the X direction [the second direction perpendicular to the first direction].
Applicant argues on pages 10-11 that Son does not teach or suggest the plurality of isolation structures are in physical contact with the barrier layer. This argument is not persuasive because, as explained in the rejection of claims below, FIGs. 2-3 of Son show reinforcing patterns 36 [the plurality of isolation structures] in physical contact with first dielectric layer 38 [the barrier layer].
In response to Applicant’s argument on page 11 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from the independent claims, as amended, see the rejections of the claims below.
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Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
In the Non-Final Office Action filed February 10, 2026, claim 2 and claim 3 dependent therefrom were rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Applicant’s amendments to the claims, filed May 11, 2026, have overcome the 35 U.S.C. 112(b) rejections, therefore the rejections have been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al., US 2021/0074720 A1 (hereinafter Son).
Regarding claim 1, as amended, Son discloses: A three-dimensional memory, comprising: a stack structure (Son, FIGs. 1-4, stack structure 68, [0027]) comprising alternating stacked gate layers (Son, FIGs. 1-4, gate layers 65, [0034-0038]) and dielectric layers (Son, FIGs. 1-4, interlayer insulating layers 22, [0039]);
a plurality of channel columns penetrating the stack structure in a first direction (Son, FIGs. 1-4, multiple vertical structures 50 shown penetrating stack structure 68 [the stack structure] in the Z direction [the first direction], [0045-0046]), a channel column (Son, FIGs. 1-4, vertical structure 50) of the plurality of channel columns comprising a barrier layer (Son, FIGs. 1-4, first dielectric layer 38, [0052]), a storage layer (Son, FIGs. 2-3, data storage patterns 40, [0050; 0131-0132]), a tunneling layer (Son, FIGs. 1-4, second dielectric layer 42, [0053]), and a channel layer (Son, FIGs. 1-4, channel semiconductor layer 44, [0048]) arranged in sequence (Son, see FIGs. 2-4, [0131]); and
a plurality of isolation structures (Son, FIGs. 1-4, reinforcing patterns 36, “formed of an insulating material,” [0041]) located between the dielectric layers and the tunneling layer in a second direction perpendicular to the first direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] located between the interlayer insulating layers 22 [the dielectric layers] and the second dielectric layer 42 [the tunneling layer] in the X direction [the second direction perpendicular to the first direction], [0041-0042]), and further between the barrier layer and the tunneling layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] located between the first dielectric layer 38 [the barrier layer] and the second dielectric layer 42 [the tunneling layer] of adjacent vertical structures 50 [the channel columns] in the X-direction [the second direction]), the plurality of isolation structures are in physical contact with the barrier layer (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] in physical contact with first dielectric layer 38 [the barrier layer]), wherein the plurality of isolation structures penetrate at least a portion of the storage layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] penetrating and separating the data storage patterns 40 [the storage layer] in the X direction [the second direction], [0071]).
Regarding claim 4, Son discloses: The three-dimensional memory of claim 1, wherein an orthographic projection in the second direction (i.e., an orthographic projection in the X direction, a side view) of the plurality of isolation structures (Son, FIGs. 2-3, reinforcing patterns 36, [0041]) falls within an orthographic projection in the second direction (i.e., an orthographic projection in the X direction, a side view) of the dielectric layers (Son, FIGs. 2-3, interlayer insulating layers 22, [0039]). Note that because the reinforcing patterns 36 [the isolation structures] and the interlayer insulating layers 22 [the dielectric layers] surround the core region, and they each have at least a portion present on the same vertical plane (see FIG. 3), they would therefore at least partially overlap in a side view, i.e., fall within an orthographic projection in the second direction.
Regarding claim 5, Son discloses: The three-dimensional memory of claim 1, wherein the plurality of isolation structures penetrate the storage layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] penetrating and separating the data storage patterns 40 [the storage layer] in the X direction [the second direction], [0071]).
Regarding claim 6, Son discloses: The three-dimensional memory of claim 5, wherein the storage layer is divided into a plurality of first storage sublayers in the first direction by the plurality of isolation structures (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] dividing the data storage patterns 40 [the storage layer] into spaced apart data storage patterns 40 [first storage sublayers] in the Z direction [the first direction], [0071]).
Regarding claim 9, as amended, Son discloses: The three-dimensional memory of claim 1, wherein an orthographic projection in the second direction (i.e., an orthographic projection in the X direction, a side view) of the gate layers (Son, FIGs. 1-4, gate layers 65, [0034-0038]) falls between orthographic projections in the second direction (i.e., an orthographic projection in the X direction, a side view) of two of the plurality of isolation structures adjacent in the first direction (Son, FIGs. 2-3, reinforcing patterns 36, shown adjacent in the Z direction [the first direction]). Because the gate layers 65 [the gate layers] and the adjacent reinforcing patterns 36 [the plurality of isolation structures] surround the core region, and each have at least a portion present on different vertical planes (see FIG. 3), they would therefore not completely overlap in a side view, i.e., fall between an orthographic projection in the second direction.
Regarding claim 10, as amended, Son discloses: The three-dimensional memory of claim 1, wherein the plurality of isolation structures (Son, FIGs. 2-3, reinforcing patterns 36, [0041]) extend toward the dielectric layers (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] extend along the X-axis toward interlayer insulating layers 22 [the dielectric layers], [0039], and a portion of the plurality of isolation structures extend between two adjacent gate layers of the gate layers (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] extending along the Z-axis between two adjacent gate layers 65 [two adjacent gate layers]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 7, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al., US 2021/0074720 A1 (hereinafter Son) in view of Kanamori et al., US 2018/0033799 A1 (hereinafter Kanamori).
Regarding claim 2, as amended, Son discloses nearly every element of claim 2 but is silent regarding: wherein a size of a portion of the storage layer in the first direction between two of the plurality of isolation structures adjacent in the first direction is greater than a size of one of the gate layers in the first direction.
However, Kanamori, in the same field of endeavor, teaches: wherein a size of a portion of the storage layer in the first direction (Kanamori, FIGs 1 and 6, the first direction is shown in FIG. 1 as the X-axis, extending vertically, FIG. 6 shows the portion of the storage layer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, [0091-0092]) between two of the plurality of isolation structures adjacent in the first direction (Kanamori, FIG. 6, anti-coupling structure 425, [0048]) is greater than a size of one of the gate layers in the first direction (Kanamori, FIG. 6 shows the size of linear portion 422a and separated patterns 422b [the size of a portion of the storage layer in the first direction] is greater than a size of gate electrode 215 [the size of one of the gate layers in the first direction], [0088]). Kanamori teaches that this structural arrangement results in increased charge density in the charge trap pattern while limiting or preventing electron diffusion, which allows for size reduction of the memory device (Kanamori, [0092]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of Kanamori, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kanamori, to limit or prevent electron diffusion, thereby improving device performance and reliability while also allowing for size reduction of the memory device.
Regarding claim 3, as amended, Son in view of Kanamori teaches: The three-dimensional memory of claim 2, wherein an orthographic projection in the second direction (i.e., a side view) of the portion of the storage layer between the two of the plurality of isolation structures adjacent in the first direction (Kanamori, FIG. 6 shows the portion of the storage layer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, located between anti-coupling structure 425 [adjacent isolation structures], [0091-0092]) overlaps at least partially with an orthographic projection in the second direction (i.e., a side view) of the gate layers (Kanamori, FIGs 1 and 6 shows gate electrodes 214 and 215 [the gate layers] and the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b [the portion of the storage layer] on the same vertical plane, surrounding active column 300; an orthographic projection in the second direction, i.e., a side view, would therefore show all structural elements in the same vertical plane as overlapping).
Regarding claim 7, Son teaches nearly every element of claim 7 but is silent regarding: wherein the plurality of isolation structures penetrate a portion of a thickness of the storage layer in the second direction, and a thickness of a portion of the storage layer that is not penetrated by the plurality of isolation structures in the second direction is smaller than a preset value.
However, Kanamori, in the same field of endeavor, teaches: wherein the plurality of isolation structures penetrate a portion of a thickness of the storage layer in the second direction (Kanamori, FIG. 6 shows anti-coupling structure 425 [the plurality of isolation structures] penetrate a portion of charge trap pattern 420 [the storage layer] in the second direction, [0048]), and a thickness of a portion of the storage layer that is not penetrated by the plurality of isolation structures in the second direction (Kanamori, FIG. 6 shows the thickness of the portion of charge trap pattern 420 [the storage layer] that is not penetrated by the anti-coupling structure 425 [the plurality of isolation structures] as first pattern 421, [0048]) is smaller than a preset value (Kanamori, FIG. 6 shows first pattern 421 [the portion of the storage layer that is not penetrated by the plurality of isolation structures] having a thickness; the limitation “smaller than a preset value” is sufficiently broad so as to encompass any finite value). Kanamori teaches that this structural arrangement provides for an increased density of the charge trap in the cell region while also reducing coupling between adjacent cells (Kanamori, [0048]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of Kanamori, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kanamori, to limit or prevent electron diffusion, thereby improving device performance and reliability while also allowing for size reduction of the memory device.
Regarding claim 8, as amended, Son in view of Kanamori teaches: The three-dimensional memory of claim 7, wherein a portion of the storage layer between two of the plurality of isolation structures adjacent in the first direction (Kanamori, FIGs 1 and 6, the first direction is shown in FIG. 1 as the X-axis, extending vertically, FIG. 6 shows the portion of the storage layer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, between two adjacent anti-coupling structures 425 [isolation structures adjacent in the first direction], [0091-0092]) constitutes a second storage sublayer (Kanamori, FIG. 6 shows the second storage sublayer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, [0048]).
Regarding claim 11, as amended, Son discloses: The three-dimensional memory of claim 10, wherein a portion of the plurality of isolation structures that extends into the dielectric layers is surrounded by the barrier layer.
Son is silent regarding: a portion of the plurality of isolation structures that extends into the dielectric layers is surrounded by the barrier layer.
However, Kanamori, in the same field of endeavor, teaches: a portion of the plurality of isolation structures that extends into the dielectric layers is surrounded by the barrier layer (Kanamori, FIG. 6 shows the portion of anti-coupling structure 425 [the plurality of isolation structures] that extends into the second to sixth insulation patters 222 to 226 [the dielectric layers] is surrounded by block pattern 410 [the barrier layer], [0045-0048]). Kanamori teaches that this structural arrangement allows for the data state of each cell of the memory device to be varied, thereby enabling device functionality (Kanamori, [0047]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of Kanamori, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kanamori, to enable programming and erasing of electronic data, thereby providing for device functionality, while improving device performance and reliability while also allowing for size reduction of the memory device.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Kanamori, and further in view of Purayath et al., US 2018/0254187 A1 (hereinafter Purayath).
Regarding claim 12, Son in view of Kanamori teaches nearly every element of claim 12 but is silent regarding: wherein the barrier layer comprises a first barrier sublayer and a second barrier sublayer, wherein the second barrier sublayer is located between the first barrier sublayer and the storage layer, and the first barrier sublayer comprises a high dielectric material.
However, Purayath, in the same field of endeavor, discloses a 3D memory device, and teaches: wherein the barrier layer comprises a first barrier sublayer (Purayath, FIG. 8A, diffusion barrier layer 806, [0065]) and a second barrier sublayer (Purayath, FIG. 8A, block oxide layer 822, [0065]), wherein the second barrier sublayer is located between the first barrier sublayer and the storage layer (Purayath, FIG. 8A shows block oxide layer 822 [the second barrier sublayer] located between diffusion barrier layer 806 [the first barrier sublayer] and charge trap layer 821 [the storage layer], [0065]), and the first barrier sublayer comprises a high dielectric material (Purayath, FIG. 8A, diffusion barrier layer 806 comprises aluminum oxide, [0065]; aluminum oxide is a high-k, i.e., high dielectric, material, [0043]). Purayath teaches that this structural arrangement reduces diffusion of metal atoms from control gate (Purayath, [0065]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son in view of Kanamori with the teachings of Purayath, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Purayath, to prevent or reduce diffusion of metal atoms from control gate, thereby improving device performance and reliability.
Regarding claim 13, Son in view of Kanamori and further in view of Purayath teaches: The three-dimensional memory of claim 12, wherein the first barrier sublayer comprises an aluminum oxide material (Purayath, FIG. 8A, diffusion barrier layer 806, aluminum oxide, [0065]), and the second barrier sublayer comprises a silicon oxide material (Purayath, FIG. 8A, block oxide layer 822, silicon oxide, [0065]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Son in view of You et al., US 2019/0341396 A1 (hereinafter You).
Regarding claim 20, as amended, Son discloses: A memory system comprising: a memory device comprising one or more three-dimensional memories, wherein the one or more three-dimensional memories comprise:
a stack structure (Son, FIGs. 1-4, stack structure 68, [0027]) comprising alternating stacked gate layers (Son, FIGs. 1-4, gate layers 65, [0034-0038]) and dielectric layers (Son, FIGs. 1-4, interlayer insulating layers 22, [0039]);
a plurality of channel columns penetrating the stack structure in a first direction (Son, FIGs. 1-4, vertical structure 50 shown penetrating stack structure 68 [the stack structure] in the Z direction [the first direction], [0045-0046]), a channel column (Son, FIGs. 1-4, vertical structure 50) of the plurality of channel columns comprising a barrier layer (Son, FIGs. 1-4, first dielectric layer 38, [0052]), a storage layer (Son, FIGs. 2-3, data storage patterns 40, [0050; 0131-0132]), a tunneling layer (Son, FIGs. 1-4, second dielectric layer 42, [0053]), and a channel layer (Son, FIGs. 1-4, channel semiconductor layer 44, [0048]) arranged in sequence (Son, see FIGs. 2-4, [0131]); and
a plurality of isolation structures (Son, FIGs. 1-4, reinforcing patterns 36, “formed of an insulating material,” [0041]) located between the dielectric layers and the tunneling layer in a second direction perpendicular to the first direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] located between the interlayer insulating layers 22 [the dielectric layers] and the second dielectric layer 42 [the tunneling layer] in the X direction [the second direction perpendicular to the first direction], [0041-0042]), and further between the barrier layer and the tunneling layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] located between the first dielectric layer 38 [the barrier layer] and the second dielectric layer 42 [the tunneling layer] of adjacent vertical structures 50 [the channel columns] in the X-direction [the second direction]), the plurality of isolation structures are in physical contact with the barrier layer (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] in physical contact with first dielectric layer 38 [the barrier layer]), wherein the plurality of isolation structures penetrating at least a portion of the storage layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] penetrating and separating the data storage patterns 40 [the storage layer] in the X direction [the second direction], [0071]);
Son is silent regarding: a memory controller coupled to the memory device and configured to control the memory device
However, You, in the same field of endeavor, disclose a three-dimensional memory device and teaches: a memory controller coupled to the memory device and configured to control the memory device (You, FIG. 14, controller 1010, [0144-0146]). You teaches that by including the controller 1010 [the memory controller], data on the memories may be stored and retrieved, thereby providing for device functionality (You, [0145]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of You, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by You, to allow for data to be stored on the memory device and retrieved, thereby providing device functionality.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
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