Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on January 15, 2026, regarding the application filed September 25, 2023. Applicant’s amendments to the claims, filed January 15, 2026, have been entered.
Election/Restrictions
Applicant’s election without traverse of Invention I, corresponding to claims 1-13 and 20, in the reply filed on January 15, 2026 is acknowledged. Claims 14-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized.
Claims 1-20 are pending, with claims 14-19 currently withdrawn from consideration.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on International Patent Application PCT/CN2023/091282, filed on April 27, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 22, 2024 has been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on September 25, 2023 are objected to under 37 CFR 1.84(h)(5) because Figures 3, 6J, and 6K show(s) modified forms of construction in the same view. The hatching or shading of one or more parts is inconsistent in the same view. For example, isolation structure 232 is shown with hatching on the left side of Figures 3, 6J, and 6K and without hatching on the right side of Figures 3, 6J, and 6K; storage layer 244 is shown with different shading on the left side of Figures 3, 6J, and 6K than on the right side of Figures 3, 6J, and 6K. Applicant is encouraged to review each drawing to verify that all parts are shown with consistent hatching or shading.
Additionally, the drawings are objected to because Figure 1B shows sacrificial layers 121 and dielectric layers 111 partially overlapping when compared to Figure 1A but this is change is not described in the specification; see Figure 1b, upper left and lower right instance of sacrificial layers 121. Figure 6B is objected to for similar reasons, see upper right and lower left instances of dielectric layers 211. Figure 6C shows second barrier sublayer 2412 not as a single conformal layer, as shown in Figure 6D, but instead comprised of multiple segments separated by lines. Figures 6D, 6E, 6F, and 6G show the upper surface of the lower left instance of dielectric layers 211 at a different plane on the z-axis than the lower right instance of dielectric layers 211.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 and claim 3 dependent therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites, inter alia, “a size of a portion of the storage layer in the first direction between two of the plurality of isolation structures that are adjacent in the first direction is greater than a size of the gate layers”. This is indefinite because the term “a size of the gate layers” appears to refer to the total combined size of all the gate layers, but the size of the isolation structures, as recited in claim 1, is less than the total combined size of all the gate layers. For examination purposes, claim 2 will be interpreted as “a size of a portion of the storage layer in the first direction between two of the plurality of isolation structures that are adjacent in the first direction is greater than a size of one of the gate layers”. This interpretation is supported by, for example, FIG. 6I and paragraph 0106 of Applicant’s specification. This rejection may be overcome by amending claim 2 to clarify Applicant’s intended meaning.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al., US 2021/0074720 A1 (hereinafter Son).
Regarding claim 1, Son discloses: A three-dimensional memory, comprising: a stack structure (Son, FIGs. 1-4, stack structure 68, [0027]) comprising alternating stacked gate layers (Son, FIGs. 1-4, gate layers 65, [0034-0038]) and dielectric layers (Son, FIGs. 1-4, interlayer insulating layers 22, [0039]); a plurality of channel columns penetrating the stack structure in a first direction (Son, FIGs. 1-4, vertical structure 50 shown penetrating stack structure 68 [the stack structure] in the Z direction [the first direction], [0045-0046]) and comprising: a barrier layer (Son, FIGs. 1-4, first dielectric layer 38, [0052]), a storage layer (Son, FIGs. 2-3, data storage patterns 40, [0050; 0131-0132]), a tunneling layer (Son, FIGs. 1-4, second dielectric layer 42, [0053]), and a channel layer (Son, FIGs. 1-4, channel semiconductor layer 44, [0048]) arranged in sequence (Son, see FIGs. 2-4, [0131]); and a plurality of isolation structures (Son, FIGs. 1-4, reinforcing patterns 36, “formed of an insulating material,” [0041]) located between the dielectric layers and the tunneling layer in a second direction perpendicular to the first direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] located between the interlayer insulating layers 22 [the dielectric layers] and the second dielectric layer 42 [the tunneling layer] in the X direction [the second direction perpendicular to the first direction], [0041-0042]), wherein the plurality of isolation structures penetrate at least a portion of the storage layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] penetrating and separating the data storage patterns 40 [the storage layer] in the X direction [the second direction], [0071]).
Regarding claim 4, Son discloses: The three-dimensional memory of claim 1, wherein an orthographic projection in the second direction (i.e., an orthographic projection in the X direction, a side view) of the plurality of isolation structures (Son, FIGs. 2-3, reinforcing patterns 36, [0041]) falls within an orthographic projection in the second direction (i.e., an orthographic projection in the X direction, a side view) of the dielectric layers (Son, FIGs. 2-3, interlayer insulating layers 22, [0039]). Note that because the reinforcing patterns 36 [the isolation structures] and the interlayer insulating layers 22 [the dielectric layers] surround the core region, and they each have at least a portion present on the same vertical plane (see FIG. 3), they would therefore at least partially overlap in a side view, i.e., fall within an orthographic projection in the second direction.
Regarding claim 5, Son discloses: The three-dimensional memory of claim 1, wherein the plurality of isolation structures penetrate the storage layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] penetrating and separating the data storage patterns 40 [the storage layer] in the X direction [the second direction], [0071]).
Regarding claim 6, Son discloses: The three-dimensional memory of claim 5, wherein the storage layer is divided into a plurality of first storage sublayers in the first direction by the plurality of isolation structures (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] dividing the data storage patterns 40 [the storage layer] into spaced apart data storage patterns 40 [first storage sublayers] in the Z direction [the first direction], [0071]).
Regarding claim 9, Son discloses: The three-dimensional memory of claim 1, wherein an orthographic projection in the second direction (i.e., an orthographic projection in the X direction, a side view) of the gate layers (Son, FIGs. 1-4, gate layers 65, [0034-0038]) falls between orthographic projections in the second direction (i.e., an orthographic projection in the X direction, a side view) of two of the plurality of isolation structures that are adjacent in the first direction (Son, FIGs. 2-3, reinforcing patterns 36, shown adjacent in the Z direction [the first direction]). Because the gate layers 65 [the gate layers] and the adjacent reinforcing patterns 36 [the plurality of isolation structures] surround the core region, and each have at least a portion present on different vertical planes (see FIG. 3), they would therefore not completely overlap in a side view, i.e., fall between an orthographic projection in the second direction.
Regarding claim 10, Son discloses: The three-dimensional memory of claim 1, wherein the plurality of isolation structures (Son, FIGs. 2-3, reinforcing patterns 36, [0041]) extend toward the dielectric layers Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] extend along the X-axis toward interlayer insulating layers 22 [the dielectric layers], [0039], and a portion of the plurality of isolation structures extend between two of the gate layers that are adjacent (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] having a portion along the Z-axis that extends along the Z-axis between two adjacent gate layers 65 [two of the gate layers that are adjacent]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 7, 8, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Son et al., US 2021/0074720 A1 (hereinafter Son) in view of Kanamori et al., US 2018/0033799 A1 (hereinafter Kanamori).
Regarding claim 2, insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Son discloses nearly every element of claim 2 but is silent regarding: wherein a size of a portion of the storage layer in the first direction between two of the plurality of isolation structures that are adjacent in the first direction is greater than a size of the gate layers in the first direction.
However, Kanamori, in the same field of endeavor, teaches: wherein a size of a portion of the storage layer in the first direction (Kanamori, FIGs 1 and 6, the first direction is shown in FIG. 1 as the X-axis, extending vertically, FIG. 6 shows the portion of the storage layer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, [0091-0092]) between two of the plurality of isolation structures that are adjacent in the first direction (Kanamori, FIG. 6, anti-coupling structure 425, [0048]) is greater than a size of the gate layers (as discussed above, interpreted as “a size of one of the gate layers”) in the first direction (Kanamori, FIG. 6 shows the size of linear portion 422a and separated patterns 422b [the size of a portion of the storage layer in the first direction] is greater than a size of gate electrode 215 [the size of one of the gate layers in the first direction], [0088]). Kanamori teaches that this structural arrangement results in increased charge density in the charge trap pattern while limiting or preventing electron diffusion, which allows for size reduction of the memory device (Kanamori, [0092]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of Kanamori, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kanamori, to limit or prevent electron diffusion, thereby improving device performance and reliability while also allowing for size reduction of the memory device.
Regarding claim 3, insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Son in view of Kanamori teaches: The three-dimensional memory of claim 2, wherein an orthographic projection in the second direction (i.e., a side view) of the portion of the storage layer between the two of the plurality of isolation structures that are adjacent in the first direction (Kanamori, FIG. 6 shows the portion of the storage layer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, located between anti-coupling structure 425 [adjacent isolation structures], [0091-0092]) overlaps at least partially with an orthographic projection in the second direction (i.e., a side view) of the gate layers (Kanamori, FIGs 1 and 6 shows gate electrodes 214 and 215 [the gate layers] and the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b [the portion of the storage layer] on the same vertical plane, surrounding active column 300; an orthographic projection in the second direction, i.e., a side view, would therefore show all structural elements in the same vertical plane as overlapping).
Regarding claim 7, Son teaches nearly every element of claim 7 but is silent regarding: wherein the plurality of isolation structures penetrate a portion of a thickness of the storage layer in the second direction, and a thickness of a portion of the storage layer that is not penetrated by the plurality of isolation structures in the second direction is smaller than a preset value.
However, Kanamori, in the same field of endeavor, teaches: wherein the plurality of isolation structures penetrate a portion of a thickness of the storage layer in the second direction (Kanamori, FIG. 6 shows anti-coupling structure 425 [the plurality of isolation structures] penetrate a portion of charge trap pattern 420 [the storage layer] in the second direction, [0048]), and a thickness of a portion of the storage layer that is not penetrated by the plurality of isolation structures in the second direction (Kanamori, FIG. 6 shows the thickness of the portion of charge trap pattern 420 [the storage layer] that is not penetrated by the anti-coupling structure 425 [the plurality of isolation structures] as first pattern 421, [0048]) is smaller than a preset value (Kanamori, FIG. 6 shows first pattern 421 [the portion of the storage layer that is not penetrated by the plurality of isolation structures] having a thickness; the limitation “smaller than a preset value” is sufficiently broad so as to encompass any finite value). Kanamori teaches that this structural arrangement provides for an increased density of the charge trap in the cell region while also reducing coupling between adjacent cells (Kanamori, [0048]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of Kanamori, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kanamori, to limit or prevent electron diffusion, thereby improving device performance and reliability while also allowing for size reduction of the memory device.
Regarding claim 8, Son in view of Kanamori teaches: The three-dimensional memory of claim 7, wherein a portion of the storage layer between two of the plurality of isolation structures that are adjacent in the first direction (Kanamori, FIGs 1 and 6, the first direction is shown in FIG. 1 as the X-axis, extending vertically, FIG. 6 shows the portion of the storage layer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, between two adjacent anti-coupling structures 425 [isolation structures adjacent in the first direction], [0091-0092]) constitutes a second storage sublayer (Kanamori, FIG. 6 shows the second storage sublayer as the portion of charge trap pattern 420 that includes the linear portion 422a and separated patterns 422b, [0048]).
Regarding claim 11, Son discloses: The three-dimensional memory of claim 10, wherein the barrier layer (Son, FIGs. 2-3, first dielectric layer 38, [0052]) is located between the dielectric layers and the plurality of isolation structures (Son, FIGs. 2-3 show first dielectric layer 38 [the barrier layer] located between the interlayer insulating layers 22 [the dielectric layers] and the reinforcing patterns 36 [the plurality of isolation structures]),
Son is silent regarding: a portion of the plurality of isolation structures that extends into the dielectric layers is surrounded by the barrier layer.
However, Kanamori, in the same field of endeavor, teaches: a portion of the plurality of isolation structures that extends into the dielectric layers is surrounded by the barrier layer (Kanamori, FIG. 6 shows the portion of anti-coupling structure 425 [the plurality of isolation structures] that extends into the second to sixth insulation patters 222 to 226 [the dielectric layers] is surrounded by block pattern 410 [the barrier layer], [0045-0048]). Kanamori teaches that this structural arrangement allows for the data state of each cell of the memory device to be varied, thereby enabling device functionality (Kanamori, [0047]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of Kanamori, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Kanamori, to enable programming and erasing of electronic data, thereby providing for device functionality, while improving device performance and reliability while also allowing for size reduction of the memory device.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Son in view of Kanamori, and further in view of Purayath et al., US 2018/0254187 A1 (hereinafter Purayath).
Regarding claim 12, Son in view of Kanamori teaches nearly every element of claim 12 but is silent regarding: wherein the barrier layer comprises a first barrier sublayer and a second barrier sublayer, wherein the second barrier sublayer is located between the first barrier sublayer and the storage layer, and the first barrier sublayer comprises a high dielectric material.
However, Purayath, in the same field of endeavor, discloses a 3D memory device, and teaches: wherein the barrier layer comprises a first barrier sublayer (Purayath, FIG. 8A, diffusion barrier layer 806, [0065]) and a second barrier sublayer (Purayath, FIG. 8A, block oxide layer 822, [0065]), wherein the second barrier sublayer is located between the first barrier sublayer and the storage layer (Purayath, FIG. 8A shows block oxide layer 822 [the second barrier sublayer] located between diffusion barrier layer 806 [the first barrier sublayer] and charge trap layer 821 [the storage layer], [0065]), and the first barrier sublayer comprises a high dielectric material (Purayath, FIG. 8A, diffusion barrier layer 806 comprises aluminum oxide, [0065]; aluminum oxide is a high-k, i.e., high dielectric, material, [0043]). Purayath teaches that this structural arrangement reduces diffusion of metal atoms from control gate (Purayath, [0065]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son in view of Kanamori with the teachings of Purayath, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Purayath, to prevent or reduce diffusion of metal atoms from control gate, thereby improving device performance and reliability.
Regarding claim 13, Son in view of Kanamori and further in view of Purayath teaches: The three-dimensional memory of claim 12, wherein the first barrier sublayer comprises an aluminum oxide material (Purayath, FIG. 8A, diffusion barrier layer 806, aluminum oxide, [0065]), and the second barrier sublayer comprises a silicon oxide material (Purayath, FIG. 8A, block oxide layer 822, silicon oxide, [0065]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Son in view of You et al., US 2019/0341396 A1 (hereinafter You).
Regarding claim 20, Son discloses: A memory system comprising: a memory device comprising one or more three-dimensional memories, wherein the one or more three-dimensional memories comprise: a stack structure (Son, FIGs. 1-4, stack structure 68, [0027]) comprising alternating stacked gate layers (Son, FIGs. 1-4, gate layers 65, [0034-0038]) and dielectric layers (Son, FIGs. 1-4, interlayer insulating layers 22, [0039]); a plurality of channel columns penetrating the stack structure in a first direction (Son, FIGs. 1-4, vertical structure 50 shown penetrating stack structure 68 [the stack structure] in the Z direction [the first direction], [0045-0046]) and comprising: a barrier layer (Son, FIGs. 1-4, first dielectric layer 38, [0052]), a storage layer (Son, FIGs. 2-3, data storage patterns 40, [0050; 0131-0132]), a tunneling layer (Son, FIGs. 1-4, second dielectric layer 42, [0053]), and a channel layer (Son, FIGs. 1-4, channel semiconductor layer 44, [0048]) arranged in sequence (Son, see FIGs. 2-4, [0131]); and a plurality of isolation structures (Son, FIGs. 1-4, reinforcing patterns 36, “formed of an insulating material,” [0041]) located between the dielectric layers and the tunneling layer in a second direction perpendicular to the first direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] located between the interlayer insulating layers 22 [the dielectric layers] and the second dielectric layer 42 [the tunneling layer] in the X direction [the second direction perpendicular to the first direction], [0041-0042]), wherein the plurality of isolation structures penetrating at least a portion of the storage layer in the second direction (Son, FIGs. 2-3 show reinforcing patterns 36 [the plurality of isolation structures] penetrating and separating the data storage patterns 40 [the storage layer] in the X direction [the second direction], [0071]);
Son is silent regarding: a memory controller coupled to the memory device and configured to control the memory device
However, You, in the same field of endeavor, disclose a three-dimensional memory device and teaches: a memory controller coupled to the memory device and configured to control the memory device (You, FIG. 14, controller 1010, [0144-0146]). You teaches that by including the controller 1010 [the memory controller], data on the memories may be stored and retrieved, thereby providing for device functionality (You, [0145]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Son with the teachings of You, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by You, to allow for data to be stored on the memory device and retrieved, thereby providing device functionality.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899