Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 10-14, 19-20 in the reply filed on 03/03/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10, 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao(US 20220059540 A1, hereafter Zhao).
Regarding Claim 10, Zhao discloses:
A semiconductor structure(Fig. 1), comprising:
A first stack structure(Fig. 1 [324/323/322/321]) comprising a first region(Fig. 1 [3]) and a second region(Fig. 1 [2]);
A first electrode layer(Fig. 1 [33]) in the first region(Fig. 1 [3]) and the second region(Fig. 1 [2]), wherein the first electrode layer(Fig. 1 [33]) penetrates through the first stack structure(Fig. 1 [324/323/322/321]) along a stacking direction(vertical), and the first electrode layer(Fig. 1 [33]) in the first region(Fig. 1 [3]) and the first electrode layer(Fig. 1 [33]) in the second region(Fig. 1 [2]) are disposed as being spaced apart;
A dielectric layer(Fig. 1 [34]) in the first region(Fig. 1 [3]) and the second region(Fig. 1 [2]);
A second electrode layer(Fig. 1 [35]) in the first region(Fig. 1 [3]) and the second region(Fig. 1 [2]), wherein the dielectric layer(Fig. 1 [34]) is disposed between the first electrode layer(Fig. 1 [33]) and the second electrode layer(Fig. 1 [35]), and the second electrode layer(Fig. 1 [35]) in the first region(Fig. 1 [3]) and the second electrode layer(Fig. 1 [35]) in the second region(Fig. 1 [2]) are disposed as being spaced apart; and
A contact structure(Fig. 1 [4]) penetrating through the first stack structure(Fig. 1 [324/323/322/321]) in the second region(Fig. 1 [2]) along the stacking direction(vertical).
Regarding Claim 12, Zhao further discloses:
The dielectric layer(Fig. 1 [34]) is located on a side of the first stack structure(Fig. 1 [324/323/322/321]) and penetrates through part of the first stack structure(Fig. 1 [324/323/322/321]) in the first region(Fig. 1 [3]) and the second region(Fig. 1 [2]) along the stacking direction(vertical), and the second electrode layer(Fig. 1 [35]) is located on the first stack structure(Fig. 1 [324/323/322/321]) in the first region(Fig. 1 [3]) and covers a side of the dielectric layer(Fig. 1 [34]) within the first stack structure(Fig. 1 [324/323/322/321]) facing away from the first electrode layer(Fig. 1 [33]).
Regarding Claim 13, Zhao further discloses:
The dielectric layer(Fig. 1 [34]) the first stack structure(Fig. 1 [324/323/322/321]) covers a side of the first electrode layer(Fig. 1 [33]) in the first region(Fig. 1 [3]) and the second region(Fig. 1 [2]) facing away from the first stack structure(Fig. 1 [324/323/322/321]).
Regarding Claim 14, Zhao further discloses:
A semiconductor layer(Fig. 1 [5]), wherein the semiconductor layer(Fig. 1 [5]) is located on the first stack structure(Fig. 1 [324/323/322/321]) in the first region(Fig. 1 [3]) and covers a side of the second electrode layer(Fig. 1 [35]) within the first stack structure(Fig. 1 [324/323/322/321]) in the first region(Fig. 1 [3]) and the second region(Fig. 1 [2]) facing away from the dielectric layer(Fig. 1 [34]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Jeong et al.(US 20230039823 A1, hereafter Jeong).
Regarding Claim 11,
Zhao discloses a device in accordance with the limitations of claim 10(See above rejection). In addition, Zhao discloses their area of Fig. 1 3 as a capacitor array.
However, Zhao does not explicitly teach or disclose interior portions of the first electrode layer in the first region and the second region are disposed as being spaced apart along a first direction and a second direction, and the first direction, the second direction, and the stacking direction are perpendicular to one another.
In the same field of endeavor, Jeong discloses a capacitor array(Fig. 7) wherein interior portions of a first electrode layer(Fig. 8 [182]) are disposed as being spaced apart along a first(vertical in Fig. 7) and a second direction(horizontal in Fig. 7), and the first direction, the second direction, and the stacking direction are perpendicular to one another.
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce the device disclosed by Zhao along the lines of Jeong. When Zhao mentions a capacitor array, it is left unclear the exact arrangement by which the capacitor cells are arranged. Among them are two typical arrangements found in the art, mainly a hexagonal configuration, or a square configuration, which is claimed by the limitation of claim 11. It would have been obvious to try the square configuration of capacitor cells as one of a limited number of known options in the prior art, motivated by a desire to produce Zhao’s device, with Zhao’s disclosure alone lacking the specific guidance on the configuration of capacitor cells in the three-dimensional space. Performing this production would have generated a predictable result in the creation of Zhao’s device with a specified capacitor array.
Regarding Claim 19,
Zhao discloses a device in accordance with the limitations of claim 10.
Zhao does not teach or disclose a second stack structure, wherein the second stack structure is located on a side of the first stack structure facing away from the second electrode layer and comprises a plurality of channel structures disposed as being spaced apart along the first direction and the second direction and gate structures that extend along the second direction and connect with the plurality of channel structures, and each of the gate structures is located between two adjacent ones of the channel structures,
Wherein positions of the channel structures at least correspond to a position of the first electrode layer in the first region, and the contact structure penetrates through the first stack structure and the second stack structure along the stacking direction.
In the same field of endeavor, Jeong discloses:
a second stack structure(Fig. 8 [LP/BL]), wherein the second stack structure(Fig. 8 [LP/BL]) is located on a side of the first stack structure(Fig. 8 [180]) facing away from the second electrode layer(Fig. 8 [186]) and comprises a plurality of channel structures(Fig. 8 [AC1]) disposed as being spaced apart along the first direction and the second direction and gate structures(Fig. 8 [132A]) that extend along the second direction and connect with the plurality of channel structures(Fig. 8 [AC1]), and each of the gate structures(Fig. 8 [132A]) is located between two adjacent ones of the channel structures(Fig. 8 [AC1]),
Wherein positions of the channel structures(Fig. 8 [AC1]) at least correspond to a position of the first electrode layer(Fig. 8 [182]) in the first region(Fig. 8 [MCA]), and the contact structure(Fig. 8 [CP/PCC]) penetrates through the first stack structure(fig. 8 [180]) and the second stack structure(Fig. 8 [LP/BL]) along the stacking direction.
It would have been obvious at the time the application at hand was filed to modify the device disclosed by Zhao along the lines of Jeong. One might have been motivated to add the second stack and the accompanying features in order to produce a transistor array as to write and read the capacitor cells as disclosed by Zhao. Performing this modification would have generated a predictable result in the creation of a DRAM structure as disclosed by Zhao with read and write capabilities.
Regarding Claim 20,
Zhao discloses a device in accordance with the limitations of claim 10(See above rejection).
Zhao does not teach or disclose positions of channel structures corresponding to a position of the first electrode layer in the second region, and positions of the gate structures correspond to the first region.
In the same field of endeavor, Jeong discloses a channel structure(Fig. 8 See below) corresponding to a position of a first electrode layer(Fig. 8 [192]), and gate structures(Fig. 8 [132A]) corresponding to the first region(Fig. 8 [MCA]).
It would have been further obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Zhao along the lines of Zhao. One might have been motivated to perform this modification in order to supply the contact structure, which is in contact with the first electrode layer in the second region, with a transistor by which to control signal to or from the contact structure provided by Zhao. Performing this modification would have generated a predictable result in the device disclosed by Zhao with a channel structure coupled to the contact structure.
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Above: Fig. 8 of Jeong with channel structure denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee(US 20210175167 A1) discloses a capacitor with a peripheral contact structure. Wu et al.(US 20230006030 A1) discloses a capacitor structure with a peripheral contact. Wang(US 20230065654 A1) discloses a capacitor structure with a contact between capacitor structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897