DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in European Patent Application No. EP22201462.3, filed on 10/13/2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/25/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “ISOLATION STRUCTURE COMPRISING A HEAVILY DOPED BURIED LAYER SURROUNDED BY ANOTHER DOPED BURIED LAYER OF THE SAME CONDUCTIVITY TYPE AND A TRENCH ISOLATION STRUCTURE FOR AN ACTIVE COMPONENT”.
Claim Objections
Claim 19 is objected to because of the following informalities: On line 3 of claim 19, “the first and second buried layers” should be changed to “the first buried layer and the second buried layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16, 19-21, 24, 28, 30, and 32-33 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tsuchiko (US 2013/0072004 A1).
Regarding claim 16, Tsuchiko teaches a semiconductor device (high voltage N-channel Lateral DMOS (HV LDMOS) 430, Fig. 14, [0032]) comprising:
a substrate (comprising substrate 14 ([0026]), first epitaxial layer 16, and second epitaxial layer 18; Fig. 14, [0026]-[0027]) having a first conductivity type (p-type, [0026]-[0027]: both substrate 14 and epitaxial layer 16 are p-type), the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Fig. 14) having a top surface (see top surface labeled in Illustrative Fig. 1, which is an annotated version of Fig. 14) and a bottom surface (bottom surface, Illustrative Fig. 1);
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a first buried layer (portion 136, Illustrative Fig. 1, [0023]) disposed in the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18; Illustrative Fig. 1) at a first depth (first depth, Illustrative Fig. 1) from the top surface (top surface, Illustrative Fig. 1), wherein the first buried layer (portion 136, Illustrative Fig. 1) has a second conductivity type ([0023]: n-type) and a first doping concentration ([0022]: “Deep buried region 134 has two different species, which includes a highly doped first n-type portion, referred to as deep buried highly doped region 136 and a lightly doped second n-type portion, referred to as deep buried lightly doped region 134 with second portion 134 surrounding the first portion 136.”);
a second buried layer (deep buried region 134, Illustrative Fig. 1, [0022]) adjacent (Illustrative Fig. 1: left and right portions of the deep buried layer 134 are adjacent to the portion 136) and surrounding ([0022]) the first buried layer (portion 136, Illustrative Fig. 1) at the first depth (Illustrative Fig. 1: the deep buried region 134 surrounds the portion 136 at the first depth), wherein the second buried layer (deep buried region 134, Illustrative Fig. 1) has the second conductivity type ([0023]: n-type) and a second doping concentration ([0022]), wherein the second doping concentration is less than the first doping concentration ([0022]: “Deep buried region 134 has two different species, which includes a highly doped first n-type portion, referred to as deep buried highly doped region 136 and a lightly doped second n-type portion, referred to as deep buried lightly doped region 134 with second portion 134 surrounding the first portion 136.”); and
an isolation trench (isolation regions 140, Illustrative Fig. 1, [0024]: “isolation regions 140 are each comprised of three overlapping regions 144, 146 and 148 of p-type doping concentrations.”) disposed in the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Illustrative Fig. 1) and surrounding the second buried layer (deep buried region 134, Illustrative Fig. 1: isolation regions 140 surrounds the deep buried region 134 (also see claim 10: “isolation regions surrounding active areas of the high voltage device and low voltage device.” ), wherein the isolation trench (isolation regions 140, Illustrative Fig. 1) extends from the top surface (top surface, Illustrative Fig. 1) of the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Illustrative Fig. 1) to a second depth (second depth, Illustrative Fig. 1), the second depth (second depth, Illustrative Fig. 1) exceeding the first depth (first depth, Illustrative Fig. 1).
Regarding claim 19, Tsuchiko teaches the semiconductor device of claim 16, wherein the substrate (comprising substrate 14 ([0026]), first epitaxial layer 16, and second epitaxial layer 18; Fig. 14, [0026]-[0027]) comprises a base substrate (substrate 14, Fig. 14) and at least one epitaxial layer (first epitaxial layer 16 and second epitaxial layer 18, Fig. 14) disposed over the base substrate (substrate 14, Fig. 14), wherein the isolation trench (isolation regions 140, Fig. 14, [0024]: “isolation regions 140 are each comprised of three overlapping regions 144, 146 and 148 of p-type doping concentrations.”) and the first (portion 136, Fig. 14, [0023]) and second (deep buried region 134, Fig, 14, [0022]) buried layers are disposed in the at least one epitaxial layer (first epitaxial layer 16, Fig. 14).
Regarding claim 20, Tsuchiko teaches the semiconductor device of claim 16, further comprising a first well region (N-well 154, Illustrative Fig. 1, [0035]) disposed between the top surface (top surface, Illustrative Fig. 1) of the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Illustrative Fig. 1) and the first buried layer (portion 136, Illustrative Fig. 1, [0023]), wherein the first well region (N-well 154, Illustrative Fig. 1) has the second conductivity type (n-type; see claim 1 rejection above).
Regarding claim 21, Tsuchiko teaches the semiconductor device of claim 20, further comprising an active component (N + drain contact pickup region 155 of the HV LDMOS 430, Illustrative Fig. 1, [0035]) provided in the first well region (N-well 154, Illustrative Fig. 1).
Regarding claim 24, Tsuchiko teaches the semiconductor device of claim 16, wherein a width (see width W2 in Illustrative Fig. 2, which is an annotated version of Fig. 14) of the second buried layer (deep buried region 134, Illustrative Fig. 2) between the isolation trench (isolation regions 140, Illustrative Fig. 2) and the first buried layer (portion 136, Illustrative Fig. 2) is less than a width (width W1, Illustrative Fig. 2) of the first buried layer (portion 136, Illustrative Fig. 2).
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Regarding claim 28, Tsuchiko teaches the semiconductor device of claim 16, wherein the second buried layer (deep buried region 134, Fig. 14) is configured such that a breakdown region ([0025]: “There are three breakdown voltages to consider with the device 11. First, buried regions 134 and 136 to substrate material 14 outside active region 120. This breakdown voltage can be controlled by doping concentrations of 134, 136 and 14 and doping profiles of134 and 136. Second, a lateral breakdown voltage inside active region 120 is controlled by the lateral distance 52 between regions 134 and 136 and isolation regions 140 and doping concentrations and profiles of regions 134, 136, 14, 16 and 140. Third, a vertical breakdown voltage inside active region 120 is controlled by a vertical distance 51 between region 136 and region 126 and doping concentrations and profiles of regions 134, 136, 18 and 126.”) is spaced apart from the isolation trench ([0025]: none of the breakdown regions are at the isolation trench (separated from the isolation regions 140), because the second buried layer (deep buried region 134) is physically separated from the isolation trench, and the width and doping concentration of the second doped region (deep buried region 134) is adjusted to determine the location of first breakdown voltage particularly.), such that the isolation trench (isolation regions 140, Fig. 14) is not in direct contact with the breakdown region ([0025]: breakdown regions are separated from the isolation regions 140).
Regarding claim 30, Tsuchiko teaches a method of manufacturing a semiconductor device (high voltage N-channel Lateral DMOS (HV LDMOS) 430, Figs. 3-9 and 14, [0032]), comprising:
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providing a substrate (comprising substrate 14 ([0026]), first epitaxial layer 16, and second epitaxial layer 18; Figs. 9 and 14, [0026]-[0027]) having a first conductivity type (p-type, [0026]-[0027]: both substrate 14 and epitaxial layer 16 are p-type), the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Fig. 14) having a top surface (see top surface labeled in Illustrative Fig. 3, which is an annotated version of Fig. 14) and a bottom surface (bottom surface, Illustrative Fig. 3);
providing a first buried layer (portion 136, Illustrative Fig. 3, [0023]) in the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Illustrative Fig. 3) at a first depth (first depth, Illustrative Fig. 3) from the top surface (top surface, Illustrative Fig. 3), wherein the first buried layer (portion 136, Illustrative Fig. 3) has a second conductivity type (([0023]: n-type) and a first doping concentration ([0022]: “Deep buried region 134 has two different species, which includes a highly doped first n-type portion, referred to as deep buried highly doped region 136 and a lightly doped second n-type portion, referred to as deep buried lightly doped region 134 with second portion 134 surrounding the first portion 136.”);
providing a second buried layer (deep buried region 134, Illustrative Fig. 3, [0022]) adjacent (Illustrative Fig. 3: left and right portions of the deep buried layer 134 are adjacent to the portion 136) and surrounding ([0022]) the first buried layer (portion 136, Illustrative Fig. 3) at the first depth (Illustrative Fig. 3: the deep buried region 134 surrounds the portion 136 at the first depth), wherein the second buried layer (deep buried region 134, Illustrative Fig. 3) has the second conductivity type ([0023]: n-type) and a second doping concentration ([0022]), wherein the second doping concentration is less than the first doping concentration ([0022]: “Deep buried region 134 has two different species, which includes a highly doped first n-type portion, referred to as deep buried highly doped region 136 and a lightly doped second n-type portion, referred to as deep buried lightly doped region 134 with second portion 134 surrounding the first portion 136.”); and
providing an isolation trench (isolation regions 140, Illustrative Fig. 3, [0024]: “isolation regions 140 are each comprised of three overlapping regions 144, 146 and 148 of p-type doping concentrations.”) in the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Illustrative Fig. 3) surrounding the second buried layer (deep buried region 134, Illustrative Fig. 3: isolation regions 140 surrounds the deep buried region 134 (also see claim 10: “isolation regions surrounding active areas of the high voltage device and low voltage device.”), wherein the isolation trench (isolation regions 140, Illustrative Fig. 3) extends from the top surface (top surface, Illustrative Fig. 3) of the substrate to a second depth (second depth, Illustrative Fig. 3), the second depth (second depth, Illustrative Fig. 3) exceeding the first depth (first depth, Illustrative Fig. 3).
Regarding claim 32, Tsuchiko teaches the method of claim 30, wherein a width (see width W2 in Illustrative Fig. 4, which is an annotated version of Fig. 14) of the second buried layer (deep buried region 134, Illustrative Fig. 4) between the isolation trench (isolation regions 140, Illustrative Fig. 4) and the first buried layer (portion 136, Illustrative Fig. 4) is less than a width (width W1, Illustrative Fig. 4) of the first buried layer (portion 136, Illustrative Fig. 4).
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Regarding claim 33, Tsuchiko teaches the method of claim 30, further comprising:
providing a first well region (N-well 154, Illustrative Fig. 3, [0035]) between the top surface (top surface, Illustrative Fig. 3) of the substrate (substrate 14, first epitaxial layer 16, and second first epitaxial layer 18, Illustrative Fig. 3) and the first buried layer (portion 136, Illustrative Fig. 3, [0023]), wherein the first well region (N-well 154, Illustrative Fig. 3) has the second conductivity type (n-type; see claim 30 rejection above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17-18, 26, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiko (US 2013/0072004 A1) as applied to claims 16, 19-21, 24, 28, 30, and 32-33 above, and further in view of Vanhoucke (US 2016/0079345 A1).
Regarding claim 17, while Tsuchiko teaches the semiconductor device of claim 16,
Tsuchiko is silent on the first doping concentration, and therefore does not teach that the first doping concentration is between 5x1018/cm3 and 5x1019/cm3.
Vanhoucke, on the other hand, teaches a semiconductor device (bipolar transistor, Fig. 8B, [0035]) with a first buried layer (first part 120, Fig. 8B, [0063]) with a first doping concentration ([0063]) surrounded by a second buried layer (second part 122, Fig. 8B, [0063]) with a second doping concentration ([0063]: the conductivity of the buried layers are the same) for improved breakdown voltage ([0015]), wherein the first doping concentration is in the range of 1x1017/cm3 and 5x1018/cm3 ([0063]). While the range provided by Vanhoucke covers concentrations that are lower than the ones provided by the current application, Tsuchiko discloses that ”vertical breakdown voltage inside active region 120 is controlled by a vertical distance 51 between region 136 and region 126 and doping concentrations and profiles of regions 134, 136, 18 and 126” ([0025]), where region 136 corresponds to first buried layer of the current application and region 134 corresponds to second buried layer of the current application (Fig. 14). Therefore, it would have been person of ordinary skill in the art before the effective filing date of the claimed invention to obtain a first concentration range as claimed in the current invention, through routine optimization to achieve a desired breakdown voltage as the first doping concentration is identified as a result-effective variable for determining the breakdown voltage. Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would already know that concentrations within the claimed range have been used in buried layers serving the same purpose as evidenced by Kim (US 2017/0148873 A1, Fig. 2: the buried layer 142 has a doping concentration range of 1x1016/cm3 and 1x1020/cm3 ([0078]). Therefore, the first doping concentration being between 5x1018/cm3 and 5x1019/cm3 does not provide an inventive concept.
Regarding claim 18, while Tsuchiko teaches the semiconductor device of claim 16,
Tsuchiko is silent on the first doping concentration, and therefore does not teach that the second doping concentration is between 5x1016/cm3 and 5x1017/cm3.
Vanhoucke, on the other hand, teaches a semiconductor device (bipolar transistor, Fig. 8B, [0035]) with a first buried layer (first part 120, Fig. 8B, [0063]) with first doping concentration ([0063]) surrounded by a second buried layer (second part 122, Fig. 8B, [0063]) with a second doping concentration ([0063]: the conductivity of the buried layers are the same) for improved breakdown voltage ([0015]), wherein the second doping concentration is between 5x1016/cm3 and 5x1017/cm3 (5x1015/cm3 and 1x1017/cm3, [0063]).
Therefore, the range provided by Vanhoucke overlaps with the ranges provided by the current application. Tsuchiko further discloses that “vertical breakdown voltage inside active region 120 is controlled by a vertical distance 51 between region 136 and region 126 and doping concentrations and profiles of regions 134, 136, 18 and 126” ([0025]), where region 136 corresponds to first buried layer of the current application and region 134 corresponds to second buried layer of the current application (Fig. 14). Therefore, it would have been person of ordinary skill in the art before the effective filing date of the claimed invention to use a second concentration range similar to the one provided by Vanhoucke and optimize the range through routine experimentation to achieve a desired breakdown voltage, as the second doping concentration is identified as a result-effective variable for determing the breakdown voltage. Therefore, the second doping concentration being between 5x1016/cm3 and 5x1017/cm3 does not provide an inventive concept.
Regarding claim 26, while Tsuchiko teaches the semiconductor device of claim 16,
Tsuchiko does not teach that the isolation trench contains a polysilicon material.
Vanhoucke, on the other hand, teaches a semiconductor device (bipolar transistor, Fig. 8B, [0035]) with a first buried layer (first part 120, Fig. 8B, [0063]), a second buried layer (second part 122, Fig. 8B, [0063]), and an isolation trench (isolation region 38, Fig. 8B, [0044]), wherein the isolation trench (isolation region 38, Fig. 8B) contains a polysilicon material ([0044]: “the trenches may be filled with a combination of dielectric plus one or more other material(s) (e.g. polysilicon, as is known in the art)”).
Isolation trench structures as disclosed by Vanhoucke are common in the field for isolating neighboring regions in a device and used for the same purpose of the isolation structures disclosed by Tsuchiko (see MPEP 2144.06). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolation structures in the semiconductor device of Tsuchiko with an equivalent isolation region taught by Vanhoucke for the same purpose of lateral isolation, which would lead to an isolation trench containing a polysilicon material.
Regarding claim 31, Tsuchiko teaches the method of claim 30,
Tsuchiko is silent on the first doping concentration, and therefore does not teach that the first doping concentration is of the order of 1018/cm3 or 1019/cm3 and the second doping concentration is of the order of 1016/cm3 or 1017/cm3.
Vanhoucke, on the other hand, teaches a semiconductor device (bipolar transistor, Fig. 8B, [0035]) with a first buried layer (first part 120, Fig. 8B, [0063]) with first doping concentration ([0063]) surrounded by a second buried layer (second part 122, Fig. 8B, [0063]) with a second doping concentration ([0063]: the conductivity of the buried layers are the same) for improved breakdown voltage ([0015]), wherein the first doping concentration is between 1x1017/cm3 and 5x1018/cm3 ([0063]) and the second doping concentration is between 5x1015/cm3 and 1x1017/cm3 ([0063]). While the range of concentrations provided by Vanhoucke are slightly different than the ones provided by the current application, Tsuchiko discloses that “Deep buried region 134 has two different species, which includes a highly doped first n-type portion, referred to as deep buried highly doped region 136 and a lightly doped second n-type portion, referred to as deep buried lightly doped region 134 with second portion 134 surrounding the first portion 136” ([0022]), where region 136 corresponds to first buried layer of the current application and region 134 corresponds to second buried layer of the current application (Fig. 14), and therefore teaches that the dopant concentration of the first buried layer should be higher than the dopant concentration of the second buried layer. Tsuchiko further discloses that ”vertical breakdown voltage inside active region 120 is controlled by a vertical distance 51 between region 136 and region 126 and doping concentrations and profiles of regions 134, 136, 18 and 126” ([0025]). Therefore, it would have been person of ordinary skill in the art before the effective filing date of the claimed invention to obtain a first concentration range and a second concentration range as claimed in the current invention, through routine optimization to achieve a desired breakdown voltage as the first doping concentration and the second doping concentration are identified as result-effective variables for the breakdown voltage. Furthermore, a person of ordinary skill in the art before the effective filing date of the claimed invention would already know that concentrations covering the claimed range have been used in buried layers serving the same purpose as evidenced by Kim (US 2017/0148873 A1, Fig. 2: the buried layer 142 has a doping concentration range of 1x1016/cm3 and 1x1020/cm3 ([0078]). Therefore, the first doping concentration being between 5x1018/cm3 and 5x1019/cm3 and the second doping concentration being between 5x1016/cm3 and 5x1017/cm3 do not provide inventive concepts.
Claims 22 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiko (US 2013/0072004 A1) as applied to claims 16, 19-21, 24, 28, 30, and 32-33 above, and further in view of Liao (US 2024/0047460 A1).
Regarding claim 22, while Tsuchiko teaches the semiconductor device of claim 20,
Tsuchiko does not teach a second well region disposed between the first well region and the isolation trench, wherein the second well region has the second conductivity type and surrounds the first well region.
Liao, on the other hand teaches a high-voltage semiconductor device (semiconductor device 100, Fig. 1, [0021]) with buried layers (first buried layer 107 and second buried layer 109, Fig. 1, [0021]: first conductivity type (n-type) corresponding the second conductivity type of the current application), isolation trenches (deep trench isolation structure 120, Fig. 1, [0024]), and a first well region (first well region 111, Fig. 1, [0022]: first conductivity type), wherein the semiconductor device
further comprising a second well region (third well region 115, Fig. 1, [0022]: first conductivity type (n-type) corresponding the second conductivity type of the current application) disposed between the first well region (first well region 111, Fig. 1) and the isolation trench (deep trench isolation structure 120, Fig. 1), wherein the second well region (third well region 115, Fig. 1) has the second conductivity type ([0022]) and surrounds the first well region (first well region 111, Fig. 1, [0022]: “The third well region 115 is disposed in the second epitaxial layer 105 of the substrate 10 and surrounds the first well region 111 and the second well region 113 in a top view”).
Liao further discloses that including a heavily doped contact region 157 that is electrically coupled to an isolation voltage (Visa), and coupling the first buried layer 107, the second buried layer 109 and the third well region 115 to the isolation voltage (Visa) through the heavily doped contact region 157 would avoid unnecessary substrate leakage current during the operation of the semiconductor device 100 (Liao, [0026]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor device of Tsuchiko is analogous to the semiconductor device of Liao, and be motivated to include another P-well region (P-well region 156, Fig. 14) on the other side of the first well region (N-well region 154, Fig. 14), and a second well region of second conductivity type with a heavily doped region (analogous to the heavily doped region 157 of Liao) between the first well regions and the trench isolation region, as taught by Liao, in the semiconductor device of Tsuchiko, to obtain the benefit of avoiding unnecessary substrate leakage current during the operation of the semiconductor device.
Thus, the combination of Tsuchiko and Liao meets all the limitations of claim 22.
Regarding claim 34, while Tsuchikoteaches the method of claim 33,
Tsuchiko does not teach that the method further comprises:
providing a second well region between the isolation trench and the first well region, such that the second well region is perimetric to the first well region and the isolation trench is perimetric to the second well region.
Liao, on the other hand teaches a method for manufacturing a high-voltage semiconductor device (semiconductor device 100, Figs. 1 and 4-9, [0021]) wherein the method comprises forming buried layers (first buried layer 107 and second buried layer 109, Figs. 1 and 4-5, [0031]-[0032]: first conductivity type (n-type) corresponding the second conductivity type of the current application), isolation trenches (deep trench isolation structure 120, Figs. 1 and 6-7, [0034]-[0035]), and a first well region (first well region 111, Figs. 1 and 9, [0037]: first conductivity type), wherein the method
providing a second well region (third well region 115, Figs. 1 and 9, [0022]: first conductivity type (n-type) corresponding the second conductivity type of the current application) between the isolation trench (deep trench isolation structure 120, Fig. 1) and the first well region (first well region 111, Fig. 1), such that the second well region (third well region 115, Fig. 1) is perimetric to the first well region (first well region 111, Fig. 1, [0022]: “The third well region 115 is disposed in the second epitaxial layer 105 of the substrate 10 and surrounds the first well region 111 and the second well region 113 in a top view”, and therefore second well region is perimetric to the first well region).
Liao further discloses that including a heavily doped contact region 157 (Fig. 1: heavily doped contact region is directly on the top surface of the third well region 115, Fig. 1) that is electrically coupled to an isolation voltage (Visa), and coupling the first buried layer 107, the second buried layer 109 and the third well region 115 to the isolation voltage (Visa) through the heavily doped contact region 157 would avoid unnecessary substrate leakage current during the operation of the semiconductor device 100 (Liao, Fig. 1, s[0026]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor device manufactured by the method of Tsuchiko is analogous to the semiconductor device manufactured by the method of Liao, and be motivated to include steps in the method of Tsuchiko to form another P-well region (P-well region 156, Fig. 14) on the other side of the first well region (N-well region 154, Fig. 14), and a second well region that is perimetric to the first well region, as taught by Liao, to obtain a semiconductor device that avoids unnecessary substrate leakage current during operation.
Thus, the combination of Tsuchiko and Liao meets all the limitations of claim 34.
Claims 23 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiko (US 2013/0072004 A1) in view of Liao (US 2024/ 0047460A1) as applied to claims 22 and 34 above, and further in view of Kan (US 2020/0194581 A1).
Regarding claim 23, while Tsuchiko in view of Liao teaches the semiconductor device of claim 22,
both Tsuchiko and Liao are silent on that the second well region has a doping concentration that is of the same order as the second doping concentration.
Kan, on the other hand, teaches a semiconductor device (semiconductor device 10, Figs. 1-3; [0017]) comprising a second well region (third well region 106 and fourth well region 108, Fig. 3; [0027]: third well region 106 and fourth well region 108 together are analogous in function and structure to the second well region of the semiconductor device of Tsuchiko in view of Liao), wherein the second well region (third well region 106 and fourth well region 108, Fig. 3) has a doping concentration ([0028]: 1017 cm--3) that is of the same order as the second doping concentration (the doping concentration of the buried layer 202 which can be 1017 cm-3 ([0021]), Fig. 3).
Kan further discloses that a plurality of wells (e.g., the third well 106 and the analogous fourth well 108 (see Fig. 3)), partially surrounding a source region, along with deep trench isolation may reduce or avoid the occurrence of leakage current in the substrate, and reduce or avoid the latch-up effect ([0016]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to set the doping concentration of the second well to be of the same order as the second doping concentration, as disclosed by Kan, in the semiconductor device of Tsuchiko in view of Liao, to reduce the leakage current in the substrate.
Regarding claim 35, while Tsuchiko in view of Liao teaches the method of claim 34, wherein
Tsuchiko is silent about the second well region, and therefore does not teach that the second well region has the second conductivity type and a doping concentration that is of the same order as the second doping concentration.
Liao, on the other hand, teaches a method wherein the second well region (third well region 115, Figs. 1, [0022]) has the second conductivity type ([0022]: first conductivity type (n-type) corresponding the second conductivity type of the current application).
Liao further discloses that including a heavily doped contact region 157 (Fig. 1: heavily doped contact region is directly on the top surface of the third well region 115, Fig. 1) that is electrically coupled to an isolation voltage (Visa), and coupling the first buried layer 107, the second buried layer 109 and the third well region 115 to the isolation voltage (Visa) through the heavily doped contact region 157 would avoid unnecessary substrate leakage current during the operation of the semiconductor device 100 (Liao, Fig. 1, s[0026]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would realize that the semiconductor device manufactured by the method of Tsuchiko is analogous to the semiconductor device manufactured by the method of Liao, and be motivated to form the second well region in the method of in the method of Tsuchiko in view of Liao to be of the second conductivity type, as taught by Liao, to obtain a semiconductor device that avoids unnecessary substrate leakage current during operation. Thus, the combination of Tsuchiko and Liao meets the limitation that the second well region has the second conductivity type.
The combination of Tsuchiko and Liao, however, is silent on that a doping concentration that is of the same order as the second doping concentration.
Kan, on the other hand, teaches a semiconductor device (semiconductor device 10, Figs. 1-3; [0017]) comprising a second well region (third well region 106 and fourth well region 108, Fig. 3; [0027]: third well region 106 and fourth well region 108 together are analogous in function and structure to the second well region of the semiconductor device manufactured by the method Tsuchiko in view of Liao), wherein the second well region (third well region 106 and fourth well region 108, Fig. 3) has a doping concentration ([0028]: 1017 cm--3) that is of the same order as the second doping concentration (the doping concentration of the buried layer 202 which can be 1017 cm-3 ([0021]), Fig. 3).
Kan further discloses that a plurality of wells (e.g., the third well 106 and the analogous fourth well 108 (see Fig. 3)), partially surrounding a source region, along with deep trench isolation may reduce or avoid the occurrence of leakage current in the substrate, and reduce or avoid the latch-up effect ([0016]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to set the doping concentration of the second well to be of the same order as the second doping concentration, as disclosed by Kan, in the method of Tsuchiko in view of Liao, to reduce the leakage current in the substrate.
Thus, the combination of Tsuchiko, Liao, and Kan meets all the limitations of claim 35.
Claims 25 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchiko (US 2013/0072004 A1) as applied to claims 16, 19-21, 24, 28, 30, and 32-33 above.
Regarding claim 25, while Tsuchiko teaches the semiconductor device of claim 24,
Tsuchiko is silent on the device dimensions, and therefore does not teach that a width of the second buried layer between the isolation trench and the first buried layer is between 1 and 5 µm.
A person of ordinary skill in the art before the effective filing date of the claimed invention, however, would know that the typical dimension of a single buried layer between isolation trenches in semiconductor devices such as the one taught by Tsuchiko are about 1-10 µm, as evidenced by Yang (US 2016/0181421 A1, the width of the buried layer 112 (Fig. 2) is in the range of about 1 µm to about 10 µm ([0027]). Furthermore, Tsuchiko discloses that “a lateral breakdown voltage inside active region 120 is controlled by the lateral distance 52 between regions 134 and 136 and isolation regions 140 and doping concentrations and profiles of regions 134, 136, 14, 16 and 140.” (Fig. 14, [0025]). Therefore, it would have been person of ordinary skill in the art before the effective filing date of the claimed invention to obtain a width of the second buried layer between the isolation trench and the first buried layer is between 1 and 5 µm, as claimed in the current invention, through routine optimization to achieve a desired breakdown voltage as the distance 52 (Fig. 14) is identified as a result-effective variable for the breakdown voltage and directly related with the width of the second buried layer between the isolation trench and the first buried layer. Accordingly, the width of the second buried layer between the isolation trench and the first buried layer does not provide an inventive concept.
Allowable Subject Matter
Claims 27 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 27, disclosing that “the first and second buried layers have the same height”, would be allowable if the height relationship between the first buried layer and the second buried layer is written in an independent form or incorporated with claim 16.
Claim 29, disclosing that “the breakdown region is spaced apart from the isolation trench by a distance equal to the width of the second buried layer”, would be allowable if claim 29 is written in an independent form or if this limitation is incorporated in a claim combining claims 16 and 28.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shin (US 2022/0189955 A1) teaches a semiconductor device with a second buried epitaxial layer of second conductivity surrounding the first buried layer of second conductivity type between an isolation trench, which is relevant to all claims.
Mallikarjunaswamy (US 2018/0286853 A1) teaches a semiconductor device with a second buried epitaxial layer of second conductivity surrounding the first buried layer of second conductivity type between an isolation trench, which is relevant to all claims.
Lin (US 2015/0137327 A1) teaches a semiconductor device with a second buried epitaxial layer of second conductivity surrounding the first buried layer of second conductivity type between an isolation trench, which is relevant to all claims.
Tsuchiko (US 2016/0254347 A1) teaches a semiconductor device with a buried layer surrounded an isolation trench, which is relevant to all claims.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812