Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 17, 19, and 21-22are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "third thin film transistor" in line 2. There is insufficient antecedent basis for this limitation in the claim. Specifically, neither claim 17 nor claim 1, upon which claim 17 depends, disclose a second thin film transistor. For the sake of further analysis, claim 17 is interpreted as disclosing an additional (i.e., a second) thin film transistor; by extension, this also applies to the sub-components that make up said transistor (e.g., a third source electrode, third drain electrode, etc.). Similarly, claim 24 recites “the third film transistor” and as such is interpreted in the same manner as claim 17.
Claim 19 recites the limitation " wherein a mobility of the first active layer is greater than a mobility of the second active layer" (emphasis added) in line 2. There is insufficient antecedent basis for this limitation in the claim. Specifically, neither claim 19 nor the claims upon which it depends (claims 18, 17, and 1), disclose the formation of a second active layer. For the sake of further analysis, the “second active layer” disclosed in claim 19 is interpreted to mean the same as the “third active layer” belonging to the “third film transistor” previously disclosed in claim 17.
Claims 21 and 22 recite the limitation "a second gate insulating layer" in line 2 of each claim. There is insufficient antecedent basis for this limitation in the claim. Specifically, neither of these claims, as well as the claims upon which they depend (claims 20, 17, and 1), disclose a first gate insulating layer. For the sake of further analysis, claim 17 is interpreted as disclosing a single (i.e., a first) gate insulating layer.
Claim Rejections - 35 USC § 102
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kim (US Patent No. 8674362).
Regarding claim 1, Kim teaches a thin film transistor substrate comprising: a first thin film transistor disposed on a base substrate, the first thin film transistor including a first source electrode, a first drain electrode, a first active layer and a first gate electrode, wherein the first gate electrode is disposed on the first active layer and includes a transparent conductive oxide semiconductor material (Figs. 5 and 9 point to a thin film transistor 10 comprising a substrate 111, a source electrode 174, a drain electrode 175, a gate electrode 153, and an active layer 133.).
Claim Rejections - 35 USC § 103
Claim(s) 2, 4, 17-21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Patent No. 8674362).
Regarding claim 2, Kim teaches wherein the first active layer includes an oxide semiconductor material different from the transparent oxide semiconductor material of the first gate electrode (Col. 3, line 64 – Col. 4, line 3 point to the active layer 133 comprising a semiconductor material, i.e., an amorphous silicon layer, a polysilicon layer, or an oxide semiconductor layer. Figs. 2-3 and Col. 4, lines 33-36 further point to the transparent conductive layer 1502/1532 of the gate electrode 153 comprising at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). It is considered obvious that one of ordinary skill in the art would use different transparent oxide semiconductor materials to form the active layer and first gate electrode respectively due to the different functions of each component.).
Regarding claim 4, Kim teaches wherein the first gate electrode includes at least one of a IGZO(InGaZnO)-based oxide semiconductor material and a IGO(InGaO)-based oxide semiconductor material, and wherein a concentration of the gallium (Ga) is higher than a concentration of the indium (In) based on a number of atoms (Col. 4, lines 33-36 point to the transparent conductive layer 1502/1532 of the gate electrode 153 comprising indium gallium oxide (IGO). It is considered obvious that one of ordinary skill in the art would adjust the conductive layer such that the concentration of gallium is higher than that of the indium in order to improve stability and suppress free carriers.).
Regarding claim 17, Kim teaches a third thin film transistor including a third source electrode, a third drain electrode, a third active layer and a third gate electrode, wherein the third active layer includes a same material as the first gate electrode of the first thin film transistor, and wherein the third gate electrode is disposed on the third active layer (Figs. 5 and 9 point to a thin film transistor 10 comprising a substrate 111, a source electrode 174, a drain electrode 175, a gate electrode 153, and an active layer 133. The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Furthermore, Col. 3, line 64 – Col. 4, line 3 and Col. 4, lines 33-36 point to the active layer 133 comprising an oxide semiconductor layer and the transparent conductive layer 1502/1532 of the gate electrode 153 comprising at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO).).
Regarding claim 18, Kim teaches wherein the third active layer includes an oxide semiconductor material different from an oxide semiconductor material of the first active layer (Col. 3, line 64 – Col. 4, line 3 point to the active layer 133 comprising a semiconductor material, i.e., an amorphous silicon layer, a polysilicon layer, or an oxide semiconductor layer. Figs. 2-3 and Col. 4, lines 33-36 further point to the transparent conductive layer 1502/1532 of the gate electrode 153 comprising at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). It is considered obvious that one of ordinary skill in the art would use different transparent oxide semiconductor materials to form the first and third active layers respectively due to the different functions of each component.).
Regarding claim 19, Kim teaches wherein a mobility of the first active layer is greater than a mobility of the second active layer (Col. 3, line 64 – Col. 4, line 3 point to the active layer 133 comprising a semiconductor material, i.e., an amorphous silicon layer, a polysilicon layer, or an oxide semiconductor layer. Figs. 2-3 and Col. 4, lines 33-36 further point to the transparent conductive layer 1502/1532 of the gate electrode 153 comprising at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). It is considered obvious that one of ordinary skill in the art would alter the mobility of the first and second active layers according to the specific performance requirements of the overall transistor that each active layer is connected to.).
Regarding claim 20, Kim teaches wherein the third active layer includes a channel part, a first connection part disposed on a first side of the channel part and a second connection part disposed on a second side of channel part (Fig. 3 of Kim points to an active layer 133 comprising a channel region 1333 (channel part), a source region 1334 (first connection part), and a drain region 1335 (second connection part).), and wherein the first gate electrode is formed of a same material and a same process as the first connection part and the second connection part of the third active layer (Col. 3, line 64 – Col. 4, line 3 and Col. 4, lines 33-36 point to the active layer 133 comprising an oxide semiconductor layer and the transparent conductive layer 1502/1532 of the gate electrode 153 comprising at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Fig. 3 further points to a manufacturing step (same process) in the formation of an OLED display wherein the gate electrode 153, the source region 1334 (first connection part), and the drain region 1335 (second connection part) are first introduced.).
Regarding claim 21, Kim teaches a second gate insulating layer disposed on the first gate electrode and the third active layer (Fig. 4 points to an insulation layer 160.), wherein the first gate electrode, the first connection part of the third active layer and the second connection part of the third active layer include a same type of dopant (Col. 5, lines 1-11 point to an ion impurity that is doped in a portion of the active layer 133 by using the gate electrode 153 as a self-align mask, resulting in the formation of the source region 1334 (first connection part), and the drain region 1335 (second connection part).).
Regarding claim 23, Kim teaches a gate insulating layer disposed on the first active layer of the first thin film transistor, wherein the first gate electrode of the first thin film transistor and the third active layer of the third thin film transistor are disposed on a same layer on the gate insulating layer (Fig. 3 points to an insulating layer 140 disposed between the active layer 133 (first active layer) and the gate electrode 153. The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Additionally, the rearrangement of parts which would not have modified the operation of the device is considered an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).). Thus, it would have been obvious to one of ordinary skill in the art to not only duplicate the disclosed structure of a thin film transistor, but to also rearrange its height/position such that the gate electrode of the first transistor is disposed on the same layer as the third active layer of the third thin film transistor.).
Claim(s) 3, 5-6, 8, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in further view of Kang (PGPub No. 20160380113).
Regarding claim 3, Kang teaches wherein the first gate electrode includes at least one of a GZO(GaZnO)-based oxide semiconductor material, and a GZTO(GaZnSnO)-based oxide semiconductor material ([0055] points to a gate electrode GE which may include gallium doped zinc oxide (GZO).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Kim and Kang, such that the first gate electrode includes in order to a GZO(GaZnO)-based oxide semiconductor material in order to create a gate electrode with transparent conductivity, good work function compatibility, and/or compatibility with oxide processing.
Regarding claim 5, Kang teaches wherein the first active layer includes at least one of a IZO(InZnO)-based oxide semiconductor material, a ITZO(InSnZnO)- based oxide semiconductor material, a FIZO(FeInZnO)-based oxide semiconductor material, a ZnO-based oxide semiconductor material, a SIZO(SiInZnO)-based oxide semiconductor material, and a ZnON-based oxide semiconductor material ([0078] points to an active layer 111 which may be formed to include an oxide semiconductor layer including indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), hafnium indium zinc oxide (HIZO) and etc.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Kang, such that the first active layer comprises a ITZO(InSnZnO)- based oxide semiconductor material in order to create a layer that prioritizes high performance by maximizing mobility and drive current.
Regarding claim 6, Kang teaches wherein the first active layer includes at least one of a IGZO(InGaZnO)-based oxide semiconductor material and a IGZTO(InGaZnSnO)-based oxide semiconductor material, and wherein a concentration of the indium (In) is higher than a concentration of the gallium (Ga) based on a number of atoms ([0078] points to an active layer 111 which may be formed to include an oxide semiconductor layer including indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), hafnium indium zinc oxide (HIZO) and etc. It is considered obvious that one of ordinary skill in the art would adjust the conductive layer such that the concentration of indium is higher than that of the gallium in order to increase conductivity.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Kang, such that the first active layer comprises a IGZO(InGaZnO)-based oxide semiconductor material in order to balance good mobility, low leakage, high uniformity, and excellent long-term stability.
Regarding claim 8, Kang teaches a gate driver disposed on the substrate (Fig. 1 points to a gate driving part 330 disposed on a first substrate 110.) and including a plurality of thin film transistors connected in parallel with each other, wherein the plurality of thin film transistors include the first thin film transistor (Fig. 1 and [0006] point to a plurality of pixels PE, wherein each pixel is connected to a transistor TR.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Kang, such that a gate driver and a plurality of thin film transistors are formed in order to create a liquid crystal display apparatus.
Regarding claim 25, Kim in combination with Kang teaches a display apparatus comprising: a plurality of subpixels (Fig. 1, [0006], and [0051] of Kang point to a display apparatus 100 comprising a plurality of pixels PE.); and the thin film transistor substrate according to claim 1 (Figs. 5 and 9 of Kim point to a thin film transistor 10 comprising a substrate 111.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Kang, such that a plurality of subpixels is further formed in order to create a liquid crystal display apparatus.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in further view of Gosain (PGPub No. 20100171120).
Regarding claim 7, Gosain teaches a first conductive material layer disposed on a first side of the first active layer of the first thin film transistor, and a second conductive material layer disposed on a second side of the first active layer of the first thin film transistor, wherein the first conductive material layer is electrically connected to the first source electrode, and the second conductive material layer is electrically connected to the first drain electrode (Fig. 5 points to a first element forming portion 21 (first thin film transistor) comprising a channel layer 25 (first active layer), a source 26 (first conductive material layer), a drain 27 (second conductive material layer), a source electrode 28, and a drain electrode 29.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Gosain, such that a first conductive material layer and a second conductive material layer are formed in order to create a channel that electrically connects the source and drain electrodes and is controlled by the gate electrode.
Regarding claim 22, Kim teaches a second gate insulating layer disposed on the third active layer without overlapping with the first gate electrode (Fig. 3 points to an insulating layer 140.).
Kim fails to teach wherein the first gate electrode, the first connection part of the third active layer and the second connection part of the third active layer are plasma treated.
Gosain teaches wherein the first gate electrode, the first connection part of the third active layer and the second connection part of the third active layer are plasma treated (Fig. 9 and [0084] point to applying a PECVD (plasma enhanced chemical vapor deposition) method on the gate electrodes 23 and 33 to form a gate insulating film 24. Fig. 10 and [0087] further point to the use of plasma implantation to form the source 26 (first connection part) and the drain 27 (second connection part).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Gosain, such that the first gate electrode, first connection part, and the second connection part are plasma treated in order to improve electrical characteristics by creating a cleaner interface on each component.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in further view of Kusumi (PGPub No. 20190279589).
Regarding claim 9, Kusumi teaches wherein the gate driver includes a shift register, and the shift register includes a pull-up transistor configured to output a gate on signal and a pull-down transistor configured to output a gate-off signal, and wherein the pull-up transistor or the pull-down transistor includes the first thin film transistor (Fig. 3 points to a first gate driver 410 comprising a unit main circuit 41m (shift register), an activation transistor T01 (pull-up transistor), and an inactive transistor T02 (pull-down transistor).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Kusumi, such that the gate driver includes a shift register, pull-up transistor, and pull-down transistor in order to form a monolithic gate driver for a display device.
Claim(s) 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in further view of Tada (US Patent No. 7361947).
Regarding claim 10, Kim teaches a second thin film transistor including a second source electrode, a second drain electrode, a second active layer, and a second gate electrode; and wherein the second gate electrode is disposed on the second active layer and includes a transparent conductive oxide semiconductor material (Figs. 5 and 9 point to a thin film transistor 10 comprising a substrate 111, a source electrode 174, a drain electrode 175, a gate electrode 153, and an active layer 133. The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).).
Kim fails to teach a light shielding layer disposed on the second thin film transistor, and wherein the light shielding layer overlaps with the second gate electrode.
Tada teaches a light shielding layer disposed on the second thin film transistor, and wherein the light shielding layer overlaps with the second gate electrode (Fig. 4 points to a photoelectric conversion element comprising P electrodes 14 and 15 which include portions (light shielding layer) that cover the gate electrode 7 and function as light shield members.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Tada, such that a light shielding layer is formed in order to protect the underlying region(s) by preserving low leakage, stable threshold voltage, and reliable operation.
Regarding claim 11, Kim teaches wherein one end of the second gate electrode is aligned with one end of a channel part of the second active layer (Fig. 5 points to the gate electrode 153 and a channel region 1333 (channel part).).
Regarding claim 12, Tada teaches wherein the light shielding layer is disposed on a same layer as the second source electrode and the second drain electrode (Fig. 4 points to a photoelectric conversion element comprising P electrodes 14 (second source electrode) and 15 (second drain electrode) which include portions (light shielding layer) that cover the gate electrode 7 and function as light shield members.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim and Tada, such that a light shielding layer is formed in order to protect the underlying region(s) by preserving low leakage, stable threshold voltage, and reliable operation.
Regarding claim 13, Kim teaches wherein the second gate electrode of the second thin film transistor includes a same material as the first gate electrode of the first thin film transistor, and the second gate electrode of the second thin film transistor is disposed on a same layer as the first gate electrode of the first thin film transistor (Figs. 5 and 9 point to a thin film transistor 10 comprising a gate electrode 153. The court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).).
Regarding claim 14, Gosain teaches a first conductive material layer disposed on a first side of the second active layer of the second thin film transistor; and a second conductive material layer disposed on a second side of the second active layer of the second thin film transistor (Fig. 5 points to a first element forming portion 21 (second thin film transistor) comprising a channel layer 25 (second active layer), a source 26 (first conductive material layer), a drain 27 (second conductive material layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Gosain, such that a first conductive material layer and a second conductive material layer are formed in order to create a channel that electrically connects the source and drain electrodes and is controlled by the gate electrode.
Regarding claim 15, Kusumi teaches a gate driver disposed on the substrate, the gate driver including a shift register, wherein the shift register includes a buffer unit and a node controller, wherein the buffer unit includes the first thin film transistor, and wherein the node controller includes the second thin film transistor (Figs. 3 & 5 and [0051] point to a first gate driver 410 comprising a unit main circuit 41m (shift register), a bistable circuit 41bs (node controller), and a second area (buffer unit) best defined by the components positioned between a signal NA and a driving output terminal G.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Kusumi, such that the shift register includes a buffer unit and a node controller in order to generate robust, accurate gate signals under the electrical loading of a large display.
Regarding claim 16, Kim in combination with Tada teaches a connection electrode connecting the first thin film transistor of the buffer unit with the second thin film transistor of the node controller, wherein the connection electrode and the light shielding layer are provided as one body (Fig. 4 of Tada points to a photoelectric conversion element comprising P electrodes 14 and 15 which include portions (light shielding layer) that cover the gate electrode 7 and function as light shield members. Fig. 5 of Kim points to the source electrode 174 having an extension (connection electrode) located between and connecting a contact hole 644 and a metal layer 711.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Tada, such that the first and second thin film transistors are connected by a connection electrode in order to establish proper communication between the two components.
Claim(s) 24 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in further view of Park (PGPub No. 20200211476).
Regarding claim 24, Park teaches pixel region defined on the substrate (Fig. 1 points to an OLED display comprising a pixel array arranged on a display panel 100 (substrate).), wherein the pixel region includes a plurality of thin film transistors, the plurality of thin film transistors includes a light emitting control transistor and a driving thin film transistor, the first thin film transistor includes the light emitting control transistor, and the third film transistor includes the driving thin film transistor (Fig. 3 points to a pixel structure comprising a first emission control transistor T4 and a driving transistor DT.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kim et al. and Park, such that a pixel region comprising a plurality of thin film transistors is formed in order to create a pixel structure that uses an internal compensation method to reduce luminance non-uniformity across the entire array.
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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