DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of Invention I which corresponds to claims 1-17 in the reply filed on 04/01/2026 is acknowledged. The traversal is noted but is not found persuasive. While claims 1 and 18 share overlapping limitations directed to the multi-part lower electrode and supporter layer structure, claim 18 recites numerous additional limitations directed to a complete semiconductor memory cell. These additional elements render the inventions of Group I and Group II distinct and impose a serious search and examination burden. The identified groups remains properly restricted.
Accordingly, the restriction requirement is maintained. Claims 18-20 are withdrawn from further consideration, pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Inventions or Species.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/25/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example: Semiconductor Device Having Stacked Lower Electrodes and a Supporter Layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 8-10, 12-14 and 17 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by WOO et.al. (US-2021/0384194-A1, hereinafter WOO)
Regarding Claim 1.
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WOO teaches in Fig.11 and in related text A semiconductor device, comprising:
a substrate (#102);
a plurality of lower electrodes (#BE/#43) on the substrate;
at least one supporter layer (#112a/#112b) in contact with the plurality of lower electrodes (#BE);
a dielectric layer (#DL) on the plurality of lower electrodes and the at least one supporter layer; and
an upper electrode (#TE) on the dielectric layer, wherein
each of the plurality of lower electrodes includes a first lower electrode (#43a) and a second lower electrode (#43b) on the first lower electrode,
the at least one supporter layer includes a first supporter layer (#112b) in contact with a side surface of an upper region of the first lower electrode (#43a), and
a level of an uppermost end of the second lower electrode (#43b) is higher than a level of an upper surface of the first supporter layer (#112b). ([0072-0075])
Regarding Claim 2.
WOO teaches The semiconductor device of claim 1,
WOO further teaches wherein at least a portion of an upper surface of the first lower electrode (#43a) is coplanar with an upper surface of the first supporter layer (#112b). (See Fig.11) ([0072-0075])
Regarding Claim 8.
WOO teaches The semiconductor device of claim 1,
WOO further teaches wherein
the at least one supporter layer (#112b/#112a) further includes a second supporter layer(#112a), and
a level of the second supporter layer (#112a) is lower than a level of the first supporter layer (#112b).
Regarding Claim 9.
WOO teaches The semiconductor device of claim 8,
WOO further teaches wherein a thickness of the first supporter layer (#112b) is greater than a thickness of the second supporter layer (#112a).
Regarding Claim 10.
WOO teaches The semiconductor device of claim 1,
WOO further teaches wherein at least a portion of a contact surface between the first lower electrode (#43a) and the second lower electrode (#43b) is coplanar with an upper surface of the first supporter layer (#112b).
Regarding Claim 12.
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WOO teaches The semiconductor device of claim 1,
WOO further teaches in Fig. 16 and Fig. 18 and in related text further comprising:
a plurality of word lines (#WL) extending in a first direction on the substrate; and
a plurality of bit lines (#BL) extending in a second direction on the substrate, wherein
the second direction intersects the first direction, and
a level of the plurality of lower electrodes is higher than a level of the plurality of word lines and a level of the plurality of bit lines. (Fig.16 [0082-0089])
Regarding Claim 13.
WOO teaches in Fig.11 and in related text A semiconductor device, comprising:
a substrate (#102);
a plurality of lower electrodes on the substrate (#BE);
at least one supporter layer (#112a/#112b) in contact with the plurality of lower electrodes (#BE);
a dielectric layer (#DL) on the plurality of lower electrodes; and
an upper electrode (#TE) on the dielectric layer, wherein
the plurality of lower electrodes include a first lower electrode (#43a) and a second lower electrode (#43b),
the second lower electrode is in contact with an upper surface of the first lower electrode,
the at least one supporter layer (#112a/#112b) includes a first supporter layer in contact with a side surface of an upper region of the first lower electrode (#43a),
an upper surface of the first supporter layer (#112b) and an upper surface of the first lower electrode (#43a) are substantially coplanar with each other, and
a level of an uppermost end of the second lower electrode (#43b) is higher than a level of an upper surface of the first lower electrode (#112b). ([0072-0075])
Regarding Claim 14.
WOO teaches The semiconductor device of claim 13,
WOO further teaches wherein an upper surface of the first lower electrode (#43a) is spaced apart from the dielectric layer by the second lower electrode (#43b).
Regarding Claim 17.
WOO teaches The semiconductor device of claim 13,
WOO further teaches wherein at least a portion of an upper surface of the second lower electrode (#43b) is parallel to an upper surface of the substrate (#102).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over WOO et.al. (US-2021/0384194-A1, hereinafter WOO), and further in view of Kim (US-2002/0008272-A1, hereinafter Kim)
Regarding Claim 11.
WOO teaches The semiconductor device of claim 1,
WOO does not explicitly disclose wherein the first lower electrode and the second lower electrode include different materials.
Kim teaches in Fig. 3F wherein the first lower electrode (#108a) and the second lower electrode (#110a) include different materials.
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify WOO’s semiconductor device with the teachings of Kim, as identified above, in order to independently control the structural stability and surface morphology of different regions of the storage node electrode.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over WOO et.al. (US-2021/0384194-A1, hereinafter WOO), and further in view of Huang et.al. (US-2009/0108319-A1, hereinafter Huang)
Regarding Claim 15.
WOO teaches The semiconductor device of claim 13,
WOO does not explicitly disclose wherein an upper surface of the second lower electrode has a wavy shape.
However, Huang teaches in Fig.9 wherein an upper surface of the second lower electrode (#14’)has a wavy shape. It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify WOO’s semiconductor device with the teachings of Huang, as identified above, in order to increase the effective electrode surface area and thereby increase capacitance.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over WOO et.al. (US-2021/0384194-A1, hereinafter WOO), and further in view of Hong (US-2002/0146882-A1, hereinafter Hong)
Regarding Claim 16.
WOO teaches The semiconductor device of claim 13,
WOO does not explicitly disclose wherein at least a portion of an upper surface of the second lower electrode has a rounded shape.
Hong teaches in Fig.2G wherein at least a portion of an upper surface of the second lower electrode (#9) has a rounded shape. It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify WOO’s semiconductor device with the teachings of Hong, as identified above, because rounded or convex electrode surfaces were known capacitor storage-node geometries and would have predictably provided a manufacturable upper electrode profile while maintaining the capacitor electrode function.
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, the first lower electrode has a recess region extending in a downward direction from a central region of an upper surface of the first lower electrode, the second lower electrode includes a first portion and a second portion, the first portion fills at least a portion of the recess region,
the second portion extends from the first portion, and the second portion covers the upper surface of the first lower electrode. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 4-7 contain allowable subject matter because they depend from claim 3 .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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