DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of March 23, 2026 in the reply filed on March 23, 2026 is acknowledged. In addition to the restriction/election requirement that was mailed on January 23, 2026, a telephone call was made on June 16, 2026 to Joseph Buczynski. This resulted in the election of a species embodiment of Fig. 4 (Claims 1-3, 11-16, and 19 readable thereon, with claims 4-10, 17-18, and 20 identified by applicant as directed to a non-elected embodiment).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arai et al (USPGPUB 20100314712, hereinafter “Arai”).
Regarding Claim 1, Arai teaches (Figs 3A, 3B) a semiconductor device comprising: a substrate (1a) ; and a plurality of cells (Fig. 3A, the device is seen divided into cells side by side on substrate 1a) side by side on the substrate (1a) in a first direction (horizontal direction) , each of the plurality of cells including a bipolar transistor (Fig. 3B, each of the plurality of cells which the device is arranged into, as seen in the plan view of Fig. 3A, is seen including a bipolar transistor) including a collector layer (3a, 3b, 3c), a base layer (4), and an emitter layer (6) sequentially stacked on each other (collector 3a,3b,3c base layer 4, and emitter 6 are seen sequentially stacked on each other from the substrate 1a) from the substrate (1a), at least one emitter electrode (9e2) that is contained in the base layer (4) as viewed from above (as viewed from above, the at least one emitter electrode 9e2 would be seen contained within the base layer 4) and that is electrically connected to (the at least one emitter electrode 9e2 is seen forming a conductive pathways with the emitter layer 6) the emitter layer (6), and a base electrode (9B1) that is contained in (the base electrode 9b1 is seen contained in the base layer 4 when viewed from above) the base layer (4) as viewed from above and that is electrically connected to (base layer 4 and the base electrode 9b1 are seen electrically connected to each other) the base layer (4), wherein the bipolar transistors of the plurality of cells are connected in parallel with each other ([0009], “The invention further intends to provide a technique capable of reducing capacitance relative to a substrate in a case of using a plurality of unit bipolar transistors connected in parallel”) , and among the plurality of cells, breakdown resistance of ([0012], “it is preferred that bipolar transistors are arranged thinly in the central portion and densely in the peripheral portion”; the cells in the central portion, as opposed to the edges, of the device would be structured so as to allow for lower breakdown voltages by increasing capacitance, and decreasing thermal stress on those cells; ) at least one second cell (cells in the central portion of the device array as seen in Figs. 3A, 3B and described in para [0012]) of the plurality of cells, which is other than each of first cells (cells at the edge of the device array as seen in Figs. 3A, 3B) of the plurality of cells each at a respective end of the plurality of cells, is higher than breakdown resistances of the first cells (cells at the edge of the device array as seen in Figs. 3A, 3B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arai as applied to claim 1 above, and further in view of Ramey et al (USPGUPB 20210224454, hereinafter “Ramey”).
Regarding Claim 11, Arai teaches a semiconductor module comprising: the semiconductor device according to Claim 1, but is silent with regards to a module substrate on which the semiconductor device is flip-chip mounted.
Ramey teaches a module substrate on which the semiconductor device is flip-chip mounted ([0074], “pins may be disposed at the perimeter of the chip or at the top and/or bottom surface of the chip. When the pin is not connected to any electronic apparatus outside the chip, the pin is an electrically floating terminal. Examples of pins include … a solder,”; a solder-ball mounting connection would be structurally identical to a device created by flip-chip manufacturing).
It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the mounting method of Ramey into the device of Arai in order to arrive at the expected result of creating a device with the known benefit of improving the connection density and thermal stability over other conventional bonding methods with reasonable expectation of success.
Allowable Subject Matter
Claims 2-3, 12-16, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2, the closest available references, that of Arai, Ramey, and Kurokawa et al (USPGPUB 20190172773, hereinafter “Kurokawa”), alone or in any reasonable combination, fails to teach the limitation, “at least one of a shape of the base electrode of each of the plurality of cells in a plan view and a relative positional relationship between the at least one emitter electrode and the base electrode in a plan view is different for the first cells than for the at least one second cell” (Kurokawa et al, which has not been previously introduced in this action, teaches a device with a non-uniform breakdown resistance, but this is not accomplished by changing the geometry of the base fingers on the BJT array). Claims 12-15, 19 are dependent upon Claim 2.
Regarding Claim 3, the closest available references, that of Arai, Ramey, and Kurokawa, alone or in any reasonable combination, fails to teach the limitation, “regarding the at least one emitter electrode of each of the plurality of cells, two emitter electrodes are positioned in the first direction with a space therebetween, the base finger being sandwiched between the emitter electrodes; and a width of the base finger of the at least one second cell in the first direction is wider than a width of the base finger of each of the first cells in the first direction”. Claim 16 is dependent upon Claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.J.L./Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
Prosecution Insights