DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-8, 11-14, 16-18 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 20220344287 A1, hereinafter Yu‘287).
Regarding independent claim 1, Yu‘287 teaches, “An integrated circuit (100, fig. 1-39; ¶ [0003] - ¶ [0106]) comprising:
a circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) that has a metal stack (54, 56, 108, 110, 104, 124 etc and [0018]) and that includes a majority of logic transistors of the integrated circuit (100); and
one or more additional circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) that have:
one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]), and
a majority of static random access memory (50A/50B/50C) and a majority of analog devices (50A/50B/50C) of the integrated circuit (100)”.
Regarding independent claim 8, Yu‘287 teaches, “A semiconductor device (100, fig. 1-39; ¶ [0003] - ¶ [0106]) comprising:
a circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) that has a metal stack (54, 56, 108, 110, 104, 124 etc and [0018]) and that includes a majority of logic transistors of the integrated circuit (100); and
one or more additional circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) that have:
one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]), and
a majority of static random access memory (50A/50B/50C) and a majority of analog devices (50A/50B/50C) of the integrated circuit (100); and
an additional die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) connected to the one or more additional circuit die”.
Regarding independent claim 14, Yu‘287 teaches, “A method (fig. 1-39; ¶ [0003] - ¶ [0106]) comprising:
providing a circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) that has a metal stack (54, 56, 108, 110, 104, 124 etc and [0018]) and that includes a majority of logic transistors of an integrated circuit (100); and
providing one or more additional circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) that have:
one or more additional metal stacks (54, 56, 108, 110, 104, 124 etc and [0018]) of which at least one is connected to the metal stack (54, 56, 108, 110, 104, 124 etc and [0018]) of the circuit die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]), and
a majority of static random access memory (50A/50B/50C) and a majority of analog devices (50A/50B/50C) of the integrated circuit (100); and
connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die (54, 56, 108, 110, 104, 124 etc and [0018])”.
connecting an additional die (50A/50B/50C, fig. 1; ¶ [0018] - ¶ [0019], 450/160, fig. 21-22, ¶ [0062 - ¶ [0063]]) connected to the one or more additional circuit die”.
Note: Prior art Shimada, Shigeru et al. (US 20030112652 A1) can also be used to reject independent claims 1, 8 and 14.
Regarding claim 5 and 11, Yu‘287 further teaches, “wherein the at least one of the one or more additional metal stacks is connected to the metal stack face to face (defining part of 54, 56, 108, 110, 104, 124 etc as ‘a metal stack’ and the rest as ‘additional metal stacks’)”.
Regarding claim 6, Yu‘287 further teaches, “The integrated circuit of claim 1, wherein the at least one of the one or more additional metal stacks is connected to the metal stack face to back (defining part of 54, 56, 108, 110, 104, 124 etc located at a lower level as ‘a metal stack’ and the rest at a higher level as ‘additional metal stacks’)”.
Regarding claim 7 and 13, Yu‘287 further teaches, “wherein at least one of the one or more additional metal stacks is connected to the metal stack by at least one of: hybrid bonding; through silicon vias; fine pitch micro bumps; or direct bonding (¶ [0018], ¶ [0053] etc).
Regarding claim 16, Yu‘287 further teaches, “The method of claim 14, further comprising: manufacturing the logic transistors included in the circuit die in isolation (112, fig. 1)”.
Regarding claim 17, Yu‘287 further teaches, “The method of claim 14, further comprising: manufacturing the one or more additional circuit die in isolation before connection thereof to the circuit die (fig. 5-6)”.
Regarding claim 18, Yu‘287 further teaches, “The method of claim 14, wherein connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die includes: connecting the at least one of the one or more additional metal stacks to the metal stack face to face (defining part of 54, 56, 108, 110, 104, 124 etc as ‘a metal stack’ and the rest as ‘additional metal stacks’)”.
Regarding claim 21, Yu‘287 further teaches, “The integrated circuit of claim 1, wherein the circuit die corresponds to a primary thermal source of the integrated circuit (mapping the most heat radiating device among 50A/50B/50C/450/160 as the circuit die)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu‘287.
Regarding claims 2, 9 and 15, ‘wherein the circuit die is constructed according to a more advanced technology process compared to the one or more additional circuit die’, the language, term, or phrase "the circuit die is constructed according to a more advanced technology process" is directed towards the process of making a circuit die. It is well settled that "product by process" limitations in claims drawn to structure are directed to the product, per se, no matter how actually made. In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also, In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wethheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al., 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or otherwise. The above case law further makes clear that applicant has the burden of showing that the method language necessarily produces a structural difference. As such, the language "circuit die" only requires a circuit die, which does not distinguish the invention from Yu‘287, who teaches the structure as claimed.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Yu‘287 as applied to claim 1 as above, and further in view of Kalyanasundaram et al. (US 10555436 B1, hereinafter Kalya‘436).
Regarding claim 22, Yu‘287 teaches all the limitations described in claim 1.
But Yu‘287 is silent upon the provision of wherein the additional circuit die further includes a temperature sensor die located in planar proximity to the circuit die.
However, Kalya‘436 an integrated circuit, wherein a temperature sensor die (44, fig. 2) located in planar proximity to the circuit die (26).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yu‘287 and Kalya‘436 to include a temperature sensor die in the integrated circuit according to the teachings of Kalya‘436 for the purpose of in predicting temperatures for one or more regions and taking remedial action to avoid overheating of the device as suggested by Kalya‘436.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yu‘287 as applied to claim 1 as above, and further in view of Arabi et al. (US 20060052970 A1, hereinafter as Arabi'970).
Regarding claim 23, Yu‘287 teaches all the limitations described in claim 1.
But Yu‘287 is silent upon the provision of wherein the additional circuit die is configured to position the circuit die closer than the additional circuit die to a cooling solution of a semiconductor device containing the integrated circuit.
However, Arabi'970 teachers the configuration of a circuit die (Fig. 1, (110); [0014]) for connection configures a circuit die (140; [0015]) for positioning closer than the circuit die to a cooling solution (13 0; [0016]) of a semiconductor device containing the integrated circuit.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yu‘287 and Arabi'970 to include a cooling solution in the integrated circuit according to the teachings of Kalya‘436 in order to ensure long-term product reliability (see Arabi'970, para. [0004]).
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Yu‘287 as applied to claim 1 as above, and further in view of Dubey et al. (US 20200076424 A1, hereinafter Dubey‘424).
Regarding claim 24, Yu‘287 teaches all the limitations described in claim 1.
But Yu‘287 is silent upon the provision of wherein the additional circuit die further includes a backside power delivery network.
However, Dube'424 teaches, a circuit die (160) includes a backside power delivery network (114).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yu‘287 and Dube'424 to include backside power delivery network according to the teachings of Dube'424 to exploit the general advantages of the backside power delivery network e.g., reduced IR drop, freed front-side routing, improved power efficiency etc.
Regarding claim 25, Yu‘287 modified with Dube'424 further teach, “The integrated circuit of claim 24, wherein the additional circuit die (110) delivers power obtained from the backside power delivery network (114) to the circuit die (160) through a metal stack (144, 136, 174 etc.) face to face connection”.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yu‘287 as applied to claim 1 as above, and further in view of Dubey‘424).
Regarding claim 26, Yu‘287 teaches all the limitations described in claim 1.
But Yu‘287 is silent upon the provision of wherein the additional die is configured to receive power directly from a third die by direct bonding of a silicon body of the additional circuit die to the third die.
However, Dube'424 teaches, wherein the additional die (30, fig. 1) is configured to receive power directly from a third die (10) by direct bonding of a silicon body (32) of the additional circuit die (30) to the third die (10).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Yu‘287 and Dube'424 by having a circuit die configured to receive power directly from another die by direct bonding of a silicon body in order to provide power gating for stacked die structures (see ¶ [0003]) as suggested by Dube'424.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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