Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the fee set forth in 37 CFR 1.17(p) on 12/29/25 prompted the new ground(s) of rejection presented in this Office action.
Further regarding claim 1, Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b) and § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Response to Arguments
Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 3-5 are rejected under 35 U.S.C. 112(d), as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends:
Regarding claim 3-5: the claims have improper dependency of claim 2 which has been canceled. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
For examination purposes, the examiner interpreted the dependency of each claim as being dependent on the claim 1, rather than on the claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 7-9, 15, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dubey (US 20200076424; in the IDS on 12/29/25).
Regarding claim 1. (Currently Amended) Fig 3 and Fig 4 (circuit diagram of Fig 3) of Dubey discloses An integrated circuit comprising:
a first circuit die 160 [0043] having a first metal stack 164 [0049]; and
a second circuit die 130 [0043] having a second metal stack 134/136/140 [0046]-[0047] that is connected to the first metal stack of the first circuit die,
wherein at least one metal layer 136 of the second metal stack is utilized by both the first circuit die and the second circuit die as a metal layer interconnect (Fig 3, [0047]).
Regarding claim 4. (Original) Dubey discloses The integrated circuit of claim [[2]] 1 (refer to the above 112(d) rejection for the examiner’s interpretation), wherein at least one metal layer 140 of the second metal stack is utilized exclusively by the first circuit die (Fig 3).
Regarding claim 6. (Original) Dubey discloses The integrated circuit of claim 1, wherein the second metal stack is connected to the first metal stack face to face (Fig 3, [0053]: metal-to-metal direct bonding).
Regarding claim 8. (Original) Dubey discloses The integrated circuit of claim 1, wherein the second metal stack is connected to the first metal stack by at least one of:
hybrid bonding;
through silicon vias;
fine pitch micro bumps; or
direct bonding [0053].
Regarding claim 9. (Currently Amended) Fig 3 and Fig 4 (circuit diagram of Fig 3) of Dubey discloses A semiconductor device comprising:
an integrated circuit that includes:
a first circuit die 160 having a first metal stack 164; and
a second circuit die 130 having a second metal stack 134/136/140 that is connected to the first metal stack of the first circuit die,
wherein at least one metal layer 136 of the second metal stack is utilized to communicate one or more signals from a first transistor layer 168 [0060] of the first circuit die back to the first transistor layer (Fig 3/Fig 4, [0060]); and
an additional die 110 [0053] connected to the second circuit die (Fig 3).
Regarding claim 15. (Currently Amended) Fig 3 and Fig 4 (circuit diagram of Fig 3) of Dubey discloses A method [0055], comprising:
providing a first circuit die 160 having a first metal stack 164;
providing a second circuit die 130 having a second metal stack 134/136/140,
wherein at least one metal layer 136 of the second metal stack is utilized to communicate one or more signals from a first transistor layer 168 [0060] of the first circuit die back to the first transistor layer (Fig 3/Fig 4, [0060]); and
connecting the second metal stack to the first metal stack of the first circuit die [0053].
Regarding claim 18. (Original) Dubey discloses The method of claim 16, wherein at least one metal layer 140 of the second metal stack is utilized exclusively by the first circuit die (Fig 3).
Regarding claim 20. (Original) Dubey discloses The method of claim 16, wherein the second metal stack is connected to the first metal stack at least one of face to face (Fig 3, [0053]: metal-to-metal direct bonding) or face to back.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 7, 10 and 16 are rejected under 35 U.S.C. 103(a) as being unpatentable Dubey (US 20200076424; in the IDS on 12/29/25).
Regarding claim 7. (Original) The embodiment Fig 3 of Dubey discloses The integrated circuit of claim 1. But the embodiment Fig 3 of Dubey does not disclose wherein the second metal stack is connected to the first metal stack face to back.
However, the embodiment Fig 1 of Dubey discloses the second metal stack 34/56 is connected to the first metal stack 54 face to back.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment Fig 3 of Dubey to have to the embodiment Fig 1 of Dubey for the purpose of providing shorter and denser interconnects between stacked dies reduce latency and power consumption for high-speed signals.
Regarding claim 10. (Original) Dubey discloses The semiconductor device of claim 9. But Dubey does not explicitly disclose wherein the first circuit die is constructed according to a more advanced technology process compared to the second circuit die.
However, in a three-semiconductor die stack connected by through-silicon vias (TSV) and direct bonding (or hybrid bonding), the topmost die can absolutely utilize a more advanced, smaller technology process node compared to the lower dies. This approach is a cornerstone of heterogeneous integration and chiplet-based design, which optimizes for performance, cost, and power.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Dubey’s the first circuit die is constructed according to a more advanced technology process compared to the second circuit die.
Regarding claim 16. (Original) Dubey discloses The method of claim 15. But Dubey does not explicitly disclose wherein the first circuit die is constructed according to a more advanced technology process compared to the second circuit die.
However, in a three-semiconductor die stack connected by through-silicon vias (TSV) and direct bonding, the topmost die can absolutely utilize a more advanced, smaller technology process node compared to the lower dies. This approach is a cornerstone of heterogeneous integration and chiplet-based design, which optimizes for performance, cost, and power.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Dubey’s the first circuit die is constructed according to a more advanced technology process compared to the second circuit die.
Allowable Subject Matter
Claims 3 and 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(d), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “at least one redundant metal layer is eliminated from the first metal stack”.
Regarding claim 5. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “at least one metal layer of the second metal stack is utilized to communicate one or more signals from a first transistor layer of the first circuit die back to the first transistor layer without communicating the one or more signals to a second transistor layer of the second circuit die”.
Claims 11-14, 17, 19 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “at least one redundant metal layer is eliminated from the first metal stack”.
Regarding claim 17. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “at least one redundant metal layer is eliminated from the first metal stack”.
Regarding claim 19. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “at least one metal layer of the second metal stack is utilized to communicate one or more signals from a first transistor layer of the first circuit die back to the first transistor layer without communicating the one or more signals to a second transistor layer of the second circuit die”.
Regarding claim 21. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “at least one metal layer of the second metal stack is utilized to communicate one or more signals from a first transistor layer of the first circuit die back to the first transistor layer without communicating the one or more signals to a second transistor layer of the second circuit die”.
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the fee set forth in 37 CFR 1.17(p) on 12/29/25 prompted the new ground(s) of rejection presented in this Office action.
Further regarding claim 1, Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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