Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I directed to claims 1-11 in the reply filed on March 5, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 26 and 27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 26, the heights of the first supports and the slit structure are discussed in paragraphs 21, 26, and 30. However, the disclosure fails to mention the slit structure having a height substantially identical to the first supports. Therefore, the limitation directed to the slit structure having a height substantially identical to the first support must be cancelled from the claims.
Regarding claim 27, the width of the contact structure is discussed in paragraph 25. However, the disclosure fails to mention the contact structing having a greater width at an upper portion than a lower portion. Therefore, the limitation directed to the contact structing having a greater width at an upper portion than a lower portion must be cancelled from the claims.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The term “substantially same” in claim 10 is a relative term which renders the claim indefinite. The term “substantially same” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Therefore, the claim has been rendered indefinite as no parameter has been given that would establish what constitutes a This extends to all claims dependent upon claim 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 8, and 25-30 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Nagashima et al. (Pub. No. US 20230091827 A1), hereinafter referred to as Nagashima.
Regarding claim 1, Nagashima teaches a semiconductor device comprising: a gate structure comprising insulating layers and conductive layers that are alternately stacked (Fig. 4, insulating layer 101, conductive layer 110; ¶104-106); a real channel structure extending through the gate structure (Figs. 3 & 4, semiconductor layer 120; ¶120); a slit structure extending in a first direction along a sidewall of the gate structure (Fig. 2, inter-finger structure insulating layer ST; ¶102); a contact structure extending through the gate structure and that is electrically connected to at least one conductive layer, among the conductive layers (Figs. 3 & 8, contact electrodes CC; ¶120); and a pair of first supports extending in an arc form along a sidewall of the contact structure and that comprises concave and convex parts on sidewalls of the first supports (Figs. 3 & 81, supporting structure HR10, contact electrodes CC; ¶118-128, 284-290).
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Regarding claim 2, Nagashima further teaches the pair of first supports having a symmetrical form (Fig. 81, supporting structure HR10; ¶284-290).
Regarding claim 3, Nagashima further teaches second supports extending through the gate structure, each second support having a pillar form, wherein the second supports are arranged in the first direction and a second direction intersecting the first direction (Fig. 3, supporting structure HR; ¶119-120).
Regarding claim 7, Nagashima further teaches the gate structure comprising a cell region and a contact region (Figs. 3 & 4, memory hole region RMH, hook-up region RHU; ¶103-130); the real channel structure is disposed in the cell region (Figs 3 & 4, memory hole region R_MH, semiconductor layer 120; ¶103-130); and at least one of the pairs of the first supports and the contact structure is disposed in the contact region (Figs. 3 & 81, hook- up region R_HU, supporting structure HR10, contact electrodes CC; ¶103-130, 284-290).
Regarding claim 8, Nagashima further teaches the slit structure having a line form extending from the cell region to the contact region (Figs. 2 & 3, inter-finger structure insulating layer ST, memory hole region R_MH, hook-up region R_HU; ¶102-103).
Regarding claim 25, Nagashima further teaches each of the pair of first supports comprises a plurality of connected pillars having curved sidewalls (Fig. 81, supporting structure HR10, circles C2, circle C3; ¶284-290).
Regarding claim 26, Nagashima further teaches the pair of first supports has a height substantially identical to a height of the slit structure (Figs. 33 & 34, supporting structure HR, inter-finger insulating structure ST; ¶137, 158-165).
Regarding claim 27, Nagashima further teaches the contact structure having a greater width at an upper portion than a lower portion (Fig. 8, contact electrode CC, diameter D107H, diameter D107L; ¶130-134).
Regarding claim 28, Nagashima further teaches the gate structure comprising a plane center region and a plane edge region, and wherein the slit structure is disposed in the plane center region (Figs. 2 & 3, memory hole region R_MH, hook-up region R_HU, inter-finger structure insulating layer ST, finger structure FS; ¶102-103).
Regarding claim 29, Nagashima further teaches a separation structure disposed in the plane edge region, extending to the plane center region, and connected to the slit structure in the first direction (Figs. 2 & 3, memory hole region R_MH, hook-up region R_HU, inter-finger structure insulating layer ST, finger structure FS; ¶102-103).
Regarding claim 30, Nagashima further teaches the slit structure protrudes into the separation structure (Figs. 2 & 3, inter-finger structure insulating layer ST; ¶102).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagashima as applied to claim 1 above, and further in view of Park et al. (Pub. No. US 20220020686), hereinafter referred to as Park.
Regarding claim 4, Nagashima further teaches a separation structure disposed in a plane edge region and connected to the slit structure in the first direction (Figs. 2 & 3, memory hole region R_MH, hook-up region R_HU, inter-finger structure insulating layer ST, finger structure FS; ¶102-103). However, Nagashima doesn’t teach a dummy channel structure extending through the gate structure and disposed between a pair of separation structures that are adjacent to each other in a second direction intersecting the first direction.
Park teaches teach a dummy channel structure extending through the gate structure and disposed between a pair of separation structures that are adjacent to each other in a second direction intersecting the first direction (Fig. 6, SLIT, dummy plug; ¶57).
Nagashima and Park are analogous are as they are in the same field of endeavor of semiconductor memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nagashima to incorporate the teachings of Park to have a dummy channel structure extending through the gate structure and disposed between a pair of separation structures that are adjacent to each other in a second direction intersecting the first direction. For the purpose of maintaining structural integrity of the stack during fabrication and to maintain uniform etching and deposition.
Regarding claim 9, Nagashima further teaches the pairs of the first supports have a height substantially identical with a height of the separation structure (Figs. 33 & 34, supporting structure HR, inter-finger insulating structure ST; ¶137, 158-165).
Regarding claim 10, Nagashima further teaches the pairs of first supports comprises first supports comprising a material same or substantially same with a material of the separation structure (supporting structure HR, inter-finger insulating structure ST; ¶102, 137).
Regarding claim 11, Nagashima further teaches the first supports comprising an oxide (supporting structure HR; ¶137).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagashima in view of Park as applied to claim 4 above, and further in view of Luo et al. (Pub. No. US 20240379787 A1), hereinafter referred to as Luo.
Regarding claim 5, Nagashima in view of Park does not teach each of the separation structures comprising concave and convex parts on sidewalls.
Luo teaches each of the separation structures comprising concave and convex parts on sidewalls (Figs. 1 & 25, gate line slit trench 101, gate line isolation structure 102; ¶20-23 & ¶155-157).
Nagashima, Park, and Luo are all analogous art as they are in the same field of endeavor of semiconductor memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nagashima in view of Park to incorporate the teachings of Luo to have the separation structures comprise concave and convex parts on the sidewalls. For the purpose of reducing the internal stresses on the separation structures which reduces the chance of deformation and improves stability, as recognized by Luo.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagashima as applied to claim 1 above, and further in view of Luo.
Regarding claim 6, Nagashima does not teach the slit structure comprising concave and convex parts on sidewalls.
Luo teaches the slit structure comprising concave and convex parts on sidewalls (Figs. 1 & 25, gate line slit trench 101, gate line isolation structure 102; ¶20-23 and ¶155-157).
Nagashima and Luo are analogous art as they are in the same field of endeavor of semiconductor memory devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nagashima to incorporate the teachings of Luo so that the slit structure comprises concave and convex parts on the sidewalls. For the purpose of keeping fabrications costs of the device low and to prevent yield loss caused by tilting between the channel structures and the gate isolating structures, as recognized by Luo.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Otsu (Pub. No. US 20230013984 A1), Iwai et al. (US Patent No. 10,879,262), and Yoshida (US Patent No. 11,450,685).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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