DETAILED ACTION
This action is responsive to the reply filed August 30, 2025. Claims 1-20 are pending. Claims 1 and 11 have been amended. Claims 2 and 12 have been cancelled. Thus, upon entry of this amendment, claims 1, 3-11, and 13-20 are presently pending. Claims 1, and 11 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment to the specification regarding the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Memory erase method claims 1, 3-8, and 10, and similarly memory device claims 11, 13-18, and 20, are rejected under 35 U.S.C. 103 as being unpatentable over Zalivaka et al. (US 20230045933; “Zalivaka” – of Record) in view of Goda (“Recent Progress on 3D NAND Flash Technologies” – of Record) and further in view of Yoo et al. (“First Demonstration of 1-bit Erase in Vertical NAND Flash Memory”, “Yoo” – of Record) and further in view of Che et al. (“A Non-Volatile Memory Based Physically Unclonable Function without Helper Data”; “Che” – of Record) as supported by Wikipedia article (“Physical unclonable function” – of Record). Except for being drafted in apparatus format and reciting required circuitry also taught by the references, the memory device claims are otherwise identical in subject matter to the erase method claims and because the applied references also teach the required claimed circuitry, the memory device claims are rejected for the same reasons as the method claims. Furthermore, the manner of operating a device does not patentably distinguish the apparatus claims from the prior art apparatus. MPEP 2114(II).
Regarding independent claims 1 and 11, Zalivaka discloses a memory erase method for a memory device, comprising:
providing a memory block, wherein the memory block comprises a plurality of memory cell strings including a plurality of memory cells (Fig.3: 211 memory block, 221 memory strings, MCn memory cells), a plurality of string selection transistors (Fig. 3: DST), and a plurality of ground selection transistors (Fig. 3: SST), wherein each of the plurality of memory cell strings includes a string selection transistor (Fig. 3: DST), multiple memory cells among the plurality of memory cells and a ground selection transistor are connected in series (Fig. 3), each memory cell string coupled to a corresponding bit line through a corresponding string selection transistor (Fig. 3: BL0-BLm), and coupled to a common source line through a corresponding ground selection transistor (Fig. 3: CSL), the multiple of memory cells connected to a plurality of corresponding word lines (Fig. 3: WL0-WLn);
Zalivaka is silent with respect to specific GIDL erase voltages to induce a distribution of erase threshold voltages, where that distribution consists of type-1 or type-2 erase bits.
PNG
media_image1.png
980
1500
media_image1.png
Greyscale
However, Goda teaches applying a word line erase voltage to the plurality of corresponding word lines of each of the plurality of memory cell strings (Fig. 3(b));
applying a common source line erase voltage to the common source line (Fig. 3(b));
applying a bit line erase voltage to a corresponding bit line of each of the plurality of memory cell strings (Fig. 3(b));
applying a string selection line erase voltage to the string selection transistor of each of the plurality of memory cell strings (Fig. 3(b)), and
applying a ground selection line erase voltage to the ground selection transistor of each of the plurality of memory cell strings (Fig. 3(b)),
wherein a voltage difference between the bit line erase voltage and the string selection line erase voltage or a voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference (Fig. 3(b)).
Goda is silent with respect to a distribution of erase threshold voltages, where that distribution consists of type-1 or type-2 erase bits.
PNG
media_image2.png
1010
1098
media_image2.png
Greyscale
However, Yoo teaches the plurality of memory cells of the plurality of memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit (Fig. 3. See also col. 1 where it states: "VGIDL (= VBL-VDSL or VSL-VSSL)" which is the same voltage differential indicated in the instant application).
While Zalivaka, discloses physically unclonable functions (PUF) within memory, Zalivaka, Goda, and Yoo combined are silent with respect to specifically using a two group physically unique distribution of characteristics for generating PUF data.
However, Che teaches further comprising: correspondingly generating physically unclonable function (PUF) data according to the plurality of memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of memory cell strings (col. 1; "we propose a non-volatile memory based (NVM) PUF", "the methodology is applicable to any type of NVM including Flash". See also Fig. 1 where it illustrates the concept of an NVM PUF by using the two-group random distribution of a physical property (resistance in this example). It is further noted that “PUFs are often based on unique physical variations occurring naturally during semiconductor manufacturing” (Wikipedia article: Physical unclonable function), and it is well understood in the art that gate overhang and drain doping profiles which generate either fast GIDL erase or slow GIDL erase cells within a random distribution as described in the instant application are necessarily a common physical variation seen in semiconductor manufacturing).
Zalivaka, Goda, Yoo and Che are from the same field of endeavor as applicant’s invention directed to uses for distributions of inherent variations in the manufacturing of memory circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zalivaka’s generation of physically unclonable functions with the teachings of Goda’s GIDL erase method and with the teachings of Yoo’s resultant erase threshold voltage distributions to generate physically unclonable function data with the standard 3D NAND circuits and further with Che’s use of GIDL to create two-groups of random distributions of a physical property in PUFs. Doing so would improve data security within memory arrays at low cost compared to other methods.
Regarding claims 3 and 13, Zalivaka, Goda, Yoo, and Che combined disclose the limitations of claim 1.
As applied, Goda further discloses wherein a gate induced drain leakage (GIDL) erasing operation is performed on the plurality of memory cells of the plurality of memory cell strings (Fig. 3(b). It is noted that this limitation appears to be directed to Fig. 2 in the instant application which is remarkably similar in all respects to Goda's Fig. 3(b)).
Regarding claims 4 and 14, Zalivaka, Goda, Yoo, and Che combined disclose the limitations of claim 3.
As applied, Yoo further discloses wherein, after the gate induced drain leakage current erasing operation, all of the multiple memory cells in a specific memory cell string are the type-1 erase bit, or all of the multiple memory cells in a specific memory cell string are the type-2 erase bit (Fig. 3. See also col. 1 where it states: "VGIDL (= VBL-VDSL or VSL-VSSL)" which is the same voltage differential indicated in the instant application. It is noted that the terms "type-1 erase" and "type-2 erase" are defined in the instant application as merely the distribution of a strong or weak erase characteristic which is analogous to Yoo's illustrated distribution in Fig. 3 and therefore all cells would necessarily be within this distribution after GIDL erase).
Regarding claims 5 and 15, Zalivaka, Goda, Yoo and Che combined disclose the limitations of claim 1.
As applied Zalivaka further discloses further comprising: classifying the plurality of memory cells into the type-1 erase bit or the type-2 erase bit according to a threshold voltage of the memory cells (Fig. 5. See also para. 62; "the system 500 may generate unique and unpredictable keys or identifiers using a physical unclonable function (PUF)". See also para 59; "There are many types of PUFs", "which are based on different physical characteristics of ICs (e.g., delay differences, frequencies, threshold voltages, initial memory states, etc)". It is further noted that Zalivaka's selection and comparison component correspond to the controller 100 of Fig. 1-5 (para 65) and are analogous to the memory controller 110 in the instant application. It is well understood in the art that all NAND memory controllers perform an erase verify operation to classify the threshold erase voltage level of memory cells in the array).
Regarding claims 7 and 17, Zalivaka, Goda, Yoo and Che combined disclose the limitations of claim 1.
As applied, Goda further discloses wherein the predetermined voltage difference ranges from 0 volts to 5 volts (Fig. 3 where it illustrates a 5V GIDL voltage difference).
Regarding claims 8 and 18, Zalivaka, Goda, Yoo and Che combined disclose the limitations of claim 1.
As applied, Zalivaka further discloses further comprising:
programming the plurality of memory cells in the memory block before randomly classifying the plurality of memory cells in the plurality of memory cell strings into the type-1 erase bit or the type-2 erase bit (para. 43; " The peripheral circuit may perform a program, read, or erase operation on the memory cell array 210". It is well understood in the art that a nonvolatile memory cell must first be programmed before it can be erased in order to generate the distribution of erase threshold voltage characteristics).
Regarding claims 10 and 20, Zalivaka, Goda, Yoo and Che combined disclose the limitations of claim 1.
As applied, Goda further discloses wherein the word line erase voltage is 0V, the common source line erase voltage is 20V, and the bit line erase voltage is 20V (Fig. 3)
Regarding claims 6 and 16, Zalivaka, Goda, Yoo and Che combined disclose the limitations of claim 5.
As applied, Che further discloses further comprising: not using unclassifiable memory cells in a condition where the plurality of memory cells cannot be classified as the type-1 erase bit or the type-2 erase bit by using the threshold voltage of the memory cells (pg. 148, col. 2: “A distribution is then constructed using these digital values and a median-finding algorithm is used to partition the population into two segments (with an equal number of elements in each segment). NVM cells with digital values in the lower half of the distribution are programmed with a '0' while those in the upper portion are programmed with a '1’”. It is noted that Che’s “programming” of cells is analogous to the generating PUF data in the instant application and would apparently be “implemented (somehow) by the memory controller or corresponding hardware” (Spec. para. 23) but no specific mechanism has been defined in the instant application. Che further explains: (pg. 153, col. 2; “The large margin that typically exists between the LRS and HRS distributions enables the bitstring to be reliably regenerated”)
Memory erase method claim 9, as well as memory device claim 19, are rejected under 35 U.S.C. 103 as being unpatentable over Zalivaka et al. (US 20230045933; “Zalivaka” – of Record) in view of Goda (“Recent Progress on 3D NAND Flash Technologies” – of Record) and further in view of Yoo et al. (“First Demonstration of 1-bit Erase in Vertical NAND Flash Memory”, “Yoo” – of Record) and further in view of Che et al. (“A Non-Volatile Memory Based Physically Unclonable Function without Helper Data”; “Che” – of Record) as supported by Wikipedia article (“Physical unclonable function” – of Record) and further in view of Melik-Martirosian (US 20120239858 – of Record). Except for being drafted in apparatus format and reciting required circuitry also taught by the references, the memory device claims are otherwise identical in subject matter to the erase method claims and because the applied references also teach the required claimed circuitry, the memory device claims are rejected for the same reasons as the method claims. Furthermore, the manner of operating a device does not patentably distinguish the apparatus claims from the prior art apparatus. MPEP 2114(II).
Regarding claims 9 and 19, Zalivaka, Goda, Yoo and Che combined disclose the limitations of claim 1.
As applied, Zalivaka further disclose wherein one page in the memory block is constructed by the plurality of memory cells which are connected with one of the corresponding word lines in the plurality of memory cell strings (Fig. 3 where it illustrates the bit lines of a row of memory cells connected with a single word line (WL0 for example), connected to the page buffer array250. It is well known in the art that this row topology of NAND memory array comprises a page), and
the memory erase method further comprises: programming all of the plurality of memory cells in a specific page of the plurality of pages before randomly classifying the plurality of memory cells in the plurality of memory cell strings into the type-1 erase bit or the type-2 erase bit (para. 43; " The peripheral circuit may perform a program, read, or erase operation on the memory cell array 210". It is well understood in the art that a nonvolatile memory cell must first be programmed before it can be erased in order to generate the distribution demonstrating erase threshold voltage characteristics);
Zalivaka, Goda, Yoo and Che combined are silent with respect to program-erase cycles.
However, Melik-Martirosian teaches determining whether a programming-erasing count of the specific page exceeds a wear threshold (para. 43; "The one or more lookup tables may provide trigger information based on a number of P/E cycles"); and
using another page of the plurality of pages as the specific page when the programming-erasing count of the specific page exceeds the wear threshold (para. 43; "Once a trigger event is met (for example", "EOL"), controller 101 accesses the one or more parameter lookup tables to facilitate adjustment of the ISPP and/or ISPE parameters", "adjustment can be performed", "on individual blocks, or on individual pages". It is noted that the terms "EOL" stands for "end of life", and the erase adjustment for end of life of a page would necessarily be that another page would need to be used).
Zalivaka, Goda, Yoo, Che and Melik-Martirosian are from the same field of endeavor as applicant’s invention directed to non-volatile memory circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zalivaka, Goda, and Yoo combined with the teachings of Melik-Martirosian’s program-erase wear cycle adjustments to preclude using pages which are end of life. Doing so would help ensure that the generated PUF data remain reliable and reproducible.
Response to Arguments
Applicant's arguments filed August 30, 2025, have been fully considered but they are not persuasive.
Applicant contends on pg. 13 of Remarks that the obviousness rejection of claim 1 is improper because the combination of references (Zalivaka, Goda, and Yoo) fail to disclose the feature of “correspondingly generating physically unclonable function (PUF) data according to the plurality of memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of memory cell strings”.
To support their argument, applicant asserts various passages and features taught by Zalivaka, Goda, and Yoo that differ from the claimed subject matter in the following ways:
Zalivaka is silent with respect to GIDL induced type-1 or type-2 erase bits.
Goda is silent with respect to “performing the GIDL erase method below the 5V (0V-5V).”
Yoo does not contextualize GIDL technology in PUF generation of the memory device and that Yoo is silent with respect to “erase type-1 grouping” and “erase type-2 grouping”
First, it is stipulated that Zalivaka, as applied, does not read on “type-1” or “type-2” erase bits. However, it is noted that the Zalivaka reference was only applied to the physical structure elements of claim 1, not to the methods of operating the device.
Regarding Goda, it appears that this argument is directed to the limitation of “wherein a voltage difference between the bit line erase voltage and the string selection line erase voltage or a voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference” as recited in claim 1. It is noted that the claim states “less than or equal” and that as illustrated in “Examiner’s Markup Goda Fig. 3” of pg. 4 of the office action, the voltage difference is 5V which is within the range indicated in applicant’s specification (para. 26).
Regarding Yoo, while the term “type-1” or “type-2” is not used by Yoo explicitly, the threshold voltage variation due to the GIDL effect is clearly shown in “Examiner’s Markup Yoo” of pg. 5 of the office action demonstrating the analogous concept as “type-1” (strong erase characteristic), and “type-2” (weak erase characteristic) as in the instant application (para. 21, and Fig. 3). As such, while it is agreed that Yoo does not explicitly discuss PUFs, Yoo clearly demonstrates of the feature of the random distributions of threshold voltages due to the GIDL effect needed for application in PUFs which are taught in combination with the other applied references.
Moreover, this limitation (“correspondingly generating physically unclonable function (PUF) data according to the plurality of memory cells randomly classified into the type-1 erase bit or the type-2 erase bit in the plurality of memory cell strings.”) was originally presented in rejected dependent claim 2 and has presently been incorporated in its entirety into amended independent claim 1. The reference specifically applied for the obviousness rejection of this feature previously (and as it is presented currently) is Che in combination with the other references of original claim 1. No argument was presented in the reply regarding previous claim 2 and thus, no error in the action for this feature is distinctly and specifically pointed out, nor how the applicant’s invention is distinguished from Che.
Lastly, applicant contends on pg. 15 of remarks that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). In this case, the effect of random distribution of threshold voltages using the GIDL effect, and the use of Physically Unclonable Functions for security is well understood in the memory arts and was known at the time of the claimed invention and as evinced by the applied prior art.
In summation, applicant’s other arguments with regard to this feature, while not persuasive on their merits as outlined above, also do not overcome the applied art of the current rejection. For at least these reasons, all rejections are deemed proper and maintained.
Conclusion
Although the prior art applied is the same, to the extent new facts of the applied prior art were applied creating a new ground of rejection, applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James S Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825