Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species I, Sub-species A, claims 1-11 in the reply filed on 02/12/2026 is acknowledged. The traversal is on the ground(s) that Inventions I and II are not independent or distinct as the amended method claims 12-20 cannot be used to make a materially different product. Also that there is no search or examination burden. This is not found persuasive because Inventions I and II are distinct as the amended method claims 12-20 can be used to make a materially different product. For example the method can be used to make a device that doesn't require that the one of the plurality of dummy transistors is adjacent to the one of the plurality of first transistors in the same oxide diffusion region, both the one of the plurality of dummy transistors and the one of the plurality of first transistors have the same effective gate widths and the same first gate lengths; and in the situation that the one of the plurality of dummy transistors is adjacent to the one of the plurality of second transistors in the same oxide diffusion region, both the one of the plurality of dummy transistors and the one of the plurality of second transistors have the same effective gate widths and the same second gate lengths. Another example is that the method could be used to make a device that doesn't require that the plurality of first transistors and the plurality of second transistors are N-type transistors, the source terminals of the plurality of first transistors are coupled to a ground line, the drain terminals of the plurality of second transistors of the plurality of first voltage-to-current converters are coupled to one of a plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of second voltage-to-current converters are coupled to another one of the plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of third voltage-to-current converters are coupled to yet another one of the plurality of current lines; and in a situation that the plurality of first transistors and the plurality of second transistors are P-type transistors, the source terminals of the plurality of first transistors are coupled to a power line, the drain terminals of the plurality of second transistors of the plurality of first voltage-to-current converters are coupled to the one of a plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of second voltage-to-current converters are coupled to the another one of the plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of third voltage-to-current converters are coupled to yet another one of the plurality of current lines. Also, there exists a search or examination burden as the inventions are classified under separate CPCs and would therefore require a different field of search.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen et al. (Pub. No. EP 1260015 B1), hereinafter referred to as Nguyen, in view of Bhattacharya et al. ("Multilevel Symmetry-Constraint Generation for Retargeting Large Analog Layouts"), hereinafter referred to as Bhattacharya, and in further view of Gruber et al. (Pub. No. US 20060028248 A1), hereinafter referred to as Gruber.
Regarding claim 1, Nguyen teaches a semiconductor device comprising a substrate, comprising six layout regions, wherein the six layout regions are arranged as an array having a plurality of columns and a plurality of rows (Fig. 7c, first differential pair of transistors 8037, second differential pair of transistors 8039, third differential pair of transistors 8041, fourth differential pair of transistors 8043, fifth differential pair of transistors 8045, sixth differential pair of transistors 8047; ¶81). However, Nguyen doesn’t explicitly teach the array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array; two first voltage-to-current converters, respectively arranged in two of the six layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; two second voltage-to-current converters, respectively arranged in another two of the six layout regions, wherein layouts of the two second voltage-to- current converters on the substrate are point-symmetrical with respect to the array center point; and two third voltage-to-current converters, respectively arranged in the other two of the six layout regions, wherein along the direction of the first axis, the two third voltage-to-current converters are between the two first voltage-to-current converters and the two second voltage-to-current converters, and layouts of the two third voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Bhattacharya teaches a semiconductor device comprising layout regions arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line- symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array (Fig. 9, Pg. 945-950).
Nguyen and Bhattacharya are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nguyen to incorporate the teachings of Bhattacharya to have the six layout regions be symmetric using a common-centroid layout. For the purpose of reducing variation in the output of the device.
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However, Nguyen in view of Bhattacharya still does not explicitly teach two first voltage-to-current converters, respectively arranged in two of the six layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; two second voltage-to-current converters, respectively arranged in another two of the six layout regions, wherein layouts of the two second voltage-to- current converters on the substrate are point-symmetrical with respect to the array center point; and two third voltage-to-current converters, respectively arranged in the other two of the six layout regions, wherein along the direction of the first axis, the two third voltage-to-current converters are between the two first voltage-to-current converters and the two second voltage-to-current converters, and layouts of the two third voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Gruber teaches two first voltage-to-current converters and two second voltage-to-current converters, wherein it is important to have good matching between components for optimal operation of the device (Figs. 1 & 2, first voltage-to-current converter 1, second voltage-to-current converter 2; ¶8-12 & ¶30-45).
Nguyen, Bhattacharya, and Gruber are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the layout of Nguyen in view of Bhattacharya to incorporate the voltage-to-current converters of Gruber to have six layout regions, wherein the six layout regions are arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line- symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array; two first voltage-to-current converters, respectively arranged in two of the six layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; two second voltage-to-current converters, respectively arranged in another two of the six layout regions, wherein layouts of the two second voltage-to- current converters on the substrate are point-symmetrical with respect to the array center point; and two third voltage-to-current converters, respectively arranged in the other two of the six layout regions, wherein along the direction of the first axis, the two third voltage-to-current converters are between the two first voltage-to-current converters and the two second voltage-to-current converters, and layouts of the two third voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point. For the purpose of reducing variation in the output of the voltage-to-current converters to improve the functioning of the device.
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Regarding claim 2, Gruber further teaches the two first voltage-to-current converters comprise a plurality of first sub-converters, the two second voltage-to-current converters comprise a plurality of second sub-converters; layouts of plurality of first sub-converters of one of the two first voltage-to- current converters are point-symmetrical to layouts of plurality of first sub-converters of the other one of the two first voltage-to-current converters with respect to the array center point, and ones of the plurality of first sub-converters synchronously enabled are point-symmetrical; and layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical (Fig. 2, transistors MP1 through MP8; ¶39-45).
Nguyen, Bhattacharya, and Gruber are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the layout of Nguyen in view of Bhattacharya to incorporate the sub-converters of Gruber such that the two first voltage-to-current converters comprise a plurality of first sub- converters, the two second voltage-to-current converters comprise a plurality of second sub-converters, and the two third voltage-to-current converters comprise a plurality of third sub-converters; layouts of plurality of first sub-converters of one of the two first voltage-to-current converters are point-symmetrical to layouts of plurality of first sub- converters of the other one of the two first voltage-to-current converters with respect to the array center point, and ones of the plurality of first sub-converters synchronously enabled are point-symmetrical; layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical; and layouts of plurality of third sub-converters of one of the two third voltage-to-current converters are point-symmetrical to layouts of plurality of third sub-converters of the other one of the two third voltage-to-current converters with respect to the array center point, and ones of the plurality of third sub-converters synchronously enabled are point-symmetrical. For the purpose of reducing variation in the output of the voltage-to-current converters and their sub-converters in order to improve the functioning of the device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Bhattacharya and Gruber as applied to claim 2 above, and further in view of Aggarwal (US Patent No. 7,307,294).
Regarding claim 3, Nguyen in view of Bhattacharya and Gruber does not explicitly teach each of the plurality of first sub-converters, each of the plurality of second sub-converters and each of the plurality of third sub-converters comprising a first transistor and a second transistor; the plurality of first transistors of the plurality of first sub-converters, the plurality of second sub-converters and the plurality of third sub-converters having first gate lengths that are the same; the plurality of second transistors of the plurality of first sub-converters, the plurality of second sub-converters and the plurality of third sub-converters having second gate lengths that are the same, wherein the first gate lengths are greater than or equal to the second gate lengths; and the plurality of first transistors and the plurality of second transistors having effective gate widths that are the same.
Aggarwal teaches dividing a first transistors into two sub-transistors and a second transistor into two sub-transistors (Fig. 8, transistor M1, transistor M2, sub-transistors MS11, MS12, MS21, MS22; Col. 1, lines 6-44). Aggarwal further teaches the first sub-transistors and the second sub-transistors having gate lengths that are the same and having effective gate widths that are the same (gate width W, gate length L; Col. 7, line 1 – Col. 8, line 40).
Nguyen, Bhattacharya, Gruber, and Aggarwal are all analogous art as they are in the same field of endeavor of semiconductor devise. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nguyen in view of Bhattacharya and Gruber to incorporate the teachings of Aggarwal’s sub-transistors such that each of the plurality of first sub-converters, each of the plurality of second sub-converters and each of the plurality of third sub-converters comprising a first transistor and a second transistor; the plurality of first transistors of the plurality of first sub-converters, the plurality of second sub-converters and the plurality of third sub-converters having first gate lengths that are the same; the plurality of second transistors of the plurality of first sub-converters, the plurality of second sub-converters and the plurality of third sub-converters having second gate lengths that are the same, wherein the first gate lengths are greater than or equal to the second gate lengths; and the plurality of first transistors and the plurality of second transistors having effective gate widths that are the same. For the purpose of having a layout configuration that allows good matching of transistors without requiring a large pattern area, as recognized by Aggarwal.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Bhattacharya, Gruber, and Aggarwal as applied to claim 3 above, and further in view of Aruga et al. (Pub. No. US 20130140642 A1), hereinafter referred to as Aruga.
Regarding claim 4, Nguyen in view of Bhattacharya, Gruber, and Aggarwal do not explicitly teach a plurality of oxide diffusion regions, arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with three of the six layout regions, another two of the plurality of oxide diffusion regions overlay with the other three of the six layout regions, wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters, a part of the plurality of second sub-converters and a part of the plurality of third sub-converters.
Aruga teaches a plurality of oxide diffusion regions, arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with two of the four layout regions, another two of the plurality of oxide diffusion regions overlay with the other two of the four layout regions, wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters and a part of the plurality of second sub-converters (Fig. 1, PREG1, NREG1; ¶4, 66-72).
Nguyen, Bhattacharya, Gruber, Aggarwal, and Aruga are all in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the layout of Nguyen in view of Bhattacharya, Gruber, and Aggarwal to incorporate the oxide diffusion regions of Aruga such that a plurality of oxide diffusion regions, arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with three of the six layout regions, another two of the plurality of oxide diffusion regions overlay with the other three of the six layout regions, wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters, a part of the plurality of second sub-converters and a part of the plurality of third sub-converters. For the purpose of having on oxide diffusion region with a six region layout.
Regarding claim 5, Nguyen in view of Bhattacharya, Gruber, and Aggarwal doesn’t explicitly teach a plurality of oxide diffusion regions, arranged on the substrate in parallel to the first axis, wherein three of the plurality of oxide diffusion regions overlay with three of the six layout regions, another three of the plurality of oxide diffusion regions overlay with the other three of the six layout regions, wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters, a part of the plurality of second sub-converters and a part of the plurality of third sub- converters.
Aruga teaches a plurality of oxide diffusion regions, arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with two of the four layout regions, another two of the plurality of oxide diffusion regions overlay with the other two of the four layout regions, wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters and a part of the plurality of second sub-converters (Fig. 1, PREG1, NREG1; ¶4, 66-72).
Nguyen, Bhattacharya, Gruber, Aggarwal, and Aruga are all in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the layout of Nguyen in view of Bhattacharya, Gruber, and Aggarwal to incorporate the oxide diffusion regions of Aruga such that a plurality of oxide diffusion regions, arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with three of the six layout regions, another two of the plurality of oxide diffusion regions overlay with the other three of the six layout regions, wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters, a part of the plurality of second sub-converters and a part of the plurality of third sub-converters. For the purpose of having on oxide diffusion region with a six region layout.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Bhattacharya, Gruber, Aggarwal, and Aruga as applied to claim 4 above, and further in view of Loh et al. (US Patent No. 5,627,732), hereinafter referred to as Loh.
Regarding claim 6, Aruga teaches each of the plurality of first transistors and each of the plurality of second transistors comprising a source terminal and a drain terminal, the first transistors and the second transistors being arranged on the same oxide diffusion region (Fig. 1, PREG1, NREG1, SOURCE, DRAIN; ¶4, 66-72); and the drain terminals of two of the plurality of second transistors are coupled to each other (Fig. 2; ¶11). However, Nguyen in view of Bhattacharya, Gruber, Aggarwal, and Aruga does not explicitly teach the drain terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of second transistors; the source terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of first transistors.
Loh teaches the collector terminal of each of the plurality of first transistors is coupled to the emitter terminal of an adjacent one of the plurality of second transistors; the emitter terminal of each of the plurality of first transistors is coupled to the emitter terminal of an adjacent one of the plurality of first transistors (Fig. 3, first transistors T1, T2, T3, second transistors T4, T5, T6; Col. 2, line 55 – Col. 3, line 13).
Nguyen, Bhattacharya, Gruber, Aggarwal, Aruga, and Loh are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nguyen in view of Bhattacharya, Gruber, Aggarwal, and Aruga to incorporate the connections of Loh such that each of the plurality of first transistors and each of the plurality of second transistors comprise a source terminal and a drain terminal; the drain terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of second transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of second transistors; the source terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of first transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of first transistors; and the drain terminals of two of the plurality of second transistors, that are adjacent to each other and arranged on the same oxide diffusion region, are coupled to each other. For the purpose of saving area and having better integration density.
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Bhattacharya, Gruber, Aggarwal, Aruga, and Loh as applied to claim 6 above, and further in view of Horng et al. (Pub No. US 20230178605 A1), hereinafter referred to as Horng.
Regarding claim 7, Bhattacharya teaches having a plurality of dummy transistors arranged on the substrate (Fig. 10; Pg. 950). However, Nguyen in view of Bhattacharya, Gruber, Aggarwal, Aruga, and Loh does not explicitly teach each of the plurality of dummy transistors comprising a source terminal and a drain terminal, wherein in a situation that one of the plurality of dummy transistors is adjacent to one of the plurality of first transistors in the same oxide diffusion region, the source terminal of the one of the plurality of dummy transistors is coupled to the source terminal of the one of the plurality of first transistors; and wherein in a situation that the one of the plurality of dummy transistors is adjacent to one of the plurality of second transistors in the same oxide diffusion region, the drain terminal of the one of the plurality of dummy transistors is coupled to the drain terminal of the one of the plurality of second transistors.
Horng teaches a dummy transistor arranged on the substrate, the dummy transistor comprising a source terminal and a drain terminal, wherein in a situation the dummy transistor is adjacent to one of the plurality of first transistors in the same oxide diffusion region, the source terminal of the dummy transistor is coupled to the source terminal of the one of the plurality of first transistors; and wherein in a situation that the dummy transistors is adjacent to one of the plurality of second transistors in the same oxide diffusion region, the drain terminal of the dummy transistors is coupled to the drain terminal of the one of the plurality of second transistors (Fig. 17a, transistors 612a-612d, transistors 616a-616c, dummy transistor 614 ;¶153-155).
Nguyen, Bhattacharya, Gruber, Aggarwal, Aruga, Loh, and Horng are all analogous art as they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the dummy transistors of Nguyen in view of Bhattacharya, Gruber, Aggarwal, Aruga, and Loh with the dummy transistor of Horng such that there are a plurality of dummy transistors arranged on the substrate, each of the plurality of dummy transistors comprises a source terminal and a drain terminal, wherein in a situation that one of the plurality of dummy transistors is adjacent to one of the plurality of first transistors in the same oxide diffusion region, the source terminal of the one of the plurality of dummy transistors is coupled to the source terminal of the one of the plurality of first transistors; and wherein in a situation that the one of the plurality of dummy transistors is adjacent to one of the plurality of second transistors in the same oxide diffusion region, the drain terminal of the one of the plurality of dummy transistors is coupled to the drain terminal of the one of the plurality of second transistors. For the purpose of improving the matching, symmetry, and operation of the device.
Regarding claim 8, Aggarwal teaches transistors having gate lengths that are the same and having effective gate widths that are the same (gate width W, gate length L; Col. 7, line 1 – Col. 8, line 40). Also, Bhattacharya teaches having a plurality of dummy transistors (Fig. 10; Pg. 950). However, Nguyen in view of Bhattacharya, Gruber, Aggarwal, Aruga, and Loh does not explicitly teach the situation that the one of the plurality of dummy transistors is adjacent to the one of the plurality of first transistors in the same oxide diffusion region, both the one of the plurality of dummy transistors and the one of the plurality of first transistors have the same effective gate widths and the same first gate lengths; and in the situation that the one of the plurality of dummy transistors is adjacent to the one of the plurality of second transistors in the same oxide diffusion region, both the one of the plurality of dummy transistors and the one of the plurality of second transistors have the same effective gate widths and the same second gate lengths.
Horng teaches the dummy transistor being adjacent to one of the plurality of first transistors in the same oxide diffusion region and the dummy transistor being adjacent to one of the plurality of second transistors in the same oxide diffusion region.
Nguyen, Bhattacharya, Gruber, Aggarwal, Aruga, Loh, and Horng are all analogous art as they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the dummy transistors of Nguyen in view of Bhattacharya, Gruber, Aggarwal, Aruga, and Loh with the dummy transistor of Horng such that in the situation that the one of the plurality of dummy transistors is adjacent to the one of the plurality of first transistors in the same oxide diffusion region, both the one of the plurality of dummy transistors and the one of the plurality of first transistors have the same effective gate widths and the same first gate lengths; and in the situation that the one of the plurality of dummy transistors is adjacent to the one of the plurality of second transistors in the same oxide diffusion region, both the one of the plurality of dummy transistors and the one of the plurality of second transistors have the same effective gate widths and the same second gate lengths. For the purpose of improving the matching, symmetry, and operation of the device.
Regarding claim 9, Nguyen in view of Bhattacharya, Gruber, Aggarwal, Aruga, and Loh does not explicitly teach in a situation that the plurality of first transistors and the plurality of second transistors are N-type transistors, the source terminals of the plurality of first transistors are coupled to a ground line, the drain terminals of the plurality of second transistors of the plurality of first voltage-to-current converters are coupled to one of a plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of second voltage-to-current converters are coupled to another one of the plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of third voltage-to-current converters are coupled to yet another one of the plurality of current lines; and in a situation that the plurality of first transistors and the plurality of second transistors are P-type transistors, the source terminals of the plurality of first transistors are coupled to a power line, the drain terminals of the plurality of second transistors of the plurality of first voltage-to-current converters are coupled to the one of a plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of second voltage-to-current converters are coupled to the another one of the plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of third voltage-to-current converters are coupled to yet another one of the plurality of current lines.
Horng teaches in a situation that the plurality of first transistors and the plurality of second transistors are N-type transistors, the source terminals of the plurality of first transistors are coupled to a ground line, the drain terminals of the plurality of second transistors of the plurality of first voltage-to-current converters are coupled to one of a plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of second voltage-to-current converters are coupled to another one of the plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of third voltage-to-current converters are coupled to yet another one of the plurality of current lines; and in a situation that the plurality of first transistors and the plurality of second transistors are P-type transistors, the source terminals of the plurality of first transistors are coupled to a power line, the drain terminals of the plurality of second transistors of the plurality of first voltage-to-current converters are coupled to the one of a plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of second voltage-to-current converters are coupled to the another one of the plurality of current lines, the drain terminals of the plurality of second transistors of the plurality of third voltage-to-current converters are coupled to yet another one of the plurality of current lines (Figs. 16 & 17a, transistors 604a-604d and 606a-606c, transistors 612a-612d and 616a-616c; ¶148-155).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen in view of Bhattacharya and Gruber as applied to claim 2 above, and further in view of Lin et al. ("Thermal-driven Analog Placement Considering Device Matching"), hereinafter referred to as Lin.
Regarding claim 10, Nguyen in view of Bhattacharya, and Gruber does not explicitly teach N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 4N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, wherein N is a positive integer.
Lin teaches N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 4N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, wherein N is a positive integer (Fig. 8, table 2; Pg. 593, 596-598).
Nguyen, Bhattacharya, Gruber, and Lin are all in the same filed of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nguyen in view of Bhattacharya and Gruber to incorporate the number of sub-devices of Lin such that N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 4N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, wherein N is a positive integer. For the purpose of having a layout with a plurality of sub-devices that preserves symmetry and matching between components.
Regarding claim 11, Nguyen in view of Bhattacharya, and Gruber does not explicitly teach yet another 8N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 8N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 8N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point.
Lin teaches yet another 8N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 8N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 8N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point (Table 2; pg. 593, 596-598).
Nguyen, Bhattacharya, Gruber, and Lin are all in the same filed of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Nguyen in view of Bhattacharya and Gruber to incorporate the number of sub-devices of Lin such that yet another 8N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 8N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 8N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point. For the purpose of having a layout with a plurality of sub-devices that preserves symmetry and matching between components.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al (US Patent No. 7,086,020).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./Examiner, Art Unit 2897
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