DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/15/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment and Argument
Applicant’s amendment with respect to claims 4 and 14 overcomes the previous rejection under 35 U.S.C 112(b). Thus, the rejection of claims 4-9, 14-19 under 35 U.S.C. 112(b) has been withdrawn.
The amendment to claim 1 and 11 have been fully considered. It materially changed the scope of the claim and necessitated a new search of the prior art. Upon conducting this new search, additional relevant references are identified and a new rejection is made in view of Aruga (US-2013/0140642-A1) and Gruber (US-2006/0028248-A1), and further in view of Chen (US-20050132314-A1).
Claim Interpretation
Claim 1 and 11 recite that “the plurality of first sub-converters comprise a plurality of first groups, … the plurality of second sub-converters comprise a plurality of second groups,”. The term “group” does not appear in the specification as filed, and the claims recite no structural, electrical, or functional criterion by which a given sub-converter is determined to belong to one group rather than another. For purpose of examination, this limitation is given its broadest reasonable interpretation consistent with the specification namely that the plurality of first sub-converters includes at least two subsets that generate currents of different magnitude and likewise for the plurality of second sub-converters.
Withdrawal of Indication of Allowable Subject Matter
The indication in the Office action mailed 2/18/2026 that claims 10 and 20 contain allowable subject matter, is hereby withdrawn. That indication was based on the prior art then of record. References newly submitted disclose or render obvious the limitations previously identified as allowable, as set forth in the rejections below. An indication of allowable subject matter does not preclude a subsequent rejection when additional prior art is made of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et. al. (US-2013/0140642-A1, hereinafter Aruga), in view of Gruber et.al. (US-2006/0028248-A1, hereinafter Gruber), and further in view of Chen et.al. (US- 20050132314A1, hereinafter Chen)
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Regarding Claim 1.
Aruga teaches A semiconductor device, comprising:
a substrate, comprising four layout regions,
wherein the four layout regions are arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array (Fig.2 PMAD1A, PMAD1B, PMAD2A, PMAD2B [0010-0012]);
Aruga provides the geometrical pattern of two “first” devices and two “second” devices arranged in a 2x2 array with point symmetry about a center point.
Aruga does not explicitly disclose
two first voltage-to-current converters, respectively arranged in two of the four layout regions,
wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
two second voltage-to-current converters, respectively arranged in the other two of the four layout regions,
wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
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However, In an analogous art pertaining to analog device design, Gruber teaches in Fig.1 and 2, two first voltage-to-current converters, and two second voltage-to-current converters (#1 #2 Fig.1, Fig.2 [0008-0012],[0030-0045]),
Furthermore, Gruber teaches the performance of these converters depend on precise matching between currents derived from different input voltages, and explicitly recognizes that integrating these converters on a semiconductor chip with proper layout arrangement using identical components is important to achieve good matching ( [0008-0012],[0030-0045]).
It would have been obvious to a person of ordinary skill in the art, in view of Aruga, to apply Aruga’s common-centroid layout methodology to the voltage-to-current converter blocks of Gruber, implementing multiple instances of the first and second converters and arranging them in a symmetric 2x2 array on the substrate. Doing so would predictably improve matching of the currents produced by the converters, thereby improving the accuracy and function of the device.
Accordingly, the combination of Aruga and Gruber teaches
two first voltage-to-current converters, respectively arranged in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
two second voltage-to-current converters, respectively arranged in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Aruga modified by Gruber does not explicitly disclose wherein the two first voltage-to-current converters comprise a plurality of first sub-converters, the plurality of first sub-converters comprise a plurality of first groups, and currents generated by the plurality of first groups are different from each other, and wherein the two second voltage-to-current converters comprise a plurality of second sub-converters, the plurality of second sub-converters comprise a plurality of second groups, and currents generated by the plurality of second groups are different from each other.
However, Chen teaches in Fig.3-4 a cascode NMOS current mirror (#100) having a plurality of separately selectable current-mirror paths Ma-Mg. The paths have respective sizes and currents of 1/32, 1/16, 1/8,1/4, 1/2, 1X, and 2X those of the reference device R0 and R1, and respective control bits select the paths (Fig.3-4) Each selectable path is at least a group of sub-converter devices, and the path groups generate different currents. Thus, Chen expressly teaches groups of current-mirror elements that generate difference currents. ([0038-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga and Gruber with the teachings of Chen, as identified above, in order to obtain selectable current levels with improved matching. This is a predictable use of known converter cells in a known matching layout.
Regarding Claim 2.
The combination of Aruga, Gruber and Chen teaches The semiconductor device of claim 1,
Gruber further teaches wherein
the two first voltage-to-current converters comprise a plurality of first sub-converters, the two second voltage-to-current converters comprise a plurality of second sub-converters;
layouts of plurality of first sub-converters of one of the two first voltage-to-current converters are point-symmetrical to layouts of plurality of first sub-converters of the other one of the two first voltage-to-current converters, with respect to the array center point; and
layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters, with respect to the array center point. (Fig.2 [0039-45] Gruber teaches each of the first and second voltage-to-current converters is implemented with current mirror circuitry, therefore each converter is composed of multiple controllable current branches consisting of sub-converters that together form the overall converter behavior.)
Because Aruga already teaches arranging multiple cells of paired devices in symmetric positions about a center point, and Gruber teaches that each converter comprises multiple controllable branches of sub-converters. It would have been no more than routine design for a POSITA to modify the combination of Aruga, Gruber and Chen with the teachings of Gruber, arranging the branches (sub-converters) themselves in a point-symmetric pattern across the two instances of each converter type to preserve common-centroid benefits at the sub-element level.
Regarding Claim 3.
The combination of Aruga, Gruber and Chen teaches The semiconductor device of claim 2,
Gruber teaches wherein ones of the plurality of first sub-converters synchronously enabled are point-symmetrical with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical with respect to the array center point. (Fig.2 [0008-0012],[0030-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga, Gruber and Chen with the teachings of Gruber, as identified above, because selecting symmetric branch subsets to enable is a straightforward design choice once the branches have been laid out in a symmetric pattern which yields the predictable benefit of preserving centroid and matching across different current settings.
Regarding Claim 11.
Aruga teaches A layout method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises four layout regions arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array; (Fig.2 PMAD1A, PMAD1B, PMAD2A, PMAD2B [0010-0012]);
Aruga provides the geometrical pattern of two “first” devices and two “second” devices arranged in a 2x2 array with point symmetry about a center point.
Aruga does not explicitly disclose
arranging two first voltage-to-current converters in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
arranging two second voltage-to-current converters in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
However, In an analogous art pertaining to analog device design, Gruber teaches in Fig.1 and 2,
Arranging in the layout two first voltage-to-current converters, and two second voltage-to-current converters (#1 #2 Fig.1, Fig.2 [0008-0012],[0030-0045]),
Furthermore, Gruber teaches the performance of these converters depend on precise matching between currents derived from different input voltages, and explicitly recognizes that integrating these converters on a semiconductor chip with proper layout arrangement using identical components is important to achieve good matching ( [0008-0012],[0030-0045]).
It would have been obvious to a person of ordinary skill in the art, in view of Aruga, to apply Aruga’s common-centroid layout methodology to the voltage-to-current converter blocks of Gruber, implementing multiple instances of the first and second converters and arranging them in a symmetric 2x2 array on the substrate. Doing so would predictably improve matching of the currents produced by the converters, thereby improving the accuracy and function of the device.
Accordingly, the combination of Aruga and Gruber teaches
arranging two first voltage-to-current converters in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
arranging two second voltage-to-current converters in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Aruga modified by Gruber does not explicitly disclose wherein the two first voltage-to-current converters comprise a plurality of first sub-converters, the plurality of first sub-converters comprise a plurality of first groups, and currents generated by the plurality of first groups are different from each other, and wherein the two second voltage-to-current converters comprise a plurality of second sub-converters, the plurality of second sub-converters comprise a plurality of second groups, and currents generated by the plurality of second groups are different from each other.
However, Chen teaches in Fig.3-4 a cascode NMOS current mirror (#100) having a plurality of separately selectable current-mirror paths Ma-Md. The paths have respective sizes and currents of 1/32, 1/16, 1/8,1/4, 1/2, 1X, and 2X those of the reference device R0 and R1, and respective control bits select the paths (Fig.3-4) Each selectable path is at least a group of sub-converter devices, and the path groups generate different currents. Thus, Chen expressly teaches groups of current-mirror elements that generate difference currents. ([0038-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga and Gruber with the teachings of Chen, as identified above, in order to obtain selectable current levels with improved matching. This is a predictable use of known converter cells in a known matching layout.
Regarding Claim 12.
The combination of Aruga, Gruber and Chen teaches the layout method of claim 11,
Gruber further teaches wherein
the two first voltage-to-current converters comprise a plurality of first sub-converters, the two second voltage-to-current converters comprise a plurality of second sub-converters;
layouts of plurality of first sub-converters of one of the two first voltage-to-current converters are point-symmetrical to layouts of plurality of first sub-converters of the other one of the two first voltage-to-current converters, with respect to the array center point; and
layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters, with respect to the array center point. (Fig.2 [0039-45] Gruber teaches each of the first and second voltage-to-current converters is implemented with current mirror circuitry, therefore each converter is composed of multiple controllable current branches consisting of sub-converters that together form the overall converter behavior.)
Because Aruga already teaches arranging multiple cells of paired devices in symmetric positions about a center point, and Gruber teaches that each converter comprises multiple controllable branches of sub-converters. It would have been no more than routine design for a POSITA to modify the combination of Aruga, Gruber and Chen with the teachings of Gruber, arranging the branches (sub-converters) themselves in a point-symmetric pattern across the two instances of each converter type to preserve common-centroid benefits at the sub-element level.
Regarding Claim 13.
The combination of Aruga, Gruber and Chen teaches The layout method of claim 12,
Gruber teaches wherein ones of the plurality of first sub-converters synchronously enabled are point-symmetrical with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical with respect to the array center point. (Fig.2 [0008-0012],[0030-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga, Gruber and Chen with the teachings of Gruber, as identified above, because selecting symmetric branch subsets to enable is a straightforward design choice once the branches have been laid out in a symmetric pattern which yields the predictable benefit of preserving centroid and matching across different current settings.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et. al. (US-2013/0140642-A1, hereinafter Aruga), in view of Gruber et.al. (US-2006/0028248-A1, hereinafter Gruber), and further in view of Chen et.al. (US- 20050132314A1, hereinafter Chen)
Regarding Claim 10 and 20.
The combination of Aruga, Gruber and Chen teaches
(claim 10) The semiconductor device of claim 2,
(claim 20) The layout method of claim 12,
Chen further teaches
Groups of one, two, four and eight quarter-unit cells forming respective slave current-mirror component A-D, with the cells of each component symmetrically placed in the array; Chen also teaches that a respective control bit selects each current-mirror path (Fig.3,6A, and 6B) For N equal to one, Chen therefore discloses N, 2N, and 4N constituent sub-units forming respective selectable current-mirror groups, each group being enabled together by its corresponding control bit and being symmetrically distributed about the center of the array.
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga, Gruber and Chen with the teachings of Chen, as identified above, because the weighted paths provide predictable current scaling while symmetric distribution preserves matching. Duplicating that known arrangement in each point-symmetric converter would have produced the recited synchronously enabled, point-symmetric N, 2N and 4N groups.
Therefore the combination of Aruga, Gruber and Chen teaches
wherein N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and
yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, wherein N is a positive integer.
Claims 4-5 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et. al. (US-2013/0140642-A1, hereinafter Aruga), in view of Gruber et.al. (US-2006/0028248-A1, hereinafter Gruber) and Chen et.al. (US-20050132314A1, hereinafter Chen), and further in view of Aggarwal et.al. (US-20060026547A1, hereinafter Aggarwal)
Regarding Claim 4 and 14.
The combination of Aruga, Gruber and Chen teaches
(claim 4) The semiconductor device of claim 2,
(claim 14) The layout method of claim 12,
The combination of Aruga, Gruber and Chen does not explicitly disclose
each of the plurality of first sub-converters and each of the plurality of second sub-converters comprise a first transistor and a second transistor;
the plurality of first transistors of the plurality of first sub-converters and the plurality of first transistors of the plurality of second sub-converters have first gate lengths that are the same;
the plurality of second transistors of the plurality of first sub-converters and the plurality of second transistors of the plurality of second sub-converters have second gate lengths that are the same, wherein the first gate lengths are greater than or equal to the second gate lengths; and
the plurality of first transistors and the plurality of second transistors have effective gate widths that are the same.
However, Aggarwal teaches dividing a first transistor into sub-transistors and a second transistor into sub-transistors in a multiple-common-centroid layout for a current mirror and a differential pair (Fig.8 transistors M1 and M2. Sub-transistors MS11, MS12, MS21, MS22) the sub-transistors having gate length(#Ls) that are the same and effective gate widths (#Ws) that are the same. Aruga also teaches in Fig.18 and in related text two PMOS transistors having a common drain and having the same gate width and gate length are employed as the basic unit of the layout ([0165]).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga, Gruber and Chen with the teachings of Aggarwal or Aruga, to use a single common gate width for all of the first and second transistors, and to choose uniform gate lengths for all first transistors and uniform gate lengths for all second transistors in order to maintain matching within each group. Moreover, selecting the first gate length to be greater than or equal to the second gate length is a routine MOSFET sizing choice based on the well-known trad-off between channel length, transconductance, linearity, and matching, and represents nothing more than an obvious optimization of device dimensions in view of the combination of Aruga, Gruber and Chen’s teaching and ordinary analog design practice.
Regarding Claim 5 and 15.
The combination of Aruga, Gruber, Chen and Aggarwal teaches
(claim 5) The semiconductor device of claim 4,
(claim 15) The layout method of claim 14,
Aruga further teaches the device further comprising:
a plurality of oxide diffusion regions (Fig.1, Fig2. #PREG #NREG), arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with two of the four layout regions, another two of the plurality of oxide diffusion regions overlay with the other two of the four layout regions,
wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters and a part of the plurality of second sub-converters. (Fig.1 [0004][0066-0072])
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Application No. 18/474,238, in view of Chen (US- 20050132314A1)
Claim number
Application number 18/474,240
Application number
18/474,238
1,11
A semiconductor device/A layout method for manufacturing a semiconductor device, comprising:
a substrate, comprising four layout regions,
wherein the four layout regions are arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array;
two first voltage-to-current converters, respectively arranged in two of the four layout regions,
wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
two second voltage-to-current converters, respectively arranged in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
wherein the two first voltage-to-current converters comprise a plurality of first sub-converters, the plurality of first sub-converters comprise a plurality of first groups, and currents generated by the plurality of first groups are different from each other, and wherein the two second voltage-to-current converters comprise a plurality of second sub-converters, the plurality of second sub-converters comprise a plurality of second groups, and currents generated by the plurality of second groups are different from each other.
(claim 1) A semiconductor device,
comprising: a substrate, comprising six layout regions,
wherein the six layout regions are arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line- symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array;
two first voltage-to-current converters, respectively arranged in two of the six layout regions,
wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; two second voltage-to-current converters, respectively arranged in another two of the six layout regions, wherein layouts of the two second voltage-to- current converters on the substrate are point-symmetrical with respect to the array center point;
and two third voltage-to-current converters, respectively arranged in the other two of the six layout regions, wherein along the direction of the first axis, the two third voltage-to-current converters are between the two first voltage-to-current converters and the two second voltage-to-current converters, and layouts of the two third voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Claim 1 of 18/474,238 does not explicitly disclose these limitation. However Chen teaches in Fig.3-4 a cascode NMOS current mirror (#100) having a plurality of separately selectable current-mirror paths Ma-Mg. The paths have respective sizes and currents of 1/32, 1/16, 1/8,1/4, 1/2, 1X, and 2X those of the reference device R0 and R1, and respective control bits select the paths (Fig.3-4) Each selectable path is at least a group of sub-converter devices, and the path groups generate different currents. Thus, Chen expressly teaches groups of current-mirror elements that generate difference currents. ([0038-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the teaching of claim 1 of 18/474,238, as identified above, in order to obtain selectable current levels with improved matching. This is a predictable use of known converter cells in a known matching layout.
2,12
The semiconductor device of claim 1/ The layout method of claim 11, wherein
layouts of plurality of first sub-converters of one of the two first voltage-to-current converters are point-symmetrical to layouts of plurality of first sub-converters of the other one of the two first voltage-to-current converters, with respect to the array center point; and
layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters, with respect to the array center point.
(claim 2) The semiconductor device of claim 1,
wherein
the two first voltage-to-current converters comprise a plurality of first sub- converters, the two second voltage-to-current converters comprise a plurality of second sub-converters, and the two third voltage-to-current converters comprise a plurality of third sub-converters;
layouts of plurality of first sub-converters of one of the two first voltage-to- current converters are point-symmetrical to layouts of plurality of first sub- converters of the other one of the two first voltage-to-current converters with respect to the array center point, and ones of the plurality of first sub-converters synchronously enabled are point-symmetrical;
layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical; and
layouts of plurality of third sub-converters of one of the two third voltage- to-current converters are point-symmetrical to layouts of plurality of third sub- converters of the other one of the two third voltage-to-current converters with respect to the array center point, and ones of the plurality of third sub-converters synchronously enabled are point-symmetrical.
3, 13
The semiconductor device of claim 2/The layout method of claim 12, wherein ones of the plurality of first sub-converters synchronously enabled are point-symmetrical with respect to the array center point, and
ones of the plurality of second sub-converters synchronously enabled are point-symmetrical with respect to the array center point.
(see teachings in claim 2 of reference application above)
10, 20
The semiconductor device of claim 2/The layout method of claim 12,
wherein N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and
yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
wherein N is a positive integer.
(Claim 10) The semiconductor device of claim 2,
wherein N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and yet another 4N of the plurality of third sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
wherein N is a positive integer.
4-9, 14-19
Claims 4-9 and 14-19 recite limitations corresponding to those of reference claims 3-9 and 14-18, differing only in the number of converter pairs, and are provisionally rejected for the same reasons,
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 6-9 and 16-19 are rejected.
Claims 6-9 and 16-19 would be allowable if the nonstatutory double patenting rejection is overcome, and to include all of the limitations of the base claim and any intervening claims
Claim 6 would be allowable, because of the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein… the drain terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of second transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of second transistors; the source terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of first transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of first transistor; and the drain terminals of two of the plurality of second transistors, that are adjacent to each other and arranged on the same oxide diffusion region, are coupled to each other. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 16 would be allowable, because of the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein… the drain terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of second transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of second transistors; the source terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of first transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of first transistor; and the drain terminals of two of the plurality of second transistors, that are adjacent to each other and arranged on the same oxide diffusion region, are coupled to each other. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 7-9 and 17-19 would be allowable because they depends from claim 6 or claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Loh et.al. (US5627732A, hereinafter Loh)
Horng et.al. (US-20230178605A1, hereinafter Horng)
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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