DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-9 and 14-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 4 and 14:
It is unclear whether the claimed limitation “the plurality of first transistors” refers to transistors for only the first sub-converters, only the second sub-converters, or both.
It is unclear whether the claimed limitation “the plurality of second transistors” refers to transistors for only the first sub-converters, only the second sub-converters, or both. Therefore, it is indefinite.
Claims 5-9 and 15-19 depends from claim 4 or 14 so they are rejected for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Aruga et. al. (US-2013/0140642-A1, hereinafter Aruga), and further in view of Gruber et.al. (US-2006/0028248-A1, hereinafter Gruber).
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Regarding Claim 1.
Aruga teaches A semiconductor device, comprising:
a substrate, comprising four layout regions,
wherein the four layout regions are arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array (Fig.2 PMAD1A, PMAD1B, PMAD2A, PMAD2B [0010-0012]);
Aruga provides the geometrical pattern of two “first” devices and two “second” devices arranged in a 2x2 array with point symmetry about a center point.
Aruga does not explicitly disclose
two first voltage-to-current converters, respectively arranged in two of the four layout regions,
wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
two second voltage-to-current converters, respectively arranged in the other two of the four layout regions,
wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
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However, In an analogous art pertaining to analog device design, Gruber teaches in Fig.1 and 2, two first voltage-to-current converters, and two second voltage-to-current converters (#1 #2 Fig.1, Fig.2 [0008-0012],[0030-0045]),
Furthermore, Gruber teaches the performance of these converters depend on precise matching between currents derived from different input voltages, and explicitly recognizes that integrating these converters on a semiconductor chip with proper layout arrangement using identical components is important to achieve good matching ( [0008-0012],[0030-0045]).
It would have been obvious to a person of ordinary skill in the art, in view of Aruga, to apply Aruga’s common-centroid layout methodology to the voltage-to-current converter blocks of Gruber, implementing multiple instances of the first and second converters and arranging them in a symmetric 2x2 array on the substrate. Doing so would predictably improve matching of the currents produced by the converters, thereby improving the accuracy and function of the device.
Accordingly, the combination of Aruga and Gruber teaches
two first voltage-to-current converters, respectively arranged in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
two second voltage-to-current converters, respectively arranged in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Regarding Claim 2.
The combination of Aruga and Gruber teaches The semiconductor device of claim 1,
Gruber further teaches wherein
the two first voltage-to-current converters comprise a plurality of first sub-converters, the two second voltage-to-current converters comprise a plurality of second sub-converters;
layouts of plurality of first sub-converters of one of the two first voltage-to-current converters are point-symmetrical to layouts of plurality of first sub-converters of the other one of the two first voltage-to-current converters, with respect to the array center point; and
layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters, with respect to the array center point. (Fig.2 [0039-45] Gruber teaches each of the first and second voltage-to-current converters is implemented with current mirror circuitry, therefore each converter is composed of multiple controllable current branches consisting of sub-converters that together form the overall converter behavior.)
Because Aruga already teaches arranging multiple cells of paired devices in symmetric positions about a center point, and Gruber teaches that each converter comprises multiple controllable branches of sub-converters. It would have been no more than routine design for a POSITA to modify the combination of Aruga and Gruber with the teachings of Gruber, arranging the branches (sub-converters) themselves in a point-symmetric pattern across the two instances of each converter type to preserve common-centroid benefits at the sub-element level.
Regarding Claim 3.
The combination of Aruga and Gruber teaches The semiconductor device of claim 2, Gruber teaches wherein ones of the plurality of first sub-converters synchronously enabled are point-symmetrical with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical with respect to the array center point. (Fig.2 [0008-0012],[0030-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga and Gruber with the teachings of Gruber, as identified above, because selecting symmetric branch subsets to enable is a straightforward design choice once the branches have been laid out in a symmetric pattern which yields the predictable benefit of preserving centroid and matching across different current settings.
Regarding Claim 4.
The combination of Aruga and Gruber teaches The semiconductor device of claim 2, The combination of Aruga and Gruber does not explicitly disclose
each of the plurality of first sub-converters and each of the plurality of second sub-converters comprise a first transistor and a second transistor;
the plurality of first transistors of the plurality of first sub-converters and the plurality of second sub-converters have first gate lengths that are the same;
the plurality of second transistors of the plurality of first sub-converters and the plurality of second sub-converters have second gate lengths that are the same, wherein the first gate lengths are greater than or equal to the second gate lengths; and
the plurality of first transistors and the plurality of second transistors have effective gate widths that are the same.
However, Aruga teaches in Fig.18 and in related text two PMOS transistors having a common drain and having the same gate width and gate length are employed as the basic unit of the layout ([0165]). It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention, when implementing Gruber’s sub-converters in Aruga’s regular analog array, to use a single common gate width for all of the first and second transistors, and to choose uniform gate lengths for all first transistors and uniform gate lengths for all second transistors to maintain matching within each group. Moreover, selecting the first gate length to be greater than or equal to the second gate length is a routine MOSFET sizing choice based on the well-known trad-off between channel length, transconductance, linearity, and matching, and represents nothing more than an obvious optimization of device dimensions in view of the combination of Aruga and Gruber’s teaching and ordinary analog design practice.
Regarding Claim 5.
The combination of Aruga and Gruber teaches The semiconductor device of claim 4, Aruga futher teaches the device further comprising:
a plurality of oxide diffusion regions (Fig.1, Fig2. #PREG #NREG), arranged on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with two of the four layout regions, another two of the plurality of oxide diffusion regions overlay with the other two of the four layout regions,
wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters and a part of the plurality of second sub-converters. (Fig.1 [0004][0066-0072])
Regarding Claim 11.
Aruga teaches A layout method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises four layout regions arranged as an array having a plurality of columns and a plurality of rows, wherein the array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, and the first axis perpendicularly intersects the second axis at an array center point of the array; (Fig.2 PMAD1A, PMAD1B, PMAD2A, PMAD2B [0010-0012]);
Aruga provides the geometrical pattern of two “first” devices and two “second” devices arranged in a 2x2 array with point symmetry about a center point.
Aruga does not explicitly disclose
arranging two first voltage-to-current converters in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
arranging two second voltage-to-current converters in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
However, In an analogous art pertaining to analog device design, Gruber teaches in Fig.1 and 2,
Arranging in the layout two first voltage-to-current converters, and two second voltage-to-current converters (#1 #2 Fig.1, Fig.2 [0008-0012],[0030-0045]),
Furthermore, Gruber teaches the performance of these converters depend on precise matching between currents derived from different input voltages, and explicitly recognizes that integrating these converters on a semiconductor chip with proper layout arrangement using identical components is important to achieve good matching ( [0008-0012],[0030-0045]).
It would have been obvious to a person of ordinary skill in the art, in view of Aruga, to apply Aruga’s common-centroid layout methodology to the voltage-to-current converter blocks of Gruber, implementing multiple instances of the first and second converters and arranging them in a symmetric 2x2 array on the substrate. Doing so would predictably improve matching of the currents produced by the converters, thereby improving the accuracy and function of the device.
Accordingly, the combination of Aruga and Gruber teaches
arranging two first voltage-to-current converters in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point; and
arranging two second voltage-to-current converters in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
Regarding Claim 12.
The combination of Aruga and Gruber teaches the layout method of claim 11,
Gruber further teaches wherein
the two first voltage-to-current converters comprise a plurality of first sub-converters, the two second voltage-to-current converters comprise a plurality of second sub-converters;
layouts of plurality of first sub-converters of one of the two first voltage-to-current converters are point-symmetrical to layouts of plurality of first sub-converters of the other one of the two first voltage-to-current converters, with respect to the array center point; and
layouts of plurality of second sub-converters of one of the two second voltage-to-current converters are point-symmetrical to layouts of plurality of second sub-converters of the other one of the two second voltage-to-current converters, with respect to the array center point. (Fig.2 [0039-45] Gruber teaches each of the first and second voltage-to-current converters is implemented with current mirror circuitry, therefore each converter is composed of multiple controllable current branches consisting of sub-converters that together form the overall converter behavior.)
Because Aruga already teaches arranging multiple cells of paired devices in symmetric positions about a center point, and Gruber teaches that each converter comprises multiple controllable branches of sub-converters. It would have been no more than routine design for a POSITA to modify the combination of Aruga and Gruber with the teachings of Gruber, arranging the branches (sub-converters) themselves in a point-symmetric pattern across the two instances of each converter type to preserve common-centroid benefits at the sub-element level.
Regarding Claim 13.
The combination of Aruga and Gruber teaches The layout method of claim 12, Gruber teaches wherein ones of the plurality of first sub-converters synchronously enabled are point-symmetrical with respect to the array center point, and ones of the plurality of second sub-converters synchronously enabled are point-symmetrical with respect to the array center point. (Fig.2 [0008-0012],[0030-0045])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Aruga and Gruber with the teachings of Gruber, as identified above, because selecting symmetric branch subsets to enable is a straightforward design choice once the branches have been laid out in a symmetric pattern which yields the predictable benefit of preserving centroid and matching across different current settings.
Regarding Claim 14.
The combination of Aruga and Gruber teaches The layout method of claim 12,
The combination of Aruga and Gruber does not explicitly disclose
each of the plurality of first sub-converters and each of the plurality of second sub-converters comprise a first transistor and a second transistor;
the plurality of first transistors of the plurality of first sub-converters and the plurality of second sub-converters have first gate lengths that are the same;
the plurality of second transistors of the plurality of first sub-converters and the plurality of second sub-converters have second gate lengths that are the same, wherein the first gate lengths are greater than or equal to the second gate lengths; and
the plurality of first transistors and the plurality of second transistors have effective gate widths that are the same.
However, Aruga teaches in Fig.18 and in related text two PMOS transistors having a common drain and having the same gate width and gate length are employed as the basic unit of the layout ([0165]). It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention, when implementing Gruber’s sub-converters in Aruga’s regular analog array, to use a single common gate width for all of the first and second transistors, and to choose uniform gate lengths for all first transistors and uniform gate lengths for all second transistors to maintain matching within each group. Moreover, selecting the first gate length to be greater than or equal to the second gate length is a routine MOSFET sizing choice based on the well-known trad-off between channel length, transconductance, linearity, and matching, and represents nothing more than an obvious optimization of device dimensions in view of the combination of Aruga and Gruber’s teaching and ordinary analog design practice.
Regarding Claim 15.
The combination of Aruga and Gruber teaches The layout method of claim 14,
Aruga futher teaches the device further comprising:
arranging a plurality of oxide diffusion regions (Fig.1, Fig2. #PREG #NREG) on the substrate in parallel to the first axis, wherein two of the plurality of oxide diffusion regions overlay with two of the four layout regions, another two of the plurality of oxide diffusion regions overlay with the other two of the four layout regions,
wherein a part of the plurality of the first transistors and a part of the plurality of the second transistors are alternately arranged on the same oxide diffusion region, so as to form a part of the plurality of first sub-converters and a part of the plurality of second sub-converters. (Fig.1 [0004][0066-0072])
Allowable Subject Matter
Claims 6-9 and 16-19 are rejected.
Claims 6-9 and 16-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AlA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein … the drain terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of second transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of second transistors;
the source terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of first transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of first transistor; and
the drain terminals of two of the plurality of second transistors, that are adjacent to each other and arranged on the same oxide diffusion region, are coupled to each other. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 7-9 contain allowable subject matter because they depend from claim 6.
Claim 10 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein …N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and
yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, wherein N is a positive integer. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 16 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein … the drain terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of second transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of second transistors;
the source terminal of each of the plurality of first transistors is coupled to the source terminal of an adjacent one of the plurality of first transistors, and is arranged on the same oxide diffusion region with the adjacent one of the plurality of first transistors; and
the drain terminals of two of the plurality of second transistors, that are adjacent to each other and arranged on the same oxide diffusion region, are coupled to each other. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 17-19 contain allowable subject matter because they depend from claim 6.
Claim 20 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the method, wherein … N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
another 2N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
yet another 4N of the plurality of first sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point,
another 2N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, and
yet another 4N of the plurality of second sub-converters are synchronously enabled and point-symmetrical with respect to the array center point, wherein N is a positive integer.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817