DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 4/28/2026 have been fully considered but they are not persuasive.
Applicant argues on Page 9 that Fig. 6 shows the amended limitation of claim 5 that “connection lines, each of the connection lines electrically connecting the circuit element layer to each of the first light emitting diodes.” The Examiner acknowledges Fig. 6 does show multiple connection lines CL, CL’, each of which extend to a respective first light emitting diodes LD1.
However, as discussed in the 112 Rejections below, There are more than two first light emitting diodes LD1 as seen in Fig. 4, and each connection lines does not individually electrically connect the circuit element layer to each of the first light emitting diodes as claimed.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection
Applicant argues on Pages 10, 11 and 14 with respect to claims 1-4, 9-11, 16-19 and 22, that Jeon et al. does not have the claimed circuit element layer disposed in the second area connected to the first light emitting diodes disposed in the non-transmission area. However, this argument is moot with respect to the previously applied 102 Rejection in view of Jeon et al., as new grounds of Rejection necessitated by Applicant’s Amendment are provided herein.
Furthermore, with respect to the New grounds of rejection, the circuit element layer is interpreted to be at least the DL, PL (and optionally also elements 101, 103, 105, 107, and associated conductive lines) of Lee et al. (US PGPub 2021/0233474 A1) and DL, PL (and associated insulating layers adjacent thereto) of Jeon et al. (US PGPub 2021/0376279 A1).
While Applicant is using the term “circuit element layer” to refer to the layers associated with pixel circuitry PC1 such as the transistor included in Applicant’s Annotated Fig. 6, Page 10 of Remarks, the term “circuit element layer is not specifically limited to a specific type of circuit element. Therefore, other circuit elements such as Data line and power lines in the second area would also satisfy this claimed limitation.
Furthermore, the claim limitation only recites “connected.” All the elements in the device are “connected.” Applicant may wish to amend to “electrically connected” to clarify.
Applicant’s arguments with respect to claims 12-15 have been considered but are moot in view of the new grounds of rejection
Specification
The amendments filed 4/28/2026 are sufficient to overcome the objections to the specification stated in the previous office action. Therefore, said objections are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As discussed in the 112(b) Rejection of claim 5, below, the limitation as written appears to be new matter, but it is not clear if this is Applicant’s intended scope.
Insofar as the limitation is as written were the intended scope, the claim limitation constitutes new matter. The connection lines do not each connect to each of first light emitting diodes, as discussed in the 112(b) Rejection below.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “connection lines, each of the connection lines electrically connecting the circuit element layer to each of the first light emitting diodes.” It is not clear if the limitation as written is what Applicant intended to claim OR if Applicant intended an accurate description of the embodiment of Fig. 4. As seen in Fig. 4, multiple connection lines CL are drawn. At least one of the connection lines CL appears to connect an individual light emitting diode labeled LD1 to a respective first pixel circuit PC1. Each connection line CL is not drawn connected to the labeled first light emitting diode LD1 as required by claim 5 and each first light emitting diodes are not drawn to be connected to each of the connection lines. The limitation as written appears to be new matter. Why would there by multiple connection lines if each line already connects to each of the first light emitting diodes?
Therefore, it is not clear if Applicant intended the scope of the claim as written or as some other undetermined limitation.
For the purposes of Examination, claim 5 will be examined as though claim 5 recited a plurality of connection lines, each respectively connecting the circuit element layer and a respective one of the first light emitting diodes; and a sub-organic film covering the connection line in the transmission area.
Claims 6-8 are dependent on claim 5 and contain the same deficiencies.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 9-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PGPub 2021/0233474 A1).
As to claim 1, Lee et al. discloses (Figs. 3A, 4, 5, 7, and 9) a display device comprising: a first area A including a transmission area 1A (Paragraph 97) and a non-transmission area (part of A that is not 1A) adjacent to the transmission area 1A and a second area (part of DA that is not A) adjacent to the first area A; a circuit element layer DL, PL (and optionally also elements 101, 103, 105, 107, and associated conductive lines) disposed in the second area DA on a substrate 100; a light emitting element layer OLED disposed on the circuit element layer DL, PL, electrically connected to the circuit element layer DL, PL (Fig. 5), and including first light emitting diodes OLED disposed in the non-transmission area (Fig. 8, #P); and an organic layer 113, 180 (Paragraphs 167 and 180) disposed on the circuit element layer DL, PL, adjacent to the light emitting element layer OLED, and including an opening (Fig. 9, opening corresponding to 1A) overlapping the transmission area 1A in a plan view and between the first light emitting diodes OLED, wherein the circuit element layer DL, PL disposed in the second area DA is connected (at least electrically, see Fig. 5) to the first light emitting diodes OLED disposed in the non-transmission area (part of A that is not 1A) of the first area A.
Furthermore, the claim limitation in line 11 only recites “connected.” While this Rejection does include electrical connection between the elements, it would also include physical connection. All the elements in the device are “connected.” Applicant may wish to amend to “electrically connected” to clarify.
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As to claim 2, Lee et al. discloses (Fig. 9) that the opening 1A of the organic layer 113, 180 is spaced apart from the first light emitting diodes OLED in a plan view.
As to claim 3, Lee et al. discloses (Fig. 9) that the organic layer 113, 180 includes: a first organic film disposed 113 between the circuit element layer DL, PL and the light emitting element layer OLED, overlapping the second area (part of DA that is not A) and the non-transmission area (part of A that is not 1A) in a plan view (Fig. 4, there are pixels P in both the second area and the non-transmission area, and therefore the first organic film 113 will also be in those areas), and including a first opening overlapping the transmission area 1A in a plan view; and a second organic film 180 disposed on the first organic film 113, overlapping the second area and the non-transmission area in a plan view (Fig. 4, there are pixels P in both the second area and the non-transmission area, and therefore the first organic film 180 will also be in those areas), and including a second opening overlapping the transmission area 1A in a plan view, the first opening and the second opening overlap, in a plan view, and the first opening and the second opening constitute the opening of the organic layer 113, 180.
As to claim 4, Lee et al. discloses (Fig. 9) that the first organic film 113 overlaps the first light emitting diodes OLED in a plan view, and the second organic film 180 is adjacent to the first light emitting diodes OLED.
As to claim 9, Lee et al. discloses that the light emitting element layer OLED further includes second light emitting diodes (Fig. 4, #P in part of DA that is not A, pixel P will include OLED) disposed on the circuit element layer (pixel P including DL, PL and other elements of circuit element layer) and disposed in the second area (part of DA that is not A).
As to claim 10, Lee et al. discloses (Fig. 9) that each of the first light emitting diodes OLED includes: a pixel electrode 210 (Paragraph 166); and a light emitting layer 220 (Paragraph 171) disposed on the pixel electrode 210.
As to claim 11, Lee et al. discloses that the first organic film 113 is disposed below the pixel electrode 210 and overlaps the pixel electrode 210 in a plan view, the second organic film 180 includes a pixel opening exposing a portion of the pixel electrode 210, and the light emitting layer 220is disposed in the pixel opening.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Wang et al. (US PGPub 2020/0105844 A1).
As to claim 16, Lee et al. discloses (Figs. 3A, 4, 5, 7, and 9) a method of manufacturing a display device, the method comprising: forming a circuit element layer DL, PL (and optionally also elements 101, 103, 105, 107, and associated conductive lines) in a second area (part of DA that is not A) on a substrate 100, the display device including a first area A including a transmission area 1A (Paragraph 97) and a non-transmission area (part of A that is not 1A) adjacent to the transmission area 1A, and the second area having a lower transmittance than a transmittance of the first area (Paragraph 97, 178); forming an organic layer 113, 180 (Paragraphs 167 and 180) on the circuit element layer DL, PL; forming a light emitting element layer OLED including first light emitting diodes OLED in the non- transmission area A on the circuit element layer DL, PL; and forming an opening (corresponding to 1A) between the first light emitting diodes OLED in the transmission area 1A, wherein the circuit element layer DL, PL disposed in the second area DA is connected (at least electrically, see Fig. 5) to the first light emitting diodes OLED disposed in the non-transmission area (part of A that is not 1A) of the first area A.
Lee et al. discloses the opening (corresponding to 1A) between light emitting diodes OLED, but Lee et al. does not explicitly teach the specific method step of patterning the organic insulating layer to form the opening.
Wang et al. teaches (Fig. 4) patterning the insulating layer 30, 70 to form the transmission area 02, such as by etching, and the like (Paragraphs 44 and 52).
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Therefore, it would be obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to pattern the organic insulating layer of Lee et al. in the transmission area, as taught by Wang et al., in order to achieve the desired hole in the transmission area since it is taught as suitable by Wang et al. and the selection from among known suitable alternatives for their known purposes is generally within the abilities of one having ordinary skill in the art.
Furthermore, the claim limitation in line 11 only recites “connected.” While this Rejection does include electrical connection between the elements, it would also include physical connection. All the elements in the device are “connected.” Applicant may wish to amend to “electrically connected” to clarify.
Claim(s) 17-19 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Wang et al as applied to claim 16 above, and further in view of Kim (US PGPub 2017/0148861 A1).
As to claim 17, Lee et al. in view of Wang et al. teaches that the forming of the light emitting element layer and the forming of the organic layer includes: forming a first organic film (Lee et al. 113) on the circuit element layer (Lee et al. DL, PL); forming a first opening overlapping the transmission area in the first organic film in a plan view (Wang et al. #H); forming a pixel electrode (Lee et al. #210) on the first organic film 113; forming a second organic film 180 on the pixel electrode 210; forming a second opening (Wang et al. #H) overlapping the transmission area in a plan view in the second organic film 180; and forming a light emitting layer (Lee et al. #220) in the pixel opening OP2.
Lee et al. discloses a pixel opening (Fig. 9, opening in 180 for OLED), but does not explicitly state how the pixel opening is formed.
Kim teaches (Fig. 5K) forming second organic insulating material and then patterned to form opening 120a exposing a portion of the pixel electrode 150 (Paragraph 160).
Therefore, it would be obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, in the absence of an explicit teaching by Lee et al. in how to make the opening that exposes the pixel electrode, to look to the prior art for suitable method steps to do so and therefore find it obvious to make a layer and then form the opening, as taught by Kim, since it is taught as suitable by Kim and the selection from among known suitable alternatives for their known purposes is generally within the abilities of one having ordinary skill in the art.
As to claim 18, Lee et al. discloses (Figs. 8 and 9) a connection line (130 and part of DL outside of and adjacent to 1A) electrically connected (Fig. 4) to the circuit element layer DL, PL and the pixel electrode 210 (Figs. 5, 7 and 9).
As to claim 19, Lee et al. discloses forming a sub-organic film 113 overlapping the connection line 130, DL in a plan view by patterning the first organic film 113 (patterning to form hole overlapping transmission area TA in view of Wang et al.).
As to claim 22, Jeon et al. discloses forming a sub-organic film 180 overlapping the connection line 130, DL in a plan view by patterning the second organic film 180 (patterning to form hole overlapping transmission area TA in view of Wang et al.).
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US PGPub 2021/0376279 A1) in view of Wang et al.
As to claim 12, Jeon et al. discloses (Figs. 1-4, 7 and 9) a display device comprising: a first area CA including a transmission area TA and a non-transmission area (area of CA that is not TA, associated with Pa) adjacent to the transmission area TA and a second area MDA adjacent to the first area CA; a circuit element layer (DL, PL and optionally also associated insulating layers adjacent thereto) disposed in the non-transmission area Pa on a substrate 100a; a light emitting element layer (layers associated with Pa, Pm, including 122a, 122b’, 122c) disposed on the circuit element layer DL, PL, electrically connected to the circuit element layer DL, PL, and including light emitting diodes OLED’ disposed in the non-transmission area Pa (Paragraph 98, unit U is repeated in the x and y direction, and therefore there will be a light emitting diode Pa on either side of TA); and an organic layer 117, 119 (Paragraphs 143, 144, 152) disposed on the circuit element layer DL, PL, adjacent to the light emitting element layer 122, and including an opening (associated with TA) overlapping the transmission area TA in a plan view and between the light emitting diodes OLED’ (Paragraph 98). Furthermore, Jeon et al. discloses a unit pattern (associated with TFT’ of Fig. 9).
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Jeon et al. discloses circuit wiring lines SL, DL, with the line SL being a gate line (Paragraphs 74, gate electrode of T2 connected to SL), wherein a component 40 associated with the first region is an imaging device such as a camera (Paragraph 41), but does not explicitly show the positioning of the circuit wiring lines in the first area.
Wang et al. teaches (Figs. 7 and 8) a conductive layer 20, 90, 100 is disposed on the substrate 10 corresponding to the non- transmission area 1, and includes unit patterns (associated with #20 and located in light emitting region 1 except the part that corresponds to 90, 100) and bridge patterns (parts of gate lines 90, data lines 100 outside of the unit patterns), and each of the bridge patterns 90, 100 connects adjacent unit patterns, and the transmission area is defined by the unit patterns 20 and the bridge patterns 90, 100, wherein the regions 2 are transparent to aid in acquiring an image (Paragraphs 40 and 45).
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Therefore, in the absence of an explicit teaching of the location of the circuit wiring lines SL, DL of Jeon et al., one having ordinary skill in the art before the effective filing date of the claimed invention, would look to the prior art for suitable locations for the circuit wiring lines and therefore find it obvious to use the type of layout of unit patterns and bridge patterns taught by Wang et al. since it is taught as suitable by Wang et al. and the selection from among known suitable alternatives for their known purposes is generally within the abilities of one having ordinary skill in the art.
As to claim 13, Jeon et al. discloses (Figs. 7 and 9) that the opening (associated with TA) of the organic layer 117, 119 does not overlap the light emitting diodes OLED’ in a plan view.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. in view of Wang et al. as applied to claim 12 above, and further in view of Lee et al.
As to claim 14, Jeon et al. discloses (Figs. 7 and 9) that the organic layer includes: a first organic film 117 disposed below the light emitting element layer 122, overlapping the second area MDA and the non-transmission area Pa in a plan view, and including a first opening (associated with TA) overlapping the transmission area TA in a plan view; and a second organic film 119 disposed on the first organic film 117, overlapping the second area MDA and the non-transmission area Pa in a plan view, and including a second opening (Associated with TA) overlapping the transmission area TA in a plan view.
Jeon et al. discloses circuit element layer DL, PL in the second area MDA in plan view, but does not show it in the cross-sectional view of Fig. 9.
Lee et al. teaches (Fig. 9) including circuit element layer DL, PL (PL1) beneath the first organic film 113.
Therefore, it would be obvious in the absence of an explicit teaching by Jeon et al. of the layer on which the circuit element layer DL, PL is formed to look to the prior art for suitable locations and therefore one having ordinary skill in the art before the effective filing date of the claimed invention to place the circuit element layer DL, PL on the analogous layer 115 of Jeon et al. since the selection from among known suitable locations for their known purposes is generally within the abilities of one having ordinary skill in the art. Such modification would have the first organic film 117 of Jeon et al. disposed between the circuit element layer DL, PL and the light emitting element layer 122.
As to claim 15, Jeon et al. discloses that the first organic film 117 overlaps the light emitting diodes OLED’ in a plan view, and the second organic film 119 is adjacent to the light emitting diodes OLED’.
Allowable Subject Matter
Claims 20, 21, 23, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 20, the prior art does not teach or suggest that the forming of the sub-organic film is performed simultaneously with the forming of the first organic film, and a height of the sub-organic film is less than a height of the first organic film. It is contemplated that forming a sub-organic film in the transmission area on the connection line may serve to protect the connection line, while having a lower height allows less material in the transmission area, potentially leading to higher transmission.
While Lee et al Fig. 9 has an organic film 320 in the transmission area 1A, it is formed simultaneously with the organic encapsulation layer 320, not the organic layer 113, 118 and also it is clear from Lee et al. if the height of the sub-organic film is less than a heigh of the first organic film.
Claim 21 is dependent on claim 20 and contains the same allowable subject matter.
As to claim 23, the prior art does not teach or suggest that the forming of the sub-organic film is performed simultaneously with the forming of the second organic film, and a height of the sub-organic film is smaller than a height of the second organic film. It is contemplated that forming a sub-organic film in the transmission area on the connection line may serve to protect the connection line, while having a lower height allows less material in the transmission area, potentially leading to higher transmission.
While Lee et al Fig. 9 has an organic film 320 in the transmission area 1A, it is formed simultaneously with the organic encapsulation layer 320, not the organic layer 113, 118 and also it is clear from Lee et al. if the height of the sub-organic film is less than a heigh of the second organic film.
Claim 24 is dependent on claim 23 and contains the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al. (US PGPub 2022/0352292 A1) teaches (Figs. 2A and 9A) a transmissive area 1/10 with a connection line 101 connecting the circuit element layer 12 and a respective one of the first light emitting diodes 114, with the connection line covered by sub-organic insulation layer 146 (Paragraph 117).
Choi et al. (US PGPub 2021/0376007 A1) discloses (Figs. 1, 8A and 9) a display device with a component area CA that has transmission areas TA with openings in layers 117, 119.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.Y.H/ Examiner, Art Unit 2875
/ABDULMAJEED AZIZ/ Supervisory Patent Examiner, Art Unit 2875
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