DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 15, 2026 has been entered.
Response to Amendment
The Amendment filed September 15, 2026 has been entered. Applicant' s amendment the title of the invention has been considered, and the objection is hereby withdrawn.
Claims 1-12 and 14-21 are pending in the application.
Response to Arguments
Applicant’s arguments, see pages 9-16 of Remarks, filed September 15, 2026, with respect to the rejections of claims under 1-12 and 14-21 under 35 U.S.C 103 have been fully considered in view of the Amendment and the arguments in regard to a requirement for a disc-shaped semiconductor wafer are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly identified prior art in combination with that previously cited.
Additionally, the rejection of claim 21 has been updated to correct errors (typos) in the claim mapping. The Examiner notes, with reference to paragraphs [0005-0007] of Okumura, that the structure included in Figs 17-18 includes a source pad 121 which includes a portion of a source electrode 111, the portion being exposed in an opening 113a of a polyimide layer 113, wherein the source pad 121 further includes a plating film 131 covering its surface.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shinohara; Eiichi et al. (US 20150028907; hereinafter Shinohara) in view of Okumura; Keiji (US 2020/0303269; hereinafter Okumura).
Regarding claim 1, Shinohara discloses a semiconductor structure for inspection comprising:
a semiconductor plate including a disc-shaped semiconductor wafer (semiconductor wafer W comprising a plurality of power devices or chips to be inspected {¶ [0004-0005; 0077}, for example a vertical MOSFET {as described; ¶ [0004]}; Fig 1; ¶ [0033]) and having a first main surface (upper surface of W) on one side and a second main surface (lower surface of W) on the other side;
an inspection region (a region including a number of the power devices or chips to be inspected, which may be every power device or chip on the wafer {¶ [0077]), and the electrodes which comprise each power device; ¶ [0033]) provided in the first main surface;
a main surface electrode having a first hardness and covering the first main surface in the inspection region (one of the electrodes formed on both sides of the chip at the upper surface of W, which implicitly has a first hardness; ¶ [0033]).
Shinohara does not disclose an insulating film covering a peripheral edge of the main surface electrode over an entire circumference of the peripheral edge, and partitioning an opening that has a wall surface extending along the entire circumference of the peripheral edge and exposes an inner side portion of the main surface electrode; and a protective electrode having a second hardness which exceeds the first hardness, covering the entire area of the inner side portion of the main surface electrode inside the opening in the inspection region, and forming a current path between the second main surface and the protective electrode via the semiconductor plate.
In the same field of endeavor, Okumura discloses a semiconductor device (for example, a vertical MOSFET, 110; Figs 17,18; ¶ [0003-0009]) having a first main surface (upper surface of 110, adjacent to 111 of Fig 18) on one side and a second main surface (lower surface of 110; Fig 18) on the other side;
an inspection region (active region 101; Fig 17; ¶ [0005]) provided in the first main surface;
a main surface electrode (source electrode 111, containing aluminum (Al); Figs 17,18; ¶ [0005-6]) having a first hardness and covering the first main surface in the inspection region;
an insulating film (polyimide layer 113; Figs 17,18; ¶ [0005]) covering a peripheral edge of the main surface electrode over an entire circumference of the peripheral edge (shown in Fig 17; ¶ [0006]), and partitioning an opening that has a wall surface extending along the entire circumference of the peripheral edge and exposes an inner side portion of the main surface electrode (shown in Figs 17,18); and
a protective electrode (131, formed by a nickel (Ni) plating film and a gold (Au) plating film sequentially stacked, Figs 17,18; ¶ [0007]) having a second hardness, covering the entire area of the inner side portion of the main surface electrode inside the opening in the inspection region (Figs 17,18; ¶ [0006-7]), and forming a current path between the second main surface and the protective electrode via the semiconductor plate (during screening, large current can be passed through 110 to 131; ¶ [0007]).
Okumura does not specifically disclose in this conventional semiconductor embodiment that the second hardness of the second electrode exceeds the first hardness of the first electrode. However, it would have been obvious to a person having ordinary skill in the art that the disclosed plating film 131 formed of Ni/Au would have a hardness which exceeds that of source electrode 111 that contains Al, because it is well known in the art that Ni, at least, has a hardness greater than Al, and because the greater hardness is one reason well-known in the art for the use of Ni as a pad plating film.
In addition, Okumura discloses in an embodiment of the invention a similar structure wherein a plating film 31 (analogous to 131, and which also may be formed of Au stacked on Ni; Figs 1,2; ¶ [0072-74]) has a second hardness which exceeds a first hardness of a first electrode 11 (analogous to 111, and also containing Al ; Figs 1,2; ¶ [0068-69, 0072]). The Examiner considers that the embodiment of the invention of Figs 1-6, comprising this similar structure, may be regarded as a combination of a first disclosed conventional embodiment of Figs 17-20 and a second disclosed conventional embodiment of Figs 17, 21-23 wherein the pad structures 121 (Fig 18) and 121’ (Fig 21) have been combined within one opening of an insulating film (13 {Figs 1-2}; 113 {Figs 17,18,21}). In this regard, the disclosed hardness relationship of the Figs 1-6 embodiment is considered obvious in the portion corresponding to the Figs 17-20 embodiment.
Alternately, for a person not needing or wanting to use Al bonding wire with the electrode (using, for example, using a terminal pin such as 133 of Fig 20; ¶ [0058]), it would be obvious to use a plating film comprising Ni and/or Au (Al is soft as compared to Ni or Au; ¶ [0059]) to prevent cracks in the electrode pad during screening (Okumura; ¶ [0058-59]). In this case, one may arrive at the above-mentioned claim 1 limitations from the inventive embodiment of Figs 1-6 of Okumura by omitting an unneeded portion 21b (Figs 1-3) to reduce manufacturing steps and complexity.
It would have been obvious to a person having ordinary skill in the art to have combined the semiconductor device features disclosed by Okumura with the semiconductor structure for inspection of Shinohara. One would have been motivated to do this in order to complete a wafer level inspection of the device(s) of Okumura (Shinohara; ¶ [0033]), and thereby save expense over an inspection done only after completion, potentially on semiconductor devices that fail the inspection, of additional manufacturing steps (such as, for example, dicing the wafer and packaging the semiconductor devices). One would have had a reasonable expectation of success because Shinohara discloses the semiconductor structure for wafer level inspection including an exemplary vertical MOSFET device comprising frontside (main surface) source and gate electrodes and backside drain electrode, and Okumura discloses the similar exemplary vertical MOSFET device comprising frontside (main surface) source and gate electrodes and backside drain electrode.
Note: in regards to claims depending from claim 1, considered in more detail below, the Examiner considers that further limitations disclosed by Okumura in Okumura’s inventive embodiment of Figs 1-6 may be generally regarded as applicable to the conventional embodiment of Figs 17-20 of Okumura in the sense that the base structures between the conventional and the inventive embodiments may be the same, except for the pad structure difference (inventive pad structure 21 {21a and 21b of Fig 2} being regarded as conventional pad structure 121 {Fig 18} combined with conventional pad structure 121’ {Fig 19}).
Regarding claim 2, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1,
wherein the inspection region comprises a plurality of inspection regions provided in the first main surface (Shinohara; as applied to claim 1, a number of the power devices or chips to be inspected, which may be every power device or chip on the wafer; a multiple number; ¶ [0077]),
the main surface electrode comprises a plurality of main surface electrodes respectively covering the first main surface in the inspection regions (as applied to claim 1, in each inspection region of each power device or chip), and
the protective electrode comprises a plurality of protective electrodes respectively covering the main surface electrodes in the inspection regions (as applied to claim 1, in each inspection region of each power device or chip), and respectively forming the current paths between the second main surface and the protective electrodes (Shinohara; ¶ [0048]; in view of Okumura as applied to claim 1; note that ¶ [0048] describes an applied voltage and electric conduction {a current path} between a collector {second main surface (rear/bottom side) and emitter {first main surface) front/top side)}, analogous to source {front electrode} and drain {rear electrode} for a vertical MOSFET device {¶[0004]}).
Regarding claim 3, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the inspection region comprises a plurality of inspection regions allocated in the first main surface (Shinohara; as applied to claim 1, a number of the power devices or chips to be inspected, which may be every power device or chip on the wafer; a multiple number; ¶ [0077]).
Shinohara in view of Okumura does not disclose the plurality of inspection regions along a first direction and a second direction crossing the first direction; however, Shinohara discloses the plurality of power devices which comprise plurality of inspection regions are formed on the disc-shaped semiconductor wafer, and it is well-known and typical in the art for such power devices to be arranged along a first direction and a second direction crossing the first direction, which would be obvious to a person having ordinary skill in the art.
Regarding claim 4, Shinohara in view of Okumura in view of Metras discloses the semiconductor structure for inspection according to Claim 2, but does not disclose wherein the number of the plurality of inspection regions is not less than 100. However, this would have been obvious to a person having ordinary skill in the art. It is well-known and common for a semiconductor wafer to comprise not less than one hundred dice or chips, and for each die therein to comprise one or more inspection regions.
Regarding claim 5, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose wherein the semiconductor plate includes a wide-bandgap semiconductor; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description wherein a semiconductor device (semiconductor chip 10; Figs 1,2) includes a wide-bandgap semiconductor (SiC; ¶ [0066]). Accordingly, it would have been obvious that this may be the case for the semiconductor device of Okumura as applied to claim 1, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only; and therefore, the semiconductor plate of claim 1 comprising the semiconductor device of Okumura may comprise SiC.
Regarding claim 6, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose wherein the semiconductor plate includes SiC; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description wherein a semiconductor device (semiconductor chip 10; Figs 1,2) includes SiC (¶ [0066]). Accordingly, it would have been obvious that this may be the case for the semiconductor device of Okumura as applied to claim 1, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only; and therefore, the semiconductor plate of claim 1 comprising the semiconductor device of Okumura may comprise SiC.
Regarding claim 7, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (Okumura; 131; Figs 17,18) is formed as an object to be abutted with a probe needle (Okumura; 141; Fig 19; ¶ [0006-7]), and has a thickness exceeding a depth of an abutment mark of the probe needle (Okumura; analogous to probe needles 41, which are prevented from penetrating through the {source} electrode pad; ¶ [0091]).
Regarding claim 8, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (Okumura; 131; Figs 17,18) consists of a plated film (nickel (Ni) plated film and gold (Au) plated film, as cited under claim 1).
Okumura discloses the main surface electrode (Okumura; 111; Figs 17,18) contains Al (as cited under claim 1), which is not referred to as a plated film, as the protective electrode specifically is (¶ [0007]). Okumura does not specifically say the main surface electrode is other than a plated film. However, this would have been obvious to a person having ordinary skill in the art. One would have been motivated to use a non-plated film because formation methods for aluminum films (and alloys thereof, as well as other metal films), such as a deposition method (sputtering, for example), are well-known and commonly used in the art.
Regarding claim 9, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the main surface electrode includes an Al-based metal film, and the protective electrode includes an Ni film (as cited under claim 1).
Regarding claim 10, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 9, wherein the protective electrode has a laminated structure including an Au film laminated on the Ni film (as cited under claim 1).
Regarding claim 12, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (Okumura; 131; Figs 17,18) has an area less than an area of the main surface electrode (Okumura; 111; Figs 17-18) in a plan view (Okumura; as shown in Fig 17).
Regarding claim 14, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (Okumura; 131; Figs 17,18) is formed at an interval from an opening end of the opening (Okumura; 113a; Fig 1) to the main surface electrode side so that part of a wall surface of the opening is exposed (Okumura; as shown in Fig 18, 113 extends above a top surface of 131 such that a wall surface of 113 is exposed above 131).
Regarding claim 15, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose the further limitations of claim 15 in the same embodiment; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description the further limitations comprising:
a functional device (Okumura; MOSFET; ¶ [0062-64]) formed in the first main surface (upper surface of 10, adjacent to 11 of Fig 2) in the inspection region;
wherein the main surface electrode (Okumura; source electrode 11; Figs 1,2) is electrically connected to the functional device (Okumura; 11 is the source electrode of the MOSFET device), and
the protective electrode (Okumura; source pad 21, comprising 31; Figs 1,2) is electrically connected to the functional device via the main surface electrode and forms the current path between the second main surface (Okumura; lower surface of 10, adjacent to 15 of Fig 2) and the protective electrode via the functional device (current is passed between the source {21} and the drain {15; Fig 2; ¶ [0080]}; ¶ [0090]).
Accordingly, it would have been obvious that the semiconductor device of Okumura and thereby the semiconductor structure of claim 1 may further include the same, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only.
Regarding claim 16, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 15, wherein the functional device includes at least one of a diode and a transistor (MOSFET transistor, as applied to claim 15).
Regarding claim 17, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 1, further comprising:
a second main surface electrode covering the second main surface (Shinohara; another of the electrodes formed on both sides of the chip at the lower surface of W; ¶ [0033]) and forming a current path between the protective electrode and the second main surface via the semiconductor plate (Shinohara; ¶ [0014], and as applied to claim 1).
Regarding claim 18, Shinohara; in view of Okumura discloses a chuck stage inspection device comprising:
a chuck stage (Shinohara; 14; Fig 1; ¶ [0034]) having a conductive mounting surface (Shinohara; 12, comprising 22; Fig 1; ¶ [0035]);
a conductive probe needle (Shinohara; 24G; Fig 1; ¶ [0037]) with an electric signal being given between the conductive mounting surface and the conductive probe needle; and
the semiconductor structure for inspection according to Claim 1 to be arranged on the conductive mounting surface in a posture that the second main surface is to be electrically connected to the conductive mounting surface and the protective electrode is to be abutted with the conductive probe needle (Shinohara; ¶ [0046-49]; in view of Okumura as applied to claim 1; note that ¶ [0048] describes an applied voltage and electric conduction between a collector {second main surface (rear/bottom side) and emitter {first main surface ) front/top side)}, analogous to source {front electrode} and drain {rear electrode} for a vertical MOSFET device {¶[0004]}).
Regarding claim 19, Shinohara in view of Okumura discloses the chuck stage inspection device of claim 18, wherein the probe needle is arranged so that an electric current is given between the mounting surface and the probe needle (as applied to and explained under claim 18).
Regarding claim 20, Shinohara in view of Okumura discloses manufacturing method of a semiconductor device by using a semiconductor evaluation device including a chuck stage (Shinohara; 14; Fig 1; ¶ [0034]) which has a conductive mounting surface (Shinohara; 12, comprising 22; Fig 1; ¶ [0035]) and a conductive probe needle (Shinohara; 24G; Fig 1; ¶ [0037]) with an electric signal being given between the conductive mounting surface and the conductive probe needle, the manufacturing method comprising:
a step of arranging the semiconductor structure for inspection according to Claim 1 on the conductive mounting surface in a posture that the second main surface (Shinohara; lower surface of W; rear, bottom side) is to be electrically connected to the conductive mounting surface (Shinohara; ¶ [0035]); and
a step of abutting the conductive probe needle with the protective electrode (Shinohara; ¶ [0037]; in view of Okumura, as applied to claim 1), giving an electric signal between the conductive mounting surface and the conductive probe needle via the semiconductor structure for inspection Shinohara; ¶ [0046-49]; in view of Okumura as applied to claim 1; note that ¶ [0048] describes an applied voltage and electric conduction between a collector {second main surface (rear/bottom side) and emitter {first main surface ) front/top side)}, analogous to source {front electrode} and drain {rear electrode} for a vertical MOSFET device {¶[0004]}), and inspecting a state of the conductive mounting surface from an energization result (dynamic characteristic, breakdown voltage, on-resistance, for example, as described in ¶ [0048-49]) of the conductive mounting surface and the conductive probe needle (because conduction is required of the conductive mounting surface in order to achieve the conduction between upper and lower surface electrodes, the state of the conductive plate is inherently included in the measurement described in ¶ [0048-49]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shinohara; Eiichi et al. (US 20150028907; hereinafter Shinohara) in view of Okumura; Keiji (US 2020/0303269; hereinafter Okumura) and further in view of Kuwajima; Hajime et al. (JP 2019/129173; hereinafter Kuwajima).
Regarding claim 11, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to Claim 10, but does not disclose wherein the protective electrode includes a Pd film interposed between the Ni film and the Au film.
In the same field of endeavor, Kuwajima discloses a bonding pad 40 (Fig 3; ¶ [0022]) comprising a Pd film (43) interposed between a Ni film (42) and a Au film (44). Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the bonding pad structure of Kuwajima for the protective electrode of Shinohara in view of Okumura according to claim 10. One would have been motivated to do this as an alternate combination of materials for a laminated pad structure. One would have had a reasonable expectation of success because the materials and structures are well-known in the art, and because Kuwajima discloses Ni/Pd/Au and Ni/Au as alternate structures (Kuwajima; Pd may be omitted; ¶ [0022]).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Shinohara; Eiichi et al. (US 20150028907; hereinafter Shinohara) in view of Okumura; Keiji (US 2020/0303269; hereinafter Okumura) and further in view of Yamamoto; Hiroki (US 2017/0092784; hereinafter Yamamoto).
Regarding claim 21, Shinohara in view of Okumura discloses the semiconductor structure for inspection according to claim 1, but does not disclose wherein the insulating film (Okumura; 113, comprising polyimide; Fig 18) has a laminated structure including an inorganic insulating film and an organic insulating film laminated in this order from the main surface electrode side, and the protective electrode (Okumura; 131; Fig 18) is in contact with the inorganic insulating film and the organic insulating film inside the opening.
In the same field of endeavor, Yamamoto discloses a similar pad structure comprising Ni/Pd/Au electrode (5; Fig 2A; ¶ 0086]) covering an aluminum electrode (14; Fig 2A; ¶ [0062]) within an opening of an insulating film (23; Fig 2A; ¶ [0085]), wherein the insulating film has a laminated structure including an inorganic insulating film (20, comprising silicon nitride; Fig 2A; ¶ [0085]) and an organic insulating film (21, comprising a resin film including polyimide; Fig 2A; ¶ [0085]) laminated in this order from the aluminum electrode 14 side, and the Ni/Pd/Au electrode 5 is in contact with the inorganic insulating film and the organic insulating film inside the opening.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have added the inorganic insulating film of Yamamoto in similar fashion to the organic insulating film 113 of Okumura according to claim 1 to satisfy the limitations of claim 21. One may have been motivated to do this because it is a well-known material structure in the art wherein, for example, the inorganic film provides moisture protection for the underlying device and the organic film helps to buffer stress that may cause cracking of a more brittle inorganic film. One may have had a reasonable expectation of success because of the similarity in the other materials comprising the insulating layer and pad electrode structures.
Conclusion
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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