DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “wherein the inspection regions are provided in the first main surface, the main surface electrodes respectively cover the first main surface in the inspection regions, and the protective electrodes respectively cover the main surface electrodes in the inspection regions, and respectively form the current paths between the second main surface and the protective electrodes.” There is insufficient antecedent basis for this limitation in the claim, there being no plurality associated with any of the underlined terms in claim 1, from which claim 2 depends.
For the purposes of examination, claim 2 will be interpreted as “The semiconductor structure for inspection according to Claim 1,
wherein the inspection region comprises a plurality of inspection regions provided in the first main surface,
the main surface electrode comprises a plurality of main surface electrodes each respectively covering the first main surface in its corresponding inspection region, and
the protective electrode comprises a plurality of protective electrodes each respectively covering the corresponding main surface electrode in the corresponding inspection region, and each respectively forming a corresponding current path between the second main surface and the corresponding protective electrode.”
Regarding claim 4, note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim 3 recites “wherein the inspection regions are allocated in the first main surface along a first direction and a second direction crossing the first direction.” There is insufficient antecedent basis for this limitation in the claim, there being no plurality associated with the inspection region of claim 1, from which claim 3 depends.
For the purposes of examination, claim 3 will be interpreted as “The semiconductor structure for inspection according to Claim 1, wherein the inspection region comprises a plurality of inspection regions allocated in the first main surface along a first direction and a second direction crossing the first direction.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-7, 9-10, and 12-19 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Okumura; Keiji (US 2020/0303269; hereinafter Okumura).
Regarding claim 1, Okumura discloses a semiconductor structure for inspection comprising:
a semiconductor plate (semiconductor chip 10; Figs 1,2; ¶ [0065]) having a first main surface (upper surface, adjacent to 11 of Fig 2) on one side and a second main surface (lower surface, adjacent to 15 of Fig 2) on the other side;
an inspection region (active region 1; ¶ [0064-65]) provided in the first main surface;
a main surface electrode (source electrode 11; Figs 1,2; ¶ [0067-68]) having a first hardness and covering the first main surface in the inspection region; and
a protective electrode (source pad 21, comprising 31; Figs 1,2; ¶ [0071-73]) having a second hardness which exceeds the first hardness (21 {comprising 31} is formed by a material that is harder than that of 11; ¶ [0072]), covering the main surface electrode in the inspection region, and forming a current path between the second main surface and the protective electrode via the semiconductor plate ( a current path is formed between the drain electrode 15 at the second main surface and the protective electrode on the source electrode 11 via the semiconductor chip 10; Fig 2).
Regarding claim 5, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the semiconductor plate (semiconductor chip 10; Figs 1,2) includes a wide-bandgap semiconductor (SiC; ¶ [0066]).
Regarding claim 6, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the semiconductor plate (semiconductor chip 10; Figs 1,2) includes SiC (¶ [0066]).
Regarding claim 7, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (source pad 21, comprising 31; Figs 1,2) is formed as an object to be abutted with a probe needle (41; ¶ [0072]), and has a thickness exceeding a depth of an abutment mark of the probe needle (probe needles are prevented from penetrating through the {source} electrode pad; ¶ [0091]).
Regarding claim 9, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the main surface electrode (source electrode 11; Figs 1,2) includes an Al-based metal film (¶ [0069]), and the protective electrode (source pad 21, comprising 31; Figs 1,2) includes an Ni film (¶ [0074]).
Regarding claim 10, Okumura discloses the semiconductor structure for inspection according to Claim 9, wherein the protective electrode (source pad 21, comprising 31; Figs 1,2) has a laminated structure including an Au film laminated on the Ni film (Au stacked on Ni; ¶ [0074]).
Regarding claim 12, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (source pad 21, comprising 31; Figs 1,2) has an area less than an area of the main surface electrode (source electrode 11; Figs 1,2) in a plan view (as shown in Fig 1; ¶ [0071]).
Regarding claim 13, Okumura discloses the semiconductor structure for inspection according to Claim 1, further comprising:
an insulating film (13; Figs 1,2; ¶ [0063,0070]) covering a peripheral edge portion of the main surface electrode (source electrode 11; Figs 1,2) and having an opening (13a; Fig 1; ¶ [0063]) from which an inner side portion of the main surface electrode is exposed;
wherein the protective electrode (source pad 21, comprising 31; Figs 1,2) covers the main surface electrode in the opening (¶ [0077-78]).
Regarding claim 14, Okumura discloses the semiconductor structure for inspection according to Claim 13, wherein the protective electrode (source pad 21, comprising 31; Figs 1,2) is formed at an interval from an opening end of the opening (13a; Fig 1) to the main surface electrode side so that part of a wall surface of the opening is exposed (31 is formed only in the region 21a, at in interval depicted by 21b from an opening end exposing a side wall surface of 13; Fig 2; ¶ [0076-77]).
Regarding claim 15, Okumura discloses the semiconductor structure for inspection according to Claim 1, further comprising:
a functional device (MOSFET; ¶ [0062-64]) formed in the first main surface (upper surface of 10, adjacent to 11 of Fig 2) in the inspection region;
wherein the main surface electrode (source electrode 11; Figs 1,2) is electrically connected to the functional device (11 is the source electrode of the MOSFET device), and
the protective electrode (source pad 21, comprising 31; Figs 1,2) is electrically connected to the functional device via the main surface electrode and forms the current path between the second main surface (lower surface of 10, adjacent to 15 of Fig 2) and the protective electrode via the functional device (current is passed between the source {21} and the drain {15; Fig 2; ¶ [0080]}; ¶ [0090]).
Regarding claim 16, Okumura discloses the semiconductor structure for inspection according to Claim 15, wherein the functional device includes at least one of a diode and a transistor (MOSFET transistor, as applied to claim 15).
Regarding claim 17, Okumura discloses the semiconductor structure for inspection according to Claim 1, further comprising:
a second main surface electrode (drain electrode 15; Fig 2; ¶ [0080]) covering the second main surface (lower surface of 10, adjacent to 15 of Fig 2) and forming a current path between the protective electrode (source pad 21, comprising 31; Figs 1,2) and the second main surface via the semiconductor plate (semiconductor chip 10; Figs 1,2; current is passed between the source {21} and the drain {15}; ¶ [0090]).
Regarding claim 18, Okumura discloses a chuck stage inspection device comprising:
a chuck stage having a conductive mounting surface (¶ [0089]);
a conductive probe needle (41; Figs 3,4; ¶ [0072,0089]) with an electric signal being given between the mounting surface and the probe needle (voltage is applied, inducing current to pass between source {21; Fig 2} and drain {15; Fig 2}, the drain being on the conductive mounting surface necessarily to facilitate the applied voltage between source and drain; ¶ [0090]); and
the semiconductor structure for inspection according to Claim 1 to be arranged on the mounting surface in a posture that the second main surface is to be electrically connected to the mounting surface and the protective electrode is to be abutted with the probe needle (¶ [0089-90]).
Regarding claim 19, Okumura discloses the chuck stage inspection device of claim 18, wherein the probe needle (41; Figs 3,4) is arranged so that an electric current is given between the mounting surface and the probe needle (¶ [0089-90]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Metras; Hughes et al. (US 2019/0385995; hereinafter Metras).
Regarding claim 2, Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose:
wherein the inspection region comprises a plurality of inspection regions provided in the first main surface,
the main surface electrode comprises a plurality of main surface electrodes each respectively covering the first main surface in its corresponding inspection region, and
the surface electrode comprises a plurality of protective electrodes each respectively covering the corresponding main surface electrode in the corresponding inspection region, and each respectively forming a corresponding current path between the second main surface and the corresponding protective electrode.
However, electrical testing (inspection) of a plurality of individual semiconductor die arranged on a wafer (or substrate) at the wafer level, wherein an inspection region or regions is formed on each die, is known in the art. See, for example, Metras (step 1103; Fig. 11; ¶ [0091]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the semiconductor structure of Okumura may have comprised a plurality of semiconductors structures satisfying the limitation of claim 2. One would have been motivated to configure the inspection region this way in to produce a plurality of functional die and/or test die on a wafer (or substrate) each comprising one or more inspection regions (Metras; test structures; ¶ [0091]) using a wafer level manufacturing method wherein a plurality of inspection regions are formed in rows and columns on a wafer, and would have had a reasonable expectation of success because this commonly done in the art.
Regarding claim 4, Okumura in view of Metras discloses the semiconductor structure for inspection according to Claim 2, but does not disclose wherein not less than one hundred inspection regions are provided in the first main surface. However, this would have been obvious to a person having ordinary skill in the art. It is well-known and common for a wafer to comprise not less than one hundred dice, and for each die therein to comprise one or more inspection regions.
Regarding claim 3, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the inspection region is allocated in the first main surface.
Okumura does not disclose the inspection region comprises a plurality of inspection regions allocated in the first main surface along a first direction and a second direction crossing the first direction.
However, electrical testing (inspection) of a plurality of individual semiconductor die of a plurality of dice at the wafer level, wherein the dice are arranged in rows (along a first direction) and columns (along a second direction crossing the first), and wherein an inspection region or regions is formed in each die, is known in the art. See, for example, Metras (step 1103; Fig. 11; ¶ [0091]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the inspection region of Okumura may comprise a plurality of inspection regions allocated in the first main surface along a first direction and a second direction crossing the first direction.
One would have been motivated to do this in to produce a plurality of functional die and/or test die each comprising one or more inspection regions (Metras; test structures; ¶ [0091]) using a wafer level manufacturing method wherein a plurality of inspection regions are formed in rows and columns on a wafer, and would have had a reasonable expectation of success because this commonly done in the art.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura).
Regarding claim 8, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (source pad 21, comprising 31; Figs 1,2) consists of a plated film (¶ [0074]).
Okumura discloses the main surface electrode (source electrode 11; Figs 1,2) consists of a metal film (for example, aluminum or aluminum alloy; ¶ [0069]), which is not referred to as a plated film, as the protective electrode specifically is (¶ [0074]), but does not specifically say the main surface electrode is other than a plated film. However, this would have been obvious to a person having ordinary skill in the art. One would have been motivated to use a non-plated film because formation methods for aluminum films (and alloys thereof, as well as other metal films), such as a deposition method (sputtering, for example), are well-known and commonly used in the art.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Kuwajima; Hajime et al. (JP 2019/129173; hereinafter Kuwajima).
Regarding claim 11, Okumura discloses the semiconductor structure for inspection according to Claim 10, but does not disclose wherein the protective electrode includes a Pd film interposed between the Ni film and the Au film.
In the same field of endeavor, Kuwajima discloses a bonding pad 40 (Fig 3; ¶ [0022]) comprising a Pd film (43) interposed between a Ni film (42) and a Au film (44). Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the bonding pad structure of Kuwajima for the protective electrode of Okumura according to claim 10. One would have been motivated to do this as an alternate structure, and would have had a reasonable expectation of success because the materials and structures are well-known in the art, and because of the similar endeavors of Kuwajima and Okumura.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Okada Akira et al. (JP 2016/139646; hereinafter Okada).
Regarding claim 20, Okumura discloses a manufacturing method of a semiconductor device by using a semiconductor evaluation device including a chuck stage which has a conductive mounting surface and a conductive probe needle with an electric signal being given between the mounting surface and the probe needle (voltage is applied, inducing current to pass between source {21; Fig 2} and drain {15; Fig 2}, the drain being on the conductive mounting surface necessarily to facilitate the applied voltage between source and drain; ¶ [0089-90]), the manufacturing method comprising:
a step of arranging the semiconductor structure for inspection according to Claim 1 on the mounting surface in a posture that the second main surface (lower surface of 10, adjacent to 15 of Fig 2) is to be electrically connected to the mounting surface (semiconductor chip 10 is placed on the conductive stage, the drain electrode 15 on the back surface of the chip {Fig 2; ¶ [0013]} necessarily contacting the mounting surface; ¶ [0089]); and
a step of abutting the probe needle (41; Figs 3,4) with the protective electrode (¶ [0089]), giving an electric signal between the mounting surface and the probe needle via the semiconductor structure for inspection (voltage is applied to the source pad 21, inducing current to pass between source {21} and drain {15}, the drain being on the conductive mounting surface necessarily to facilitate the applied voltage between source and drain in order for current flow therebetween; ¶ [0090]).
Okumura does not disclose inspecting a state of the mounting surface from an energization result of the mounting surface and the probe needle.
In the same field of endeavor, Okada discloses a semiconductor evaluation device (1; Fig 1; ¶ [0022-23]) comprising a chuck stage (6; Fig 1; ¶ [0023]) with a mounting surface, and a probe needle (contact probe 9; Fig 1; ¶ [0033]); and, inspecting a state of the mounting surface from an energization result of the mounting surface (from a contact resistance between the mounting surface and a resistor 34 of the inspection jig 32 {Embodiment 3, comprising the resistor 34 on a silicon wafer 33}; ¶ [0089,0033]) and the probe needle (¶ [0051-55,0090-94]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the semiconductor structure for inspection according to claim 1 with the inspecting a state of the mounting surface of Okada, using the semiconductor structure for inspection according to claim 1, and measuring an electrical parameter of the semiconductor structure for inspection in place of a contact resistance of a resistor of an inspection jig as taught by Okada. One may have been motivated to do this in order to utilization the semiconductor structure for inspection according to claim 1 for the additional purpose of inspecting a state of the mounting surface, and eliminate the need for a separate structure as taught by Okada for this purpose, thereby saving cost and/or manufacturing complexity. One would have had a reasonable expectation of success because of the similarity of the semiconductor evaluation device and endeavors of Okada and Okumura.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817