DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR STRUCTURE FOR INSPECTION HAVING A CURRENT PATH BETWEEN OPPOSITE SIDES OF A SEMICONDUCT PLATE AND A PROTECTIVE ELECTRODE ON ONE SIDE OF THE SEMICONDUCTOR PLATE, CHUCK STAGE INSPECTION DEVICE, AND MANUFACTURING METHOD OF A SEMINCONDUCTOR DEVICE
Response to Amendment
The Amendment filed May 11, 2026 has been entered. Applicant' s amendments to claims 2-4 have been considered, and the 35 U.S.C. 112(b) rejections are hereby withdrawn.
Claims 1-12, 14-20, and newly added claim 21 are pending in the application.
Response to Arguments
Applicant’s arguments, see pages 8-16 of Remarks, filed May 11, 2026, with respect to the rejections of claims under 1, 5-7, 9-10, and 12-19 under 35 U.S.C 102(a)(1) and of claims 2-4, 8, 11, and 20 35 U.S.C 103 have been fully considered in view of the Amendment and some of the arguments are persuasive.
Specifically, the argument that the protective electrode of Okumura does not cover the entire area of the inner side portion of the main surface electrode inside the opening of an insulating film is persuasive in regards to the cited embodiment of Okumura. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of another embodiment of Okumura in combination with the previously cited references.
As further explanation regarding the Amended claim 1, the Examiner has considered Applicant’s argument that modification of Okumura to extend the plating film 31 to cover the entire inner side of source electrode 11 within the opening 31a would be inconsistent with the teaching of Okumura, but considers it moot in view of additional viewpoints: The argument omits Okumura’s disclosure in the background of the invention of a plating film covering the entire inner side of a source electrode within an opening of an insulating film. The Examiner considers that the embodiment of the invention of Figs 1-6 of Okumura may be regarded as a combination of a first disclosed conventional embodiment of Figs 17-20 and a second disclosed conventional embodiment of Figs 17, 21-23 wherein the pad structures 121 (Fig 18) and 121’ (Fig 21) have been combined within one opening of an insulating film (13 {Figs 1-2}; 113 {Figs 17,18,21}). That is, the rejection of record was based upon Okumura’s modification of known conventional structures, and the Examiner considers that Amended claim 1 is unpatentable over at least one of the known conventional structures disclosed by Okumura, and detailed in the rejections below.
Further, while Okumura states that it is impossible to use the single source pad 121 of Figs 17-20 in optimal states for two or more means of differing purposes (¶ [0060]), that does mean that such use for two or more means of differing purposes is required; that is, the conventional embodiment of Figs 17-20 is of use on its own, even in view of Okumura’s invention, for a case where two or more different uses are not required.
Regarding the argument with respect to the rejection of claim 2, that the test pads of Metras are not analogous to the protective electrode of amended claim 1, the Examiner did not intend to rely upon the structure of the test pads of Metras, but only the row and column arrangement on a wafer. In the updated rejections below, the additional reference Thalmann is added for additional support.
Regarding the argument with respect to the rejection of claim 20, that the fact of inspection jig 2 of Okada being different from the semiconductor structure of Okumura renders the combination of references non-obvious, the argument is not persuasive. The inventive concept of Okada that is combined with Okumura is the ability to inspect a state of a mounting surface from an energization result of the mounting surface and a probe needle (see page 11 of the prior Office Action). Okada discloses that if an energization result may be monitored between a probe needle and a mounting surface, then the state of a mounting surface may be inspected. The Examiner contends that it would be obvious to a person having ordinary skill in the art that a different energization result from the energization result disclosed by Okada may be used; that is a different parameter from a different structure may be monitored between a probe needle and mounting structure, and be relevant to Okada’s disclosure of the monitor being used to inspect the state of a mounting surface.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-10, 12 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura).
Regarding claim 1, Okumura discloses a semiconductor structure for inspection comprising:
a semiconductor plate (semiconductor chip 110; Figs 17,18; ¶ [0005]) having a first main surface (upper surface of 110, adjacent to 111 of Fig 18) on one side and a second main surface (lower surface of 110; Fig 18) on the other side;
an inspection region (active region 101; Fig 17; ¶ [0005]) provided in the first main surface;
a main surface electrode (source electrode 111, containing aluminum (Al); Figs 17,18; ¶ [0005-6]) having a first hardness and covering the first main surface in the inspection region;
an insulating film (polyimide layer 113; Figs 17,18; ¶ [0005]) covering a peripheral edge of the main surface electrode over an entire circumference of the peripheral edge (shown in Fig 17; ¶ [0006]), and partitioning an opening that has a wall surface extending along the entire circumference of the peripheral edge and exposes an inner side portion of the main surface electrode (shown in Figs 17,18); and
a protective electrode (131, formed by a nickel (Ni) plating film and a gold (Au) plating film sequentially stacked, Figs 17,18; ¶ [0007]) having a second hardness, covering the entire area of the inner side portion of the main surface electrode inside the opening in the inspection region (Figs 17,18; ¶ [0006-7]), and forming a current path between the second main surface and the protective electrode via the semiconductor plate (during screening, large current can be passed through 110 to 131; ¶ [0007]).
Okumura does not specifically disclose in this conventional semiconductor embodiment that the second hardness of the second electrode exceeds the first hardness of the first electrode. However, it would have been obvious to a person having ordinary skill in the art that the disclosed plating film 131 formed of Ni/Au would have a hardness which exceeds that of source electrode 111 that contains Al, because it is well known in the art that Ni, at least, has a hardness greater than Al, and because the greater hardness is one reason well-known in the art for the use of Ni as a pad plating film.
In addition, Okumura discloses in an embodiment of the invention a similar structure wherein a plating film 31 (analogous to 131, and which also may be formed of Au stacked on Ni; Figs 1,2; ¶ [0072-74]) has a second hardness which exceeds a first hardness of a first electrode 11 (analogous to 111, and also containing Al ; Figs 1,2; ¶ [0068-69, 0072]). The Examiner considers that the embodiment of the invention of Figs 1-6, comprising this similar structure, may be regarded as a combination of a first disclosed conventional embodiment of Figs 17-20 and a second disclosed conventional embodiment of Figs 17, 21-23 wherein the pad structures 121 (Fig 18) and 121’ (Fig 21) that have been combined within one opening of an insulating film (13 {Figs 1-2}; 113 {Figs 17,18,21}). In this regard, the disclosed hardness relationship of the Figs 1-6 embodiment is considered obvious in the portion corresponding to the Figs 17-20 embodiment.
Alternately, for a person not needing or wanting to use Al bonding wire with the electrode (using, for example, using a terminal pin such as 133 of Fig 20; ¶ [0058]), it would be obvious to use a plating film comprising Ni and/or Au (Al is soft as compared to Ni or Au; ¶ [0059]) to prevent cracks in the electrode pad during screening (Okumura; ¶ [0058-59]). In this case, one may arrive at the invention of claim 1 from the inventive embodiment of Figs 1-6 by omitting an unneeded portion 21b (Figs 1-3) to reduce manufacturing steps and complexity.
Note: in regards to claims depending from claim 1, considered in more detail below, the Examiner considers that further limitations disclosed by Okumura in Okumura’s inventive embodiment of Figs 1-6 may generally regarded as applicable to the conventional embodiment of Figs 17-20 of Okumura in the sense that the base structures between the conventional and the inventive embodiments may be the same, except for the pad structure difference (inventive pad structure 21 {21a and 21b of Fig 2} being regarded as conventional pad structure 121 {Fig 18} combined with conventional pad structure 121’ {Fig 19}).
Regarding claim 5, Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose wherein the semiconductor plate (semiconductor chip 110; Figs 17,18) of the conventional embodiment includes a wide-bandgap semiconductor; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description wherein a semiconductor plate (semiconductor chip 10; Figs 1,2) includes a wide-bandgap semiconductor (SiC; ¶ [0066]). Accordingly, it would have been obvious that this may be the case for the semiconductor structure of claim 1, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only.
Regarding claim 6, Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose wherein the semiconductor plate (semiconductor chip 110; Figs 17,18) of the conventional embodiment includes SiC; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description wherein a semiconductor plate (semiconductor chip 10; Figs 1,2) includes SiC (¶ [0066]). Accordingly, it would have been obvious that this may be the case for the semiconductor structure of claim 1, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only.
Regarding claim 7, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (131; Figs 17,18) is formed as an object to be abutted with a probe needle (141; Fig 19; ¶ [0006-7]), and has a thickness exceeding a depth of an abutment mark of the probe needle (analogous to probe needles 41, which are prevented from penetrating through the {source} electrode pad; ¶ [0091]).
Regarding claim 8, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (131; Figs 17,18) consists of a plated film (nickel (Ni) plated film and gold (Au) plated film, as cited under claim 1).
Okumura discloses the main surface electrode (111; Figs 17,18) contains Al (as cited under claim 1), which is not referred to as a plated film, as the protective electrode specifically is (¶ [0007]). Okumura does not specifically say the main surface electrode is other than a plated film. However, this would have been obvious to a person having ordinary skill in the art. One would have been motivated to use a non-plated film because formation methods for aluminum films (and alloys thereof, as well as other metal films), such as a deposition method (sputtering, for example), are well-known and commonly used in the art.
Regarding claim 9, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the main surface electrode includes an Al-based metal film, and the protective electrode includes an Ni film (as cited under claim 1).
Regarding claim 10, Okumura discloses the semiconductor structure for inspection according to Claim 9, wherein the protective electrode has a laminated structure including an Au film laminated on the Ni film (as cited under claim 1).
Regarding claim 12, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (131; Figs 17,18) has an area less than an area of the main surface electrode (111; Figs 17-18) in a plan view (as shown in Fig 17).
Regarding claim 14, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the protective electrode (131; Figs 17,18) is formed at an interval from an opening end of the opening (113a; Fig 1) to the main surface electrode side so that part of a wall surface of the opening is exposed (as shown in Fig 18, 113 extends above a top surface of 131 such that a wall surface of 113 is exposed above 121).
Regarding claim 15, Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose the further limitations of claim 15 in the same embodiment; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description the further limitations comprising:
a functional device (MOSFET; ¶ [0062-64]) formed in the first main surface (upper surface of 10, adjacent to 11 of Fig 2) in the inspection region;
wherein the main surface electrode (source electrode 11; Figs 1,2) is electrically connected to the functional device (11 is the source electrode of the MOSFET device), and
the protective electrode (source pad 21, comprising 31; Figs 1,2) is electrically connected to the functional device via the main surface electrode and forms the current path between the second main surface (lower surface of 10, adjacent to 15 of Fig 2) and the protective electrode via the functional device (current is passed between the source {21} and the drain {15; Fig 2; ¶ [0080]}; ¶ [0090]).
Accordingly, it would have been obvious that the semiconductor structure of claim 1 may further include the same, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only.
Regarding claim 16, Okumura discloses the semiconductor structure for inspection according to Claim 15, wherein the functional device includes at least one of a diode and a transistor (MOSFET transistor, as applied to claim 15).
Regarding claim 17, Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose the further limitation of claim 17 in the same embodiment; however, Okumura discloses in the inventive embodiment of Figs 1-2 and associated description the further limitations comprising:
a second main surface electrode (drain electrode 15; Fig 2; ¶ [0080]) covering the second main surface (lower surface of 10, adjacent to 15 of Fig 2) and forming a current path between the protective electrode (source pad 21, comprising 31; Figs 1,2) and the second main surface via the semiconductor plate (semiconductor chip 10; Figs 1,2; current is passed between the source {21} and the drain {15}; ¶ [0090]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the drain electrode 15 with the embodiment of claim 1. One would have been motivated do to this in order to form a drain electrode of a transistor to enable a functional device, as was done in the inventive embodiment. One would have had a reasonable expectation of success because this is a well-known structure in the art and not precluded by the pad structure difference between the inventive and conventional embodiments disclosed by Okumura.
Regarding claim 18, Okumura discloses a chuck stage inspection device comprising:
a chuck stage having a conductive mounting surface (¶ [0089]);
a conductive probe needle (141; Fig 19; ¶ [0006]) with an electric signal being given between the conductive mounting surface and the conductive probe needle (voltage is applied to the source pad 121 {Fig 19} via the probe needle 141, and current passed between a source and drain (¶ [0006]).
Okumura does not disclose the semiconductor structure for inspection according to Claim 1 to be arranged on the conductive mounting surface in a posture that the second main surface is to be electrically connected to the conductive mounting surface and the conductive protective electrode is to be abutted with the probe needle; however, Okumura discloses in this in the inventive embodiment of Figs 1-2 and associated description (¶ [0089-90]).
Accordingly, it would have been obvious that the semiconductor structure for inspection according to Claim 1 may be arranged in the same fashion, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only.
Regarding claim 19, Okumura discloses the chuck stage inspection device of claim 18, wherein the probe needle (141; Fig 19) is arranged so that an electric current is given between the mounting surface and the probe needle (¶ [0089-90]).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Metras; Hughes et al. (US 2019/0385995; hereinafter Metras) and Thalmann; Erwin et al. (US 2015/0377954; hereinafter Thalmann).
Regarding claim 2, Okumura discloses the semiconductor structure for inspection according to Claim 1, but does not disclose:
wherein the inspection region comprises a plurality of inspection regions provided in the first main surface, the main surface electrode comprises a plurality of main surface electrodes respectively covering the first main surface in the inspection regions, and
the protective electrode comprises a plurality of protective electrodes respectively covering the main surface electrodes in the inspection regions, and respectively forming the current paths between the second main surface and the protective electrodes.
However, the reason this is not disclosed as applied to claim 1 is because the semiconductor plate (semiconductor chip 110; Figs 17,18) as applied to claim 1 is the result of a semiconductor wafer being diced into individual die (chips) which constitute a plurality of semiconductor plates, analogous to that described for another embodiment (¶ [0088]). In fact, the limitations of claim 2 exist on the wafer prior to dicing, when the entire wafer is considered as the semiconductor plate rather than the semiconductor chip 110, each chip comprising one of the plurality.
Further, electrical testing (inspection) of a plurality of individual semiconductor die arranged on a wafer (or substrate) at the wafer level, wherein an inspection region or regions is formed on each die, is known in the art. See, for example, Metras (step 1103; Fig. 11; ¶ [0091]) or Thalmann (Figs 1-2; ¶ [0019-24])
Accordingly, it would have been obvious to a person having ordinary skill in the art that the semiconductor structure of Okumura may comprise a plurality of semiconductors structures satisfying the limitation of claim 2 when considered in wafer form, for example, for wafer-level testing. One would have been motivated to configure the inspection region this way in to produce a plurality of functional die and/or test die on a wafer (or substrate) each comprising one or more inspection regions (Metras; test structures; ¶ [0091]; or, Thalmann; transistor structures or other structures in which at least one electrical contact is on a first face of a semiconductor die and at least one other electrical contact is on a second face of the semiconductor die; ¶ [0009]) using a wafer level manufacturing method wherein a plurality of inspection regions are formed in rows and columns on a wafer, and would have had a reasonable expectation of success because this commonly done in the art.
Regarding claim 3, Okumura discloses the semiconductor structure for inspection according to Claim 1, wherein the inspection region is allocated in the first main surface.
Okumura does not disclose the inspection region comprises a plurality of inspection regions allocated in the first main surface along a first direction and a second direction crossing the first direction.
However, electrical testing (inspection) of a plurality of individual semiconductor die of a plurality of dice at the wafer level, wherein the dice are arranged in rows (along a first direction) and columns (along a second direction crossing the first), and wherein an inspection region or regions is formed in each die, is known in the art. See, for example, Metras (Figs 9,11; ¶ [0080, 0091]) or Thalmann (Figs 1,2; ¶ [0002,0019,0024]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the inspection region of Okumura may comprise a plurality of inspection regions allocated in the first main surface along a first direction and a second direction crossing the first direction.
One would have been motivated to do this in to produce a plurality of functional die and/or test die each comprising one or more inspection regions (Metras; test structures; ¶ [0091]; or, Thalmann; transistor structures or other structures in which at least one electrical contact is on a first face of a semiconductor die and at least one other electrical contact is on a second face of the semiconductor die; ¶ [0009]) using a wafer level manufacturing method wherein a plurality of inspection regions are formed in rows and columns on a wafer, and would have had a reasonable expectation of success because this commonly done in the art.
Regarding claim 4, Okumura in view of Metras discloses the semiconductor structure for inspection according to Claim 2, but does not disclose wherein the number of the plurality of inspection regions is not less than 100. However, this would have been obvious to a person having ordinary skill in the art. It is well-known and common for a wafer to comprise not less than one hundred dice, and for each die therein to comprise one or more inspection regions.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Kuwajima; Hajime et al. (JP 2019/129173; hereinafter Kuwajima).
Regarding claim 11, Okumura discloses the semiconductor structure for inspection according to Claim 10, but does not disclose wherein the protective electrode includes a Pd film interposed between the Ni film and the Au film.
In the same field of endeavor, Kuwajima discloses a bonding pad 40 (Fig 3; ¶ [0022]) comprising a Pd film (43) interposed between a Ni film (42) and a Au film (44). Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the bonding pad structure of Kuwajima for the protective electrode of Okumura according to claim 10. One would have been motivated to do this as an alternate combination of materials for a laminated pad structure, and would have had a reasonable expectation of success because the materials and structures are well-known in the art, and because Kuwajima discloses Ni/Pd/Au and Ni/Au as alternate structures (Kuwajima; Pd may be omitted; ¶ [0022]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Okada Akira et al. (JP 2016/139646; hereinafter Okada).
Regarding claim 20, Okumura discloses a manufacturing method of a semiconductor device by using a semiconductor evaluation device including a chuck stage which has a conductive mounting surface and a conductive probe needle with an electric signal being given between the conductive mounting surface and the conductive probe needle (voltage is applied, inducing current to pass between source {21; Fig 2} and drain {15; Fig 2}, the drain being on the conductive mounting surface necessarily to facilitate the applied voltage between source and drain; ¶ [0089-90]), the manufacturing method comprising:
a step of arranging a semiconductor structure for inspection (according to the conventional embodiment of Figs 1-2) on the mounting surface in a posture that the second main surface (lower surface of 10, adjacent to 15 of Fig 2) is to be electrically connected to the mounting surface (semiconductor chip 10 is placed on the conductive stage, the drain electrode 15 on the back surface of the chip {Fig 2; ¶ [0013]} necessarily contacting the mounting surface; ¶ [0089]); and
a step of abutting the probe needle (41; Figs 3,4) with the protective electrode (¶ [0089]), giving an electric signal between the mounting surface and the probe needle via the semiconductor structure for inspection (voltage is applied to the source pad 21, inducing current to pass between source {21} and drain {15}, the drain being on the conductive mounting surface necessarily to facilitate the applied voltage between source and drain in order for current flow therebetween; ¶ [0090]).
Okumura does not disclose:
(1) the semiconductor structure for inspection is the semiconductor structure for inspection according to Claim 1; however, it would have been obvious that the semiconductor structure for inspection according to Claim 1 may be arranged in the same fashion, as explained under claim 1, that Okumura’s inventive embodiment may be regarded as a modification of the conventional embodiment, the modification being a combination of pad structures, only; and,
(2) inspecting a state of the mounting surface from an energization result of the mounting surface and the probe needle.
In the same field of endeavor, Okada discloses a semiconductor evaluation device (1; Fig 1; ¶ [0022-23]) comprising a chuck stage (6; Fig 1; ¶ [0023]) with a mounting surface, and a probe needle (contact probe 9; Fig 1; ¶ [0033]); and, inspecting a state of the mounting surface from an energization result of the mounting surface (from a contact resistance between the mounting surface and a resistor 34 of the inspection jig 32 {Embodiment 3, comprising the resistor 34 on a silicon wafer 33}; ¶ [0089,0033]) and the probe needle (¶ [0051-55,0090-94]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the semiconductor structure for inspection according to claim 1 with the inspecting a state of the mounting surface of Okada, using the semiconductor structure for inspection according to claim 1, and measuring an electrical parameter of the semiconductor structure for inspection in place of a contact resistance of a resistor of an inspection jig as taught by Okada. One may have been motivated to do this in order to utilize the semiconductor structure for inspection according to claim 1 for the additional purpose of inspecting a state of the mounting surface, and eliminate the need for a separate structure as taught by Okada for this purpose, thereby saving cost and/or manufacturing complexity. One would have had a reasonable expectation of success because both Okada and Okumura describe measuring an electrical signal between a conductive mounting surface and a conductive probe needle.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Okumura; Keiji (US 2020/0303269; hereinafter Okumura) in view of Yamamoto; Hiroki (US 2017/0092784; hereinafter Yamamoto).
Regarding claim 21, Okumura discloses the semiconductor structure for inspection according to claim 1, but does not disclose wherein the insulating film (113, comprising polyimide; Fig 18; ¶ [0005]) has a laminated structure including an inorganic insulating film and an organic insulating film laminated in this order from the main surface electrode side, and the protective electrode (121; Fig 18) is in contact with the inorganic insulating film and the organic insulating film inside the opening.
In the same field of endeavor, Yamamoto discloses a similar pad structure comprising Ni/Pd/Au electrode (5; Fig 2A; ¶ 0086]) covering an aluminum electrode (13; Fig 2A; ¶ [0062]) within an opening of an insulating film (23; Fig 2A; ¶ [0085]), wherein the insulating film has a laminated structure including an inorganic insulating film (20, comprising silicon nitride; Fig 2A; ¶ [0085]) and an organic insulating film (21, comprising a resin film including polyimide; Fig 2A; ¶ [0085]) laminated in this order from the aluminum electrode 13 side, and the Ni/Pd/Au electrode 5 is in contact with the inorganic insulating film and the organic insulating film inside the opening.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have added the inorganic insulating film of Yamamoto in similar fashion to the organic insulating film 113 of Okumura according to claim 1 to satisfy the limitations of claim 15. One may have been motivated to do this because it is a well-known material structure in the art wherein, for example, the inorganic film provides moisture protection for the underlying device and the organic film helps to buffer stress that may cause cracking of a more brittle inorganic film. One may have had a reasonable expectation of success because of the similarity in the other materials comprising the insulating layer and pad electrode structures.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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