DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/474,372, application filed on 09/26/2023. Claims 1-11 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 09/26/2023 and 02/20/2026, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-2, 4-5, 7 and 10-11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Abbas et al. (US PG Pub No. 2022/0092246).
7. With respect to claim 1, Abbas teaches:
A macro model of a semiconductor integrated circuit device for use on a circuit design simulator (see macro model, Abstract; using macro model for simulation, para 39; see simulations for real-time model, para 13), comprising:
a plurality of functional blocks (see one or more macro blocks, para 15; see compiler based design of analog blocks, para 24) configured to approximately or equivalently represent characteristics of the semiconductor integrated circuit device on the circuit design simulator (analog circuit design a circuit design representation of analog macro, para 47; prototype providing same functionality, para 48); and
a characteristics setting block configured to set (see parameter data set, para 45; setting parameters such as those of supply voltage, temperature conditions, etc, para 46; see combination of parameter values, para 46), using array data derived from evaluation measurement data obtained by actual measurement with the semiconductor integrated circuit device (see input/output parameters of simulation matrix/array, para 14; see simulation data set, para 45; data set of parameters like power, voltage, and temperature, par 45), at least one internal parameter out of a plurality of internal parameters set in the plurality of functional blocks (configuring parameters of analog macro blocks to behavioral/architectural implementation of analog circuitry, para 16).
8. With respect to claim 2, Abbas teaches:
The macro model according to claim 1, wherein the characteristics setting block is configured
to receive at least one operation condition parameter related to operation conditions of the semiconductor integrated circuit device (see temperature conditions, para 14; see outputs exposed to different processes based on testing, such as supply voltage, temperature conditions, para 23), and
to set the at least one internal parameter such that the characteristics of the semiconductor integrated circuit device on the circuit design simulator reflect the at least one operation condition parameter (see selected analog macro from derivation module, macro of op-amp, same functionality, based on independent/dependent parameters, para 39).
9. With respect to claim 4, Abbas teaches:
The macro model according to claim 2, wherein the at least one operation condition parameter includes at least one of a supply voltage, a reference voltage, an ambient temperature, an internal temperature, and a load current with respect to the semiconductor integrated circuit device (see parameter data set, para 45; setting parameters such as those of supply voltage, temperature conditions, etc, para 46; see combination of parameter values, para 46).
10. With respect to claim 5, Abbas teaches:
The macro model according to claim 1, wherein the characteristics setting block is configured to receive a characteristics variation parameter related to characteristics variation of the semiconductor integrated circuit device (see dataset, parameter variations, para 45-46),
to generate characteristics variation array data reflecting the characteristics variation based on the array data and the characteristics variation parameter (see dataset, parameter variations, para 45-46), and
to set the at least one internal parameter using the characteristics variation array data (see parameter variation, supply voltage, temperature conditions, para 45-46).
11. With respect to claim 7, Abbas teaches:
The macro model according to claim 1, wherein the semiconductor integrated circuit device is an operational amplifier (see op-amp, para 39).
12. With respect to claim 10, Abbas teaches:
A circuit design simulation program to be executed by a computer including a calculation portion to make the computer function as a circuit design simulator, the program including the macro model according to claim 1, the program making the computer simulate a response of a semiconductor integrated circuit device on the circuit design simulator (see circuit simulation, see rejection of claim 1 above).
13. With respect to claim 11, Abbas teaches:
A circuit design simulator that is implemented by a computer executing the circuit design simulation program according to claim 10 (see simulation program, quick design prototyping and programmable design adaption, para 22-25).
Allowable Subject Matter
14. Claims 3, 6 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
15. With respect to claim 3, the prior art made of record fails to teach the combination of steps recited in independent claim 3, including the following particular combination of steps as recited in claim 3, as follows:
wherein the array data is a one- or multi-dimensional lookup table in which the at least one operation condition parameter is associated with the at least one internal parameter.
16. With respect to claim 6, the prior art made of record fails to teach the combination of steps recited in independent claim 6, including the following particular combination of steps as recited in claim 6, as follows:
wherein the characteristics setting block is configured to interpolate, for the at least one internal parameter, an intermediate value of two set values derived from the array data.
17. With respect to claims 8-9, the prior art made of record fails to teach the combination of steps recited in independent claim 8, including the following particular combination of steps as recited in claim 8, as follows:
wherein the plurality of functional blocks include a power supply block that represents a DC gain of the operational amplifier, and a filter block that represents a band width of the operational amplifier.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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