DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/26/2023, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-6, 8-10, and 12, is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 12016176) herein referred to as Jang in view of Hong et al. (US 20130015429) herein referred to as Hong.
As to claim 1, Jang discloses a semiconductor memory device, comprising:
a substrate (100 substrate, Fig 20); a bit line (420 conduction line , Fig 20) on the substrate and extending in a first direction;
a channel accommodating insulating layer (412 lower insulating layer, Fig. 20) positioned on the substrate (100 substrate, Fig 20), and
defining a channel trench (trench fills the channel layer 430, Fig. 20) extending in a second direction crossing the first direction;
a channel layer (430 channel layer, Fig 20) extending along a bottom surface and a side surface of the channel trench (trench fills the channel layer 430, Fig. 20) and contacting the bit line (420 conduction line , Fig 20);
a word line (440 word line Fig.20) in the channel trench (trench fills the channel layer 430, Fig. 20) and extending in the second direction;
a gate insulating layer (450 gate insulating layer, Fig 20) separating the channel layer (430 channel layer, Fig 20) from the word line (440 word line Fig.20); and
a capacitor structure (capacitor 480, Fig. 21) on the channel layer (430 channel layer, Fig 20) and electrically connected to the channel layer (430 channel layer, Fig 20), wherein
Jang does not disclose:
“the channel layer has a double layer structure of an oxide semiconductor layer and a first graphene layer”
However, Hong does teach the channel layer further includes
“the channel layer ([0051] graphene channel 76, Hong) has a double layer structure of an oxide semiconductor layer and a first graphene layer ([0051] oxide layer 78 opposite the graphene channel”, Hong)
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to include a graphene, oxide, graphene multilayer on the channel layer of the Jang device such as is used in the Hong device. It is well known in the industry that the work function of graphene depends on the number of layers. You at least need two layers of graphene to build a field-effect tunneling transistor. Normally due to the very small band gap, graphene cannot be used solely, you need some other materials as transport barriers between the layers, and the materials used will determine the work function, from that point conventional rules apply. Having an additional graphene layer, with an oxide layer in between two graphene layers increases scalability ([0045] Hong) and, therefore, increases storage capacity for a given die area.
As to claims 2 and 9, the Jang/Hong combination discloses the semiconductor memory device of claim 1 and claim 8 respectively, as discussed above, wherein the channel layer further includes:
a second graphene layer ([0051] graphene electrode 76, Fig. 4, Hong), and
the oxide semiconductor layer ([0051] oxide layer 78 opposite the graphene channel 76, Hong) is interposed between the first graphene layer ([0051] graphene channel 80, Hong) and
the second graphene layer ([0051] graphene electrode 76, Fig. 4, Hong),See ([0007] “In another embodiment, the GFM device includes a substrate, a graphene channel layer on a surface of the substrate, and a tunnel oxide layer on a surface of the graphene channel layer opposite the substrate.”; Hong)
As to claims 3, 6, 10 and 12, the Jang/Hong combination discloses the semiconductor memory device and method of claims 2, 5, 9, 8 , respectively, as discussed above, and further discloses wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO) (col 21, lines 46-47 “the channel layer 430 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In.sub.xGa.sub.yZn.sub.zO,” Jang.
As to claim 5, the Jang/Hong combination discloses the semiconductor memory device of claim 1, as discussed above, and further discloses wherein:
a first surface of the oxide semiconductor layer is in electrical contact with the bit line (420 conduction line , Fig 20), and
a second surface opposite to the first surface of the oxide semiconductor layer is in electrical contact ([0051] “Connections to and from a source and drain of the ground select gate 54 are made by on-chip interconnects 92 and 94.”) with the first graphene layer.
As to claim 8, the Jang/Hong combination discloses a semiconductor memory device, comprising:
a substrate (100 substrate, Fig 20, Jang); a bit line (420 ST, Fig 20, Jang) on the substrate and extending in a first direction;
a word line (440 word line Fig.20, Jang) on the substrate, electrically insulated from the bit line (420 conduction line , Fig 20, Jang), and extending in a second direction crossing the first direction;
a channel layer (430 channel layer, Fig 20, Jang) on the substrate, in electrical contact with the bit line, and insulated from the word line; and
a capacitor structure (capacitor 480, Fig. 21, Jang) electrically connected to the channel layer, wherein
the channel layer (430 channel layer, Fig 20 Jang) includes: an oxide semiconductor layer in electrical contact with the bit line (420 conduction line , Fig 20); and
a first graphene layer ([0051] graphene channel 80, Hong) on the oxide semiconductor layer ([0051] oxide layer 78, Hong).
Claim(s) 4, 7, 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 12016176) herein referred to as Jang in view of Hong et al. (US 20130015429) herein referred to as Hong and further in view of Kim et al. (US 20140272350) herein referred to as Kim.
As to claims 4, 7, 11 and 13 the Jang/Hong combination discloses the semiconductor memory device and method of claims 2, 5, 9 and 8 respectively, as discussed above, and further discloses wherein:
a thickness of each of the first and second graphene layers is about 0.3 nm to about 2 nm.
Jang and Hong as combined teach the device and methods of claims 4, 7, 11, and 13. However, the combined references do not explicitly teach the thickness of the graphene layers.
Kim teaches a first and second graphene layer with thickness between about 0.3 nm to about 2 nm. See [0043, Kim] “The first graphene layer has a thickness of about 0.4 nm to about 5 nm, preferably from about 0.4 nm to about 2 nm.” and [0070, Kim], “The second graphene layer may have a thickness from about 0.4 nm to about 5 nm, preferably from about 0.4 nm to about 2 nm.”
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). It would have been obvious to make the thickness of the first and second graphene layers about 0.3 nm to about 2 nm as in the prior art Kim.
Furthermore, the Applicant has not shown that thickness of the first graphene layer of about 0.3 nm, and the thickness of the second graphene layer of about 2 nm are novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made, to optimize the graphene layer thickness in the Jang/Hong device as in the Kim device so as to be able to control key electronic properties like work function, charge transfer, and light absorption. Optimizing graphene thickness directly impacts device performance, significantly improving the work function, increasing the open circuit voltage, and enhancing the energy conversion efficiency. Since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.
Claim(s) 14, 15 ,18, 16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 12016176) herein referred to as Jang in view of Hong et al. (US 20130015429) herein referred to as Hong and further in view of Torres, Alonso Elias (US 20240213352) herein referred to as Torres.
As to claim 14, the Jang/Hong combination discloses a method of manufacturing a semiconductor memory device, the method comprising:
forming a bit line (420 conduction line, Fig 20, Jang) extending in a first direction on a substrate (100 substrate, Fig 20, Jang);
forming a channel accommodating insulating layer (412 lower insulating layer, Fig. 20, Jang) on the substrate (100 substrate, Fig 20, Jang) to define a channel trench (trench fills the channel layer 430, Fig. 20, Jang), wherein
the channel trench exposes at least a portion of the bit line (420 conduction line , Fig 20, Jang) and extending in a second direction crossing the first direction;
stacking an oxide semiconductor layer ([0051] oxide layer 78, Hong )on the substrate (100 substrate, Fig 20, Jang) and the channel accommodating insulating layer (412 lower insulating layer, Fig. 20, Jang);
stacking a first graphene layer ([0051] graphene channel 80, Hong) on the oxide semiconductor layer ([0051] oxide layer 78 opposite the graphene channel 76, Hong);
forming a photoresist film on the first graphene layer; (col 13 lines 15-18 “The upper surface of the lower peri interlayer insulating film 290 may be placed on the same plane as the lower etching stop film 250 extending along the upper surface of the peri gate structure 240ST”, Jang. )
forming a word line (440 word line Fig.20, Jang) extending in the second direction;
forming a gate insulating layer (450 gate insulating layer, Fig 20, Jang) positioned between the channel layer (430 channel layer, Fig 20, Jang) and the word line (440 word line Fig.20, Jang); and
forming a capacitor structure (capacitor 480, Fig. 21, Jang) positioned on the channel layer (430 channel layer, Fig 20, Jang) and electrically connected to the channel layer.
Since Jang does not have a multilayer graphene, oxide, graphene channel layer, Jang does not disclose an etching process for a multilayer graphene layer:
“forming a channel layer by etching the first graphene layer (obvious) and the oxide semiconductor layer by using the photoresist film as a mask;” and
“exposing the first graphene layer of the channel layer by removing the photoresist film;”
However, Torres does teach:
forming a channel layer by etching the first graphene layer and the oxide semiconductor layer by using the photoresist film as a mask [0059, Torres] “In sum, the mask 103 formed over the graphene layer(s) is used to etch away unwanted areas of the graphene layer(s), and an etch is then used to pattern the graphene and thereby define the channel(s). After etching, the mask 103 is removed following a conventional suitable technique. The pattern of the graphene channel(s) is thus transferred.”
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, that the etching process of Jang includes etching more than one layer such as the etching process of the Torres device forms a channel by etching the graphene and oxide layer by using a photoresist. The use and removal of a photoresist film is a well-known process in the industry for transferring circuit patterns, and acting as a protective stencil that defines where etching or deposition occurs so as to fabricate an industrially tested and accepted device/process/material.)
As to claim 15, the Jang/Hong/Torres combination discloses the method of claim 14, as discussed above, and further discloses wherein further comprising:
stacking a second graphene layer ([0051] graphene electrode 90, Fig. 4, Hong), on the substrate and the channel accommodating insulating layer, wherein
the oxide semiconductor layer is stacked on the second graphene layer ([0051] oxide layer 78 opposite the graphene channel 76, Hong), wherein
the forming of the channel layer further includes
etching the second graphene layer, and wherein the second graphene layer is in contact with the bit line.(Hong Fig. 4 shows multilayer graphene oxide graphene in a channel. Combined Jang/ Hong/Torres device includes the channel layers of the Hong device in the Jang structure as disclosed above.)
As to claim 18, the Jang/Hong/Torres combination discloses the method of claim 14, as discussed above, and further discloses wherein:
a first surface of the oxide semiconductor layer (oxide layer 78, Hong) is in physical contact with the bit line (420 conduction line, Fig 20 Jang), and
a second surface opposite to the first surface of the oxide semiconductor layer is in physical contact with the first graphene layer (Fig. 4 , Hong).
As to claims 16 and 19, the Jang/Hong/Torres combination discloses the method of claim 14, as discussed above, and further discloses wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO) (col 21, lines 46-47 “the channel layer 430 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In.sub.xGa.sub.yZn.sub.zO,” Jang.
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US 12016176) herein referred to as Jang in view of Hong et al. (US 20130015429) herein referred to as Hong and further in view of Torres, Alonso Elias (US 20240213352) herein referred to as Torres and further in view of Kim et al. (US 20140272350) herein referred to as Kim.
As to claims 17 and 20 the Jang/Hong/Torres combination discloses the semiconductor memory device and method of claims 15 and 14 respectively, as discussed above, and further discloses wherein:
a thickness of each of the first and second graphene layers is about 0.3 nm to about 2 nm.
Jang/Hong/Torres as combined teach the device and methods of claims 17 and 20. However, the combined references do not explicitly teach the thickness of the graphene layers.
However, Kim teaches a first and second graphene layer with thickness between about 0.3 nm to about 2 nm. See [0043] of Kim, “The first graphene layer has a thickness of about 0.4 nm to about 5 nm, preferably from about 0.4 nm to about 2 nm.” and [0070], “The second graphene layer may have a thickness from about 0.4 nm to about 5 nm, preferably from about 0.4 nm to about 2 nm.
See Examiner’s rejection of claims 4, 7, 11 and 13 above.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897