DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/02/2026 has been entered. Claims 1-22 are currently pending in the application. Claims 13 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/27/2024. Claims 1-12, 14 and 16-22 are considered below.
Response to Arguments
In response to the rejection of claim 1 under 35 U.S.C. 103 in the previous Office action dated 02/02/2026, Applicant has amended independent claim 1 and provided on pages 11-13 of the amendment an argument, which has been fully considered but it is not persuasive. In order to best respond, it is suggested the Applicant to see the below detailed rejection of the currently amended claim 1.
In response to the rejection of claim 18 under 35 U.S.C. 103 in the previous Office action, Applicant has amended independent claim 18 and provided on pages 14-15 of the amendment an argument, which has been fully considered but it is not persuasive. In order to best respond, it is suggested the Applicant to see the below detailed rejection of the currently amended claim 18.
Allowable Subject Matter
The indicated allowability of claims 7-12 is withdrawn in light of the rejection under 35 U.S.C. 112(b) follow.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7-12 are rejected under 35 U.S.C. 112(b), as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
As per claim 7, this claim recites a limitation, “the second node disposed between the first capacitor and the second node” in lines 12-13. Since it is unclear what the above underlined limitation is required, it is considered that the invention is not clearly defined.
As per claims 8-12, these claims are therefore rejected for the reason set forth in claim 7 above.
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-6, 14, 16, 17, 21 and 22 are rejected under 35 U.S.C. 112(a), as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Note that, in order to satisfy its burden under the written description requirement, a patent application must disclose the full scope of the claim. Univ. of Rochester v. G.D. Searle & Co., 358 F.3d 916, 920 (Fed. Cir. 2004) (The purpose of the written description requirement is to “ensure that the scope of the right to exclude, as set forth in the claims, does not overreach the scope of the inventor’s contribution to the field of art as described in the patent specification.”).
As per claim 1, this claim recites a limitation, “a second capacitor directly connected to the second node” in line 12, which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure, specifically Fig. 2, explicitly discloses a second capacitor [C2] directly connected to the first power line [PL1/VDD] and an unlabeled node, which is between the second node [N5] and the first capacitor [C1]. Also see claim 1 in the amendment filed 11/19/2025, wherein a third node corresponds to the unlabeled node. In other words, the original disclosure does not explicitly disclose “a second capacitor [C2] directly connected to the second node [N5]” of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
In addition to claim 1, this claim further recites a limitation, “a fourth transistor electrically connected to a third node” in line 15. This limitation includes features, (i) “a fourth transistor directly-and-electrically connected to a third node and a compensation voltage line” and (ii) “a fourth transistor always/permanently electrically connected to a third node and a compensation voltage line,” which were not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure, specifically Fig. 2, discloses that a fourth transistor [T9] is indirectly-and-electrically connected to a third node [N3] via the transistor [T1], the fourth transistor [T9] is not electrically connected to a third node [N3] when the transistor [T1] is turned off, and the fourth transistor [T9] is only electrically connected to a third node [N3] when the transistor [T1] is turned on. In other words, the original disclosure does not explicitly provide a support for the above features of the above underlined limitation of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
In addition to claim 1, this claim further recites a limitation, “a first emission control transistor connected to the third node” in lines 18-19. This limitation includes a feature, “a first emission control transistor directly connected to the third node,” which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure, specifically Fig. 2, discloses a first emission control transistor [T5] indirectly connected to the third node [N3] via the transistor T1. In other words, the original disclosure does not explicitly provide a support for the above feature of the above underlined limitation of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
In addition to claim 1, this claim further recites a limitation, “wherein the second node is directly connected to the first capacitor and the second capacitor” in last two lines, which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. The original disclosure, specifically Fig. 2, explicitly discloses the second node [N5] indirectly connected to the first capacitor [C1] and the second capacitor [C2] via an unlabeled node, which is between the second node [N5], the first capacitor [C1], and the second capacitor [C2]. In other words, the original disclosure does not explicitly disclose “the second node [N5] directly connected to the first capacitor [C1] and the second capacitor [C2]” of this claim, so as to reasonably convey to one skilled in the relevant art that the inventor(s), at the time the application was filed, had possession of the claimed invention. Further, see the above bolded note.
As per claims 2-6, 14, 16, 17, 21 and 22, these claims are therefore rejected for the reason set forth in claim 1 above.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
FIRST SET OF REJECTIONS:
Claims 1-6, 14, 16, 17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112951164A cited in IDS; see the corresponding US 2023/0351955 A1 for the following citations) in view of Kim et al. (US 2021/0065628 A1; hereinafter Kim.)
As per claim 1, Zhang discloses a display device (see at least Fig. 3A; ¶ 3) comprising:
a display panel including a pixel (see at least ¶ 84;) and
a panel driver that drives the display panel (see at least Figs. 1C, 4C, disclosing a panel driver providing various signals [Data, WR, EM1-EM3] and voltages [V1, Vcm, OVDD, VI1, VI2],) wherein
the pixel (see at least any of Figs. 1C, 4C) includes:
a light emitting device [D1] electrically connected to a first power line [OVDD] (see at least Fig. 1C;)
a first transistor [Td] electrically connected to a cathode of the light emitting device [D1] and operating depending on a potential of a first node [G] (see at least Fig. 1C;)
a second transistor [Tda] electrically connected between a data line [Data] and a second node [a node between elements [Tda, Ts2, C3] (see at least Fig. 1C;)
a third transistor [Ts2] electrically connected between a reference voltage line [VI] and the second node (see at least Fig. 1C;)
a first capacitor [C3] electrically connected between the first node [G] and the second node (see at least Fig. 1C;)
a fourth transistor electrically connected to a third node and a compensation voltage line (see at least Fig. 1C, disclosing a fourth transistor Ts1 electrically connected to a third node [S] via the elements [G, C1] and electrically connected to a compensation voltage line Vcm,) the third node [S] being different from the first node [G] and the second node (see at least Fig. 1C;) and
a first emission control transistor [Te2] connected to the cathode of the light emitting device and the third node (see at least Fig. 1C, disclosing a first emission control transistor [Te2] [[directly]] connected to the cathode of the light emitting device D1 and [[indirectly]] connected to the third node [S] via the transistor Td,) and
wherein the second node [the node between elements [Tda, Ts2, C3]] is directly connected to each of the second transistor [Tda], the third transistor [Ts2], and the first capacitor [C3] (see at least Fig. 1C.)
Accordingly, Zhang discloses all limitations of this claim except for a second capacitor, as claimed.
However, in the same field of endeavor, Kim discloses a related display device (see at least Fig. 1) comprising a display panel [10] including a plurality of pixels [PXs], wherein each pixel includes a second capacitor [C1] directly connected to the first power line [ELVDD] and the second node [N1] (see at least Fig. 3) and wherein the second node [N1] is directly connected to each of the second transistor [T2], the third transistor [T8], the first capacitor [C2], and the second capacitor [C1] (see at least Fig. 3,) thereby sufficiently securing time for compensating for a threshold voltage of the first/ driving transistor (see ¶ 7.)
Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the pixel of the Zhang reference to include a second capacitor, in view of the teaching in the Kim reference, to obtain the predictable result of sufficiently securing time for compensating for a threshold voltage of the first/ driving transistor.
As per claim 2, Zhang discloses the first power line [OVDD] directly connected to an anode of the light emitting device [D1] (see at least Fig. 1C.)
As per claim 3, Zhang discloses the first transistor [Td] being an N-type transistor (see at least Fig. 1C.)
As per claim 4, Zhang discloses the first transistor including: a first electrode electrically connected to the light emitting device [D1]; a second electrode electrically connected to a second power line [OVSS]; and a gate electrically connected to the first node [G] (see at least Fig. 1C)
and the fourth transistor [Ts1] electrically connected to the first electrode (see at least Fig. 1C; note that "electrically connected" does not require "directly connected".)
As per claim 5, Zhang discloses the fourth transistor [Ts1] including: a first electrode electrically connected to the compensation voltage line [Vcm]; a gate electrically connected to a compensation scan line {EM2]; and a second electrode electrically connected to the first electrode of the first transistor [Td] (see at least Fig. 1C; note that "electrically connected" does not require "directly connected".)
As per claim 6, Zhang discloses the pixel further including: a second emission control transistor [Te1] electrically connected between the second electrode and the second power line [OVSS] (see at least Fig. 1C.)
As per claim 14, Zhang discloses the display panel including a plurality of light-emitting devices and a plurality of pixel driving circuits (see at least ¶ 5) and the panel driver including a scan driver outputting a scan signal [WR] to the corresponding pixel and a data driver outputting a data signal [Data] to the corresponding data line (see at least Fig. 1C; ¶¶ 29-30,) but is silent to the scan driver that outputs a plurality of scan signals to a plurality of scan lines.
However, Kim further discloses the panel driver [20-40] including a scan driver [20] that is electrically connected to a plurality of scan lines [SL11 …SL3n; Fig. 1] and outputs a plurality of scan signals to the plurality of scan lines (see at least Figs. 1, 3, 6;) and a data driver [30] that is electrically connected to a plurality of data lines [DL1-DLm] and outputs a plurality of data signals to the corresponding data lines, respectively (see at least Figs. 1, 3, 6,) thereby sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel (see at least ¶ 7.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to recognize that Kim remedies for the above-discussed deficiency of Zhang or to further modify the above modified display device of Zhang to obtain the scan driver outputting a plurality of scan signals to a plurality of scan lines, in view of the teaching in the Kim reference, to obtain the predictable result of sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel.
As per claim 16, Zhang discloses a data writing period [S3] in which the second transistor [Tda] is turned on and a compensation period [S2] in which the fourth transistor [Ts1] is turned on do not overlap each other (see at least Fig. 2A, specifically the waveform of signals em2 and wr.)
As per claim 17, Zhang discloses the compensation period [S2] appearing before the data writing period [S3] and the fourth transistor [Ts1] turned off during the data writing period [s3] (see at least Fig. 2A, specifically the waveform of signals em2 and wr.)
As per claim 22, Zhang does not teach a first initialization transistor, as claimed. However, Kim further discloses a first initialization transistor [T4] electrically connected between a first initialization voltage line [VINT] and the first node [N2], to initialize the gate electrode of the driving transistor and the anode electrode of the organic light emitting diode LD to the initialization voltage (see at least Fig. 3; ¶ 94: last 4 lines,) thereby sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel (see at least ¶ 7.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to further include a first initialization transistor in the pixel of the above modified display device of Zhang, in view of the teaching in the Kim reference, to obtain the predictable result of sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over by Jeong (US 7,773,054 B2) in view of Yang et al. (US 2021/0358405 A1; hereinafter Yang) and Zhang.
As per claim 18, Jeong discloses a display device (see at least Fig. 2) comprising:
a display panel [100] including a pixel [110] (see at least Fig. 2;) and
a panel driver [200, 300] that drives the display panel [110], and including a scan driver [300] electrically connected to a plurality of scan lines [S3.1-S3.N] (see at least Figs. 2, 9,) wherein
the pixel (see Fig. 9) includes:
a light emitting device [OLED] including:
an anode electrically connected to a power line [Vdd] (see at least Fig. 9;) and
a cathode electrically connected to a first electrode of a first transistor [M6"], wherein the first transistor operates depending on a potential of a first node [a node between the elements [M6", M2", Cvth], wherein the first node is electrically connected to a gate of the first transistor (see at least Fig. 9;)
a second transistor [M1"] electrically connected between a data line [Dm] and the first node (see at least Fig. 9;) and
a first capacitor [Cvth] electrically connected between the second transistor [M1"] and the first node (see at least Fig. 9.) and
Accordingly, Jeong discloses all limitations of this claim except for an additional transistor and a first emission control transistor, as claimed.
However, in the same field of endeavor, Yang discloses a related display device [1] (see at least Fig. 14) comprising a display panel [11] including a plurality of pixels [P] (see Fig. 14,) wherein the pixel comprising an additional transistor [T4] electrically and directly connected between the first electrode of the first transistor [T1] and a compensation voltage line [Vref] to directly apply a compensation voltage [Vref] to the first electrode of the first transistor [T1] (see at least Fig. 13,) thereby eliminating the problem of the short-term after image that may occur due to the hysteresis effect of the display device (see at least ¶ 78.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the pixel of the Jeong reference to include an additional transistor, in view of the teaching in the Yang reference, to obtain the predictable result of eliminating the problem of the short-term after image that may occur due to the hysteresis effect of the display device.
The above combination of Jeong and Yang obviously renders all limitations of this claim, but is silent to a first emission control transistor, as claimed.
However, in the same field of endeavor, Zhang discloses a related display device (see at least Fig. 3A; ¶ 3) comprising: a first emission control transistor [Te2] directly connected to the cathode of the light emitting device [D1] and the first electrode of the first transistor [Td] (see at least Fig. 1C,) thereby reducing an influence of the voltage end [OVDD] (OVDD corresponding to Vdd of Jeong shown in Fig. 9) and on a voltage stored in the capacitor [C1] (C1 corresponding to Cvth” of Jeong shown in Fig. 9) (see at least ¶ 39.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the pixel of the Jeong reference to include a first emission control transistor directly connected to the cathode of the light emitting device and the first transistor, in view of the teaching in the Zhang reference, to obtain the predictable result of reducing an influence of the voltage [Vdd] and on a voltage stored in the capacitor [Cvth”].
Further, since Zhang discloses [[the first electrode of]] the first emission control transistor [Te2] directly connected to the cathode of the light emitting device [D1] and [[the second electrode of]] the first emission control transistor [Te2] directly connected to the first electrode of the first/driving transistor [Td] (see Zhang Fig. 1C) and Yang discloses [[the second electrode of]] the additional transistor [T4] directly connected the first electrode of the first/driving transistor [T1], the above combination of Jeong, Yang, and Zhang obviously renders [[the second electrode of]] the first emission control transistor directly connected to the first electrode of the first/driving transistor and [[the second electrode of]] the additional transistor, as required by the limitation in last two lines of claim 18.
Accordingly, the above combination of Jeong, Yang, and Zhang obviously renders all limitations of this claim.
As per claim 19, the above modified Jeong in view of Yang and Zhang obviously renders wherein: the additional transistor is turned on depending on a compensation scan signal applied from the scan driver (see Yang at least Figs. 13-14, disclosing the additional transistor T4 turned on depending on a compensation scan signal Comp applied from the scan driver including the element 12 and the element generating the compensation scan signal Comp,) and the second transistor is turned on depending on a data writing scan signal applied from the scan driver (see Jeong at least Figs. 2, 9, disclosing the second transistor [M1"] turned on depending on a data writing scan signal [S3.n] applied from the scan driver.)
As per claim 20, the above modified Jeong in view of Yang and Zhang obviously renders the additional transistor turned on before the second transistor and turned off during a period in which the second transistor is turned on (see Yang at least Figs. 8, 9, 13; ¶¶ 77-81, disclosing the additional transistor T4 turned on before the second transistor [T2] and turned off during a period in which the second transistor [T2] is turned on; note that Figs. 8-9 discuss the P-type of the transistor T4 which is turned on by the low level of the compensation signal Comp while Fig. 13 uses the N-type of the transistor T4 which is turned on by the high level of the compensation signal Comp.)
SECOND SET OF REJECTIONS:
Claims 1-6, 14 and 16-22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (CN 112951164A cited in IDS; see the corresponding US 2023/0351955 A1 for the following citations) in view of Yang et al. (US 2021/0358405 A1; hereinafter Yang) and Kim et al. (US 2021/0065628 A1; hereinafter Kim.)
As per claim 1, Zhang discloses a display device (see at least Fig. 3A; ¶ 3) comprising:
a display panel including a pixel (see at least ¶ 84;) and
a panel driver that drives the display panel (see at least Figs. 1C, 4C, disclosing a panel driver providing various signals [Data, WR, EM1-EM3] and voltages [V1, Vcm, OVDD, VI1, VI2],) wherein
the pixel (see at least any of Figs. 1C, 4C) includes:
a light emitting device [D1] electrically connected to a first power line [OVDD] (see at least Fig. 1C;)
a first transistor [Td] electrically connected to a cathode of the light emitting device [D1] and operating depending on a potential of a first node [G] (see at least Fig. 1C;)
a second transistor [Tda] electrically connected between a data line [Data] and a second node [a node between elements [Tda, Ts2, C3]] (see at least Fig. 1C;)
a third transistor [Ts2] electrically connected between a reference voltage line [VI] and the second node (see at least Fig. 1C;)
a first capacitor [C3] electrically connected between the first node [G] and the second node (see at least Fig. 1C;)
a third node [S] being different from the first node [G] and the second node [the node between elements [Tda, Ts2, C3]] (see at least Fig. 1C;) and
a first emission control transistor [Te2] connected to the cathode of the light emitting device and the third node [S] (see at least Fig. 1C, disclosing a first emission control transistor [Te2] [[directly]] connected to the cathode of the light emitting device D1 and [[indirectly]] connected to the third node [S] via the transistor Td,) and
wherein the second node [the node between elements [Tda, Ts2, C3]] is directly connected to each of the second transistor [Tda], the third transistor [Ts2], and the first capacitor [C3] (see at least Fig. 1C.)
Accordingly, Zhang discloses all limitations of this claim except for a fourth transistor and a second capacitor, as claimed.
Regarding to the missing fourth transistor, in the same field of endeavor, Yang discloses a related display device [1] (see at least Fig. 14) comprising a display panel [11] including a plurality of pixels [P] (see Fig. 14,) wherein the pixel comprising a fourth transistor [T4] electrically connected to a third node [N2] and electrically-and-directly connected a compensation voltage line [Vref] and the first electrode of the first transistor [T1] to directly apply a compensation voltage [Vref] to the first electrode of the first transistor [T1] (see at least Fig. 13,) thereby eliminating the problem of the short-term after image that may occur due to the hysteresis effect of the display device (see at least ¶ 78.)
Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the pixel of the Zhang reference to include a fourth transistor, in view of the teaching in the Yang reference, to obtain the predictable result of eliminating the problem of the short-term after image that may occur due to the hysteresis effect of the display device.
Accordingly, the above modified Zhang in view of Yang obviously renders all limitations of this claim except for a second capacitor, as claimed.
Regarding to the missing second capacitor, in the same field of endeavor, Kim discloses a related display device (see at least Fig. 1) comprising a display panel [10] including a plurality of pixels [PXs], wherein each pixel includes a second capacitor [C1] directly connected to the second node [N1] and the first power line [ELVDDL] (see Fig. 3) to charge a charge corresponding to the threshold voltage of the first/ driving transistor (see ¶ 80,) thereby sufficiently securing time for compensating for a threshold voltage of the first/ driving transistor (see ¶ 7.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the pixel of the Zhang reference to include a second capacitor, in view of the teaching in the Kim reference, to obtain the predictable result of sufficiently securing time for compensating for a threshold voltage of the first/ driving transistor.
Accordingly, the above modified Zhang in view of Yang and Kim obviously renders all limitations of this claim, as claimed.
As per claim 2, Zhang discloses the first power line [OVDD] directly connected to an anode of the light emitting device [D1] (see at least Fig. 1C.)
As per claim 3, Zhang discloses the first transistor [Td] being an N-type transistor (see at least Fig. 1C.)
As per claim 4, the above modified Zhang obviously renders the first transistor including: a first electrode electrically connected to the light emitting device [D1]; a second electrode electrically connected to a second power line [OVSS]; and a gate electrically connected to the first node [G] (see Zhang at least Fig. 1C) and the fourth transistor electrically connected to the first electrode (see Yang least Fig. 13, disclosing the fourth transistor T4 electrically connected to the first electrode of the first/driving transistor T1.)
As per claim 5, the above modified Zhang obviously renders the fourth transistor including: a first electrode electrically connected to the compensation voltage line; a gate electrically connected to a compensation scan line; and a second electrode electrically connected to the first electrode of the first transistor (see Yang at least Fig. 13, disclosing the fourth transistor T4 including: a first electrode electrically connected to the compensation voltage line Vref; a gate electrically connected to a compensation scan line Comp; and a second electrode electrically connected to the first electrode of the first transistor T1.)
As per claim 6, Zhang discloses the pixel further including: a second emission control transistor [Te1] electrically connected between the second electrode and the second power line [OVSS] (see at least Fig. 1C.)
As per claim 14, Zhang further discloses the display panel including a plurality of light-emitting devices and a plurality of pixel driving circuits (see Zhang at least ¶ 5) and the panel driver including a scan driver outputting a scan signal [WR] to the corresponding pixel and a data driver outputting a data signal [Data] to the corresponding data line (see Zhang at least Fig. 1C; ¶¶ 29-30,) but is silent to the scan driver that outputs a plurality of scan signals to a plurality of scan lines.
However, Kim further discloses the panel driver [20-40] including a scan driver [20] that is electrically connected to a plurality of scan lines [SL11 …SL3n; Fig. 1] and outputs a plurality of scan signals to the plurality of scan lines (see at least Figs. 1, 3, 6;) and a data driver [30] that is electrically connected to a plurality of data lines [DL1-DLm] and outputs a plurality of data signals to the corresponding data lines, respectively (see at least Figs. 1, 3, 6,) thereby sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel (see at least ¶ 7.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to recognize that Kim remedies for the above-discussed deficiency of Zhang or to further modify the above modified display device of Zhang to obtain the scan driver outputting a plurality of scan signals to a plurality of scan lines, in view of the teaching in the Kim reference, to obtain the predictable result of sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel.
As per claim 16, the above modified Zhang in view of Yang and Kim obviously renders a data writing period in which the second transistor is turned on and a compensation period in which the fourth transistor is turned on do not overlap each other (see Zhang at least Fig. 2A, specifically the waveform of signals em2 and wr; Yang at least Figs. 8, 9, 13.)
As per claim 17, the above modified Zhang in view of Yang and Kim obviously renders the compensation period appearing before the data writing period and the fourth transistor turned off during the data writing period [s3] (see Zhang at least Fig. 2A, specifically the waveform of signals em2 and wr; Yang at least Figs. 8, 9, 13.)
As per claim 18, see the rejection of claims 1 and 14 for similar limitations. Note that an additional transistor of claim 18 corresponds to a fourth transistor of claim 1. The above modified Zhang in view of Yang and Kim obviously renders the additional/four transistor electrically-and-directly connected between the first electrode of the first transistor and a compensation voltage line to directly apply a compensation voltage to the first electrode of the first transistor (see the discussion in the rejection of claim 1; or Yang at least Fig. 13, disclosing the additional transistor T4 electrically-and-directly connected between the first electrode of the first transistor T1 and a compensation voltage line Vref to directly apply a compensation voltage to the first electrode of the first transistor T1.)
Further, since Zhang discloses [[the first electrode of]] the first emission control transistor [Te2] directly connected to the cathode of the light emitting device [D1] and [[the second electrode of]] the first emission control transistor [Te2] directly connected to the first electrode of the first/driving transistor [Td] (see Zhang Fig. 1C) and Yang discloses [[the second electrode of]] the additional transistor [T4] directly connected the first electrode of the first/driving transistor [T1], the above combination of Zhang, Yang, and Kim obviously renders [[the second electrode of]] the first emission control transistor directly connected to the first electrode of the first/driving transistor and [[the second electrode of]] the additional transistor, as required by the limitation in last two lines of claim 18.
As per claim 19, the above modified Zhang in view of Yang and Kim obviously renders the additional transistor turned on depending on a compensation scan signal applied from the scan driver and the second transistor turned on depending on a data writing scan signal applied from the scan driver (see Yang at least Figs. 8, 9, 13.)
As per claim 20, the above modified Zhang in view of Yang and Kim obviously renders the additional transistor turned on before the second transistor and turned off during a period in which the second transistor is turned on (see Yang at least Figs. 8, 9, 13.)
As per claim 21, the above modified Zhang in view of Yang and Kim obviously renders the fourth transistor directly connected to the first electrode of the first transistor (see Yang at least Fig. 13, disclosing the fourth transistor T4 directly connected to the first electrode of the first transistor T1.)
As per claim 22, Zhang does not teach a first initialization transistor, as claimed. However, Kim further discloses a first initialization transistor [T4] electrically connected between a first initialization voltage line [VINT] and the first node [N2], to initialize the gate electrode of the driving transistor and the anode electrode of the organic light emitting diode LD to the initialization voltage (see at least Fig. 3; ¶ 94: last 4 lines,) thereby sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel (see at least ¶ 7.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to further include a first initialization transistor in the pixel of the above modified display device of Zhang, in view of the teaching in the Kim reference, to obtain the predictable result of sufficiently securing time for compensating for a threshold voltage of a driving transistor for each pixel.
Conclusion
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626
Prosecution Insights