DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II directed to claims 1-7 and 14-20 in the reply filed on 01/26/2026 is acknowledged. No claims are cancelled. No claims were amended. No claims were added. Claim 8-13 are directed to non-elected species there by withdrawn. As a result, claims 1-20 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, and 14-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHANEMOUGAME, Daniel (US 20220102362 A1) “CHANEMOUGAME et al.”.
Regarding Independent Claim 1, CHANEMOUGAME et al. Fig. 1-15 discloses, a semiconductor structure (“a CFET SRAM bit cell made with two stacked levels of transistors.” ¶ [0049]), comprising:
a first pass gate (“pass-gate (PG), e.g., PG1 and PG2” ¶ [0042]) oriented along a first line (Fig. 3 shows first pass gate along a first line);
a first inverter (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]) in line with the first line (Figs. 3-4 show INV2 is in line with PG1 and INV1 is in line with PG2), comprising:
a first channel region (nano-sheet region of PD1 in Fig. 4B);
a second channel region (nano-sheet region of PU1 in Fig. 4B) stacked above the first channel region (“nano-sheet stacked on nano-sheet.” ¶ [0038]); and
an inverter gate around the first channel region and the second channel region (“A vertical common gate between NMOS and PMOS in FIG. 1D” ¶ [0038]; “INV1, formed by the bottom NMOS first pull-down transistor PD1 and the top PMOS first pull-up transistor PU1 can be identified by its common gate G.” ¶ [0050]),
comprising a gate extension (“two vertical shapes (PC) representing the gates” ¶ [0049]) above the pass gate PG1 (Fig. 4A shows PC is above PG1).
Regarding Claim 2, CHANEMOUGAME et al. discloses the limitations of claim 1. CHANEMOUGAME et al. further discloses, further comprising:
a second inverter (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]); and
a cross couple electrically connected between the gate extension and a source/drain (S/D) of the second inverter (“FIG. 13A shows formation of the cross-couple 3/3 including metallization of the cross-couple. Now that the XC etch is completed, the cavity created is filled by metal (W, Ru, Co, Cu) as shown in FIGS. 13B-E. As illustrated on the different cross-sections A-B in FIG. 13B, A in FIG. 13C, B in FIG. 13D, and C in FIG. 13E, when the metal is dropped into the cavity, it connects together the source or drain of the second pass-gate PG2, the source or drain of each device of the second inverter INV2 and the gate of first inverter INV1, therefore effectively forming the cross-couple XC.” ¶ [0079]).
Regarding Claim 3, CHANEMOUGAME et al. discloses the limitations of claim 2. CHANEMOUGAME et al. further discloses, wherein the second inverter is oriented along a second line different from the first line (Fig. 4 shows INV1 and INV2 are along different lines).
Regarding Claim 4. CHANEMOUGAME et al. discloses the limitations of claim 1. CHANEMOUGAME et al. further discloses, wherein the first channel region comprises nanosheet layers (nano-sheet region of PD1 in Fig. 4B).
Regarding Claim 5. CHANEMOUGAME et al. discloses the limitations of claim 1. CHANEMOUGAME et al. further discloses, wherein the inverter gate is confined laterally by a gate spacer (Fig. 4B shows the gate G is confined by gate spacer).
Regarding Claim 6. CHANEMOUGAME et al. discloses the limitations of claim 1. CHANEMOUGAME et al. further discloses, further comprising a separating insulator separating the inverter gate from the pass gate (“separation pillars SP” ¶ [0059]; “the gates of the pass-gates, e.g., PG2, are vertically separated from the gates of the PMOS devices on top by the fifth fill material F5. The fifth fill material F5 may be dielectric material.” ¶ [0060]).
Regarding Claim 7. CHANEMOUGAME et al. discloses the limitations of claim 6. CHANEMOUGAME et al. fig 5B further discloses, wherein the separating insulator (SP & F5) comprises a first vertical section (Lower portion of SP in Fig. 5B below F5), a first horizontal section (F5 in Fig 5B), and a second vertical section (Upper portion of SP in Fig. 5B above F5).
Regarding Independent Claim 14, CHANEMOUGAME et al. Figs. 1-15 discloses a semiconductor structure (“a CFET SRAM bit cell made with two stacked levels of transistors.” ¶ [0049]), comprising:
an inverter gate configured to activate an inverter gate transistor (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]);
a pass gate (“pass-gate (PG), e.g., PG1 and PG2” ¶ [0042]); and
a separating insulator between the inverter gate and the pass gate (“separation pillars SP” ¶ [0059]; “the gates of the pass-gates, e.g., PG2, are vertically separated from the gates of the PMOS devices on top by the fifth fill material F5. The fifth fill material F5 may be dielectric material.” ¶ [0060]), wherein the inverter gate comprises a gate extension (“two vertical shapes (PC) representing the gates” ¶ [0049]) extending horizontally along a first line in a location vertically above the pass gate and the separating insulator (Fig. 4A shows PC is above PG1 and insulator).
Regarding Claim 15, CHANEMOUGAME et al. discloses the limitations of claim 14. CHANEMOUGAME et al. further discloses, further comprising:
a second inverter (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]); and
a cross couple electrically connected between the gate extension and a source/drain (S/D) of the second inverter (“FIG. 13A shows formation of the cross-couple 3/3 including metallization of the cross-couple. Now that the XC etch is completed, the cavity created is filled by metal (W, Ru, Co, Cu) as shown in FIGS. 13B-E. As illustrated on the different cross-sections A-B in FIG. 13B, A in FIG. 13C, B in FIG. 13D, and C in FIG. 13E, when the metal is dropped into the cavity, it connects together the source or drain of the second pass-gate PG2, the source or drain of each device of the second inverter INV2 and the gate of first inverter INV1, therefore effectively forming the cross-couple XC.” ¶ [0079]).
Regarding Claim 16, CHANEMOUGAME et al. discloses the limitations of claim 15. CHANEMOUGAME et al. further discloses, wherein the second inverter is oriented along a second line different from the first line (Fig. 4 shows INV1 and INV2 are along different lines).
Regarding Claim 17, CHANEMOUGAME et al. discloses the limitations of claim 14. CHANEMOUGAME et al. further discloses, wherein the inverter gate is confined laterally by a gate spacer (Fig. 4B shows the gate G is confined by gate spacer).
Regarding Claim 18, CHANEMOUGAME et al. discloses the limitations of claim 14. CHANEMOUGAME et al. fig 5B further discloses, wherein the separating insulator (SP & F5) comprises a first vertical section (Lower portion of SP in Fig. 5B below F5), a first horizontal section (F5 in Fig 5B), and a second vertical section (Upper portion of SP in Fig. 5B above F5).
Regarding Claim 19. CHANEMOUGAME et al. discloses the limitations of claim 14. CHANEMOUGAME et al. fig 5B further discloses, wherein the inverter gate transistor (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]) comprises a first channel region (nano-sheet region of PD1 in Fig. 4B);
a second channel region (nano-sheet region of PU1 in Fig. 4B) stacked above the first channel region (“nano-sheet stacked on nano-sheet.” ¶ [0038]).
Regarding Claim 20. CHANEMOUGAME et al. discloses the limitations of claim 19. CHANEMOUGAME et al. fig 4B further discloses, wherein the first channel region comprises a pull-down transistor (PD1 in Fig. 4B) and the second channel region comprises a pull up transistor (PU1 in Fig. 4B).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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