DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species II directed to claims 1-7 and 14-20 in the reply filed on 01/26/2026 is acknowledged. No claims are cancelled. No claims were amended. No claims were added. Claim 8-13 are directed to non-elected species there by withdrawn. As a result, claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments, see page 6-9 of the Remarks document, filed 07/06/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made over CHANEMOUGAME, Daniel (US 20220102362 A1) “CHANEMOUGAME et al.” in view of Smith, Jeffrey (US 20180040695 A1) “Smith et al.”.
Specification
The disclosure is objected to because of the following informalities:
The specification ¶ [0045] stated “The first horizontal etch gap 146 expands along the first line with the second word line 106b”. However, element 146 is the first channel region. The first horizontal etch gap is 154.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recited “a first pass gate oriented along a first line” and “a gate extension above the pass gate”. There is insufficient antecedent basis for these limitations in the claim. Claim 1, does not recite “a pass gate” before reciting “the pass gate”. Therefore, it is unclear, and the scope of the claim is unclear.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1-7, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over CHANEMOUGAME, Daniel (US 20220102362 A1) “CHANEMOUGAME et al.” in view of Smith, Jeffrey (US 20180040695 A1) “Smith et al.”.
Regarding Independent Claim 1, CHANEMOUGAME et al. Fig. 1-15 discloses, a semiconductor structure (“a CFET SRAM bit cell made with two stacked levels of transistors.” ¶ [0049]), comprising:
a first pass gate PG2 oriented along a first line (Figs. 4A-4B & 5B shows pass gate PG2 on gate line PC, “one gate line will run across multiple bit cells located in the same row (gate orientation) of the array” ¶ [0054]);
a first inverter INV1 (“the gate for the first inverter INV1 is separated from the adjacent cell's inverter, and is also separated from the second pass-gate PG2” ¶ [0042]) in line with the first line (Figs. 5B show INV2 is in line with PG1 and INV1 is in line with PG2), comprising:
a first channel region (nano-sheet region of PD1 in Figs. 4B & 15B; “the first inverter, e.g., INV1, formed by the bottom NMOS first pull-down transistor PD1 and the top PMOS first pull-up transistor PU1 can be identified by its common gate G” ¶ [0050]; “two nano-sheets NS for the bottom NMOS pull-down transistors PD1 and PD2” ¶ [0084]);
a second channel region (nano-sheet region of PU1 in Figs. 4B, 5B and 15B) stacked above the first channel region (“nano-sheet stacked on nano-sheet.” ¶ [0038]); and
an inverter gate around the first channel region and the second channel region (“A vertical common gate between NMOS and PMOS in FIG. 1D” ¶ [0038]; “INV1, formed by the bottom NMOS first pull-down transistor PD1 and the top PMOS first pull-up transistor PU1 can be identified by its common gate G.” ¶ [0050]; “Each of the at least six transistors can be lateral gate-all-around transistors in that the gate wraps all around a cross section of channels of the at least six transistors.” ¶ [0006]),
CHANEMOUGAME et al. further discloses a conductive body located vertically above pass gate PG2, separated from PG2 by dielectric F5 and in contact with the gate of inverter INV1 (Figs. 9A-9C, 11D-11E, 13B-13E; “The fifth fill material F5, e.g., dielectric layer, ….acts as an etch stop layer” ¶ [0072]; “when the metal is dropped into the cavity, it connects together the source or drain of the second pass-gate PG2, the source or drain of each device of the second inverter INV2 and the gate of first inverter INV1” ¶ [0079])
However, CHANEMOUGAME et al. does not disclose, the conductive body above the pass gate is a portion of the inverter gate.
In the similar field of endeavor of random-access memory (SRAM) device, Smith et al. Figs. 1, 3 discloses an inverter gate, comprising a gate extension above the pass gate (“vertical portion 130b isolates the upper electrode from an extension portion 140 of the lower electrode. The extension portion 140 permits access to the lower electrode from a surface of the electrode region.” ¶ [0047]; “the lower electrode section 110 and gate extension 140 form a “step” shape,” ¶ [0047]; “control gate and pass gate both located within the same structure (gate, gate region, cell)” ¶ [0058]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the conductive body above the pass gate PG2 as an extension of the inverter gate of CHANEMOUGAME et al. with gate electrode with the extension portion 140 of Smith et al. in order to enable un-metalized wires within either NMOS or PMOS gate electrode, and the functionality of this process is to incorporate an in-situ cross-couple within a gate structures. Cross-couples, as used for the case of SRAM designs, function by taking the charge in a S/D bar and transferring it to the input to a control gate. This is typically done through a local interconnect layer, which leads to congestion for the case of a 3D SRAM device. Techniques herein, however, remove the need for the cross-couple to be routed through a local interconnect metal layer (Smith et al. ¶ [0058]) and incorporating self-alignment capability to enable significant area scaling benefit associated with stacking N-MOS and PMOS wires as complimentary stacking. Techniques include overlapping “stair-cased” or step-shaped gate electrodes. A repeatable process can be done to form an increasing “step-like” progression or configuration in the gate electrodes, where each step produces a self-aligned contact (Smith et al. ¶ [0035]).
Regarding Claim 2, CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 1. CHANEMOUGAME et al. 11E, 12-12E and 13B-13E further discloses, further comprising:
a second inverter INV2 (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]); and
a cross couple electrically connected between the gate extension and a source/drain (S/D) of the second inverter (“when the metal is dropped into the cavity, it connects together the source or drain of the second pass-gate PG2, the source or drain of each device of the second inverter INV2 and the gate of first inverter INV1, therefore effectively forming the cross-couple XC.” ¶ [0079]).
Regarding Claim 3, CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 2. CHANEMOUGAME et al. Figs. 4A, 4C and 5B further discloses, wherein the second inverter is oriented along a second line different from the first line (Figs. 4A, 4C and 5B shows INV1 and INV2 are along different lines; “Inside the bit cell boundaries, two horizontal nanosheet shapes (NS) can be seen representing the active layer or silicon channel, and two vertical shapes (PC) representing the gates.” ¶ [0049]; “Description herein will refer to the inverter on the left as INV1 and the inverter on the right as INV2” ¶ [0042).
Regarding Claim 4. CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 1. CHANEMOUGAME et al. Figs. 4A, 8B, 15B further discloses, wherein the first channel region comprises nanosheet layers (nano-sheet region of PD1 in Figs. 4A, 8B, 15B; “Each of the at least six transistors can be lateral transistors with channels formed from nano-sheets grown by epitaxy.” ¶ [0014]).
Regarding Claim 5. CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 1. CHANEMOUGAME et al. Figs. 5B, 7A-7C further discloses, wherein the inverter gate is confined laterally by a gate spacer (“Gate spacer GS may be between the first fill material F1 and the fourth fill material F4” ¶ [0058]; “the gate spacer GS and the oxide F4 exposed in the source and drain area are not etched due to the selectivity, making the etch self-aligned.” ¶ [0062]).
Regarding Claim 6. CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 1. CHANEMOUGAME et al. Figs. 5B, 7D-7E, 8E-8F further discloses, further comprising a separating insulator separating the inverter gate from the pass gate (“separation pillars SP” ¶ [0059]; “The shape of CT enables to form a pillar to separate the gate of the first inverter INV1 from inverters of adjacent cells INV1N but also from the gate of the second pass-gate PG2” ¶ [0063]; “the gates of the pass-gates, e.g., PG2, are vertically separated from the gates of the PMOS devices on top by the fifth fill material F5. The fifth fill material F5 may be dielectric material.” ¶ [0060]).
Regarding Claim 7. CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 6. CHANEMOUGAME et al. Figs. 5B, 8F further discloses, wherein the separating insulator (SP & F5) comprises a first vertical section (Lower portion of SP in Fig. 5B below F5), a first horizontal section (F5 in Fig 5B), and a second vertical section (Upper portion of SP in Fig. 5B above F5).
Regarding Independent Claim 14, CHANEMOUGAME et al. Figs. 1-15 discloses a semiconductor structure (“a CFET SRAM bit cell made with two stacked levels of transistors.” ¶ [0049]), comprising:
an inverter gate configured to activate an inverter gate transistor (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]);
a pass gate PG2 (“pass-gate (PG), e.g., PG1 and PG2” ¶ [0042]); and
a separating insulator between the inverter gate and the pass gate (“separation pillars SP” ¶ [0059]; “The shape of CT enables to form a pillar to separate the gate of the first inverter INV1 from inverters of adjacent cells INV1N but also from the gate of the second pass-gate PG2” ¶ [0063]; “the gates of the pass-gates, e.g., PG2, are vertically separated from the gates of the PMOS devices on top by the fifth fill material F5. The fifth fill material F5 may be dielectric material.” ¶ [0060]),
CHANEMOUGAME et al. further discloses a conductive body located vertically above pass gate PG2, separated from PG2 by dielectric F5 and in contact with the gate of inverter INV1 (Figs. 9A-9C, 11D-11E, 13B-13E; “The fifth fill material F5, e.g., dielectric layer, ….acts as an etch stop layer” ¶ [0072]; “when the metal is dropped into the cavity, it connects together the source or drain of the second pass-gate PG2, the source or drain of each device of the second inverter INV2 and the gate of first inverter INV1” ¶ [0079])
However, CHANEMOUGAME et al. does not disclose, the conductive body above the pass gate is a portion of the inverter gate.
In the similar field of endeavor of random-access memory (SRAM) device, Smith et al. Figs. 1, 3 discloses an inverter gate, comprising a gate extension above the pass gate (“vertical portion 130b isolates the upper electrode from an extension portion 140 of the lower electrode. The extension portion 140 permits access to the lower electrode from a surface of the electrode region.” ¶ [0047]; “the lower electrode section 110 and gate extension 140 form a “step” shape,” ¶ [0047]; “control gate and pass gate both located within the same structure (gate, gate region, cell)” ¶ [0058]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the conductive body above the pass gate PG2 as an extension of the inverter gate of CHANEMOUGAME et al. with gate electrode with the extension portion 140 of Smith et al. in order to enable un-metalized wires within either NMOS or PMOS gate electrode, and the functionality of this process is to incorporate an in-situ cross-couple within a gate structures. Cross-couples, as used for the case of SRAM designs, function by taking the charge in a S/D bar and transferring it to the input to a control gate. This is typically done through a local interconnect layer, which leads to congestion for the case of a 3D SRAM device. Techniques herein, however, remove the need for the cross-couple to be routed through a local interconnect metal layer (Smith et al. ¶ [0058]) and incorporating self-alignment capability to enable significant area scaling benefit associated with stacking N-MOS and PMOS wires as complimentary stacking. Techniques include overlapping “stair-cased” or step-shaped gate electrodes. A repeatable process can be done to form an increasing “step-like” progression or configuration in the gate electrodes, where each step produces a self-aligned contact (Smith et al. ¶ [0035]).
Regarding Claim 15, CHANEMOUGAME et al. as modified by Smith et al. disclose the limitations of claim 14. CHANEMOUGAME et al. 11E, 12-12E and 13B-13E further discloses, further comprising:
a second inverter INV2 (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]); and
a cross couple electrically connected between the gate extension and a source/drain (S/D) of the second inverter (“when the metal is dropped into the cavity, it connects together the source or drain of the second pass-gate PG2, the source or drain of each device of the second inverter INV2 and the gate of first inverter INV1, therefore effectively forming the cross-couple XC.” ¶ [0079]).
Regarding Claim 16, CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 15. CHANEMOUGAME et al. Figs. 4A, 4C and 5B further discloses, wherein the second inverter is oriented along a second line different from the first line (Figs. 4A, 4C and 5B shows INV1 and INV2 are along different lines; “Inside the bit cell boundaries, two horizontal nanosheet shapes (NS) can be seen representing the active layer or silicon channel, and two vertical shapes (PC) representing the gates.” ¶ [0049]; “Description herein will refer to the inverter on the left as INV1 and the inverter on the right as INV2” ¶ [0042).
Regarding Claim 17, CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 14. CHANEMOUGAME et al. Figs. 5B, 7A-7C further discloses, wherein the inverter gate is confined laterally by a gate spacer (“Gate spacer GS may be between the first fill material F1 and the fourth fill material F4” ¶ [0058]; “the gate spacer GS and the oxide F4 exposed in the source and drain area are not etched due to the selectivity, making the etch self-aligned.” ¶ [0062]).
Regarding Claim 18, CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 14. CHANEMOUGAME et al. fig 5B further discloses, wherein the separating insulator (SP & F5) comprises a first vertical section (Lower portion of SP in Fig. 5B below F5), a first horizontal section (F5 in Fig 5B), and a second vertical section (Upper portion of SP in Fig. 5B above F5).
Regarding Claim 19. CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 14. CHANEMOUGAME et al. fig 5B further discloses, wherein the inverter gate transistor (“form two inverters, e.g., INV1 and INV2, (NMOS and PMOS sharing a common gate)” ¶ [0042]) comprises a first channel region (nano-sheet region of PD1 in Figs. 4B & 15B; “the first inverter, e.g., INV1, formed by the bottom NMOS first pull-down transistor PD1 and the top PMOS first pull-up transistor PU1 can be identified by its common gate G” ¶ [0050]; “two nano-sheets NS for the bottom NMOS pull-down transistors PD1 and PD2” ¶ [0084]); a second channel region (nano-sheet region of PU1 in Figs. 4B, 5B and 15B) stacked above the first channel region (“nano-sheet stacked on nano-sheet.” ¶ [0038]).
Regarding Claim 20. CHANEMOUGAME et al. as modified by Smith et al. discloses the limitations of claim 19. CHANEMOUGAME et al. Figs. 4A-4B and 15B further discloses, wherein the first channel region comprises a pull-down transistor (“the NMOS of each inverter is called the pull-down (PD), e.g., PD1 and PD2” ¶ [0042]) and the second channel region comprises a pull up transistor (“The PMOS of each inverter is called the pull-up (PU), e.g., PU1 and PU2” ¶ [0042]).
Conclusion
The Prior arts (US 11349001 B2) “Xie et al.” filing date 2019-10-10; (US 10109637 B1) “Zang et al.” filing date 2017-12-28; made of record and not relied upon is considered pertinent to applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday - Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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