DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 03/10/2026 has been entered. Claims 17-18 are new.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 03/10/2026, have been fully considered, the arguments are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20110215400 A1 to Nakamura, being used in the current rejection, see detail below.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13 and 17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lane
et al. (US 7064442 B1, hereinafter Lane, of the record) in view of Nakamura et al. (US 20110215400 A1, hereinafter Nakamura).
Re: Independent Claim 1, Lane discloses a semiconductor device (in Col. 4, lines 10-13, Fig. 3) comprising:
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Lane’s Figure 3-Annotated.
a plurality of conductive members (portions of lead frame 320, 325, 330 in Col. 4, lines 19-25, Fig. 3-Annotated) including a first die pad (320-pad, 320-L1, 320-L2 in Col. 4, lines 19-25, Fig. 3-Annotated) and a second die pad (325-pad, 325-L1, 325-L2 in Col. 4, lines 19-25, Fig. 3-Annotated) that are spaced apart from each other (Fig. 3-Annotated);
a first semiconductor element (305 integrated circuit in Col. 4, lines 19-25, Fig. 3) mounted on the first die pad (320-pad, 320-L1, 320-L2, Fig. 3-Annotated);
a second semiconductor element (310 integrated circuit in Col. 4, lines 19-25, Fig. 3) mounted on the second die pad (325-pad, 325-L1, 325-L2, Fig. 3-Annotated); and
an insulator (315 transformer block in Col. 4, lines 19-25, Fig. 3) that is electrically connected (Fig. 3-Annotated) to the first semiconductor element (305, Fig. 3) and the second semiconductor element (310, Fig. 3), and that insulates (315 between 305 and 310, Fig. 3) the first semiconductor element (305, Fig. 3) and the second semiconductor element (310, Fig. 3) from each other (Fig. 3),
wherein the plurality of conductive members (portions of lead frame 320, 325, 330 Fig. 3) includes a third die pad (330-pad, 330-L1, 330-L2 in Col. 4, lines 19-25, Fig. 3-Annotated) spaced apart from the first die pad (320-pad, 320-L1, 320-L2, Fig. 3-Annotated) and the second die pad (325-pad, 325-L1, 325-L2, Fig. 3-Annotated), the insulator (315, Fig. 3) is mounted on the third die pad (330-pad, 330-L1, 330-L2, Fig. 3-Annotated),
the third die pad (330-pad, 330-L1, 330-L2, Fig. 3-Annotated) has a third pad portion (330-pad, Fig. 3-Annotated), on which the insulator (315, Fig. 3) is mounted, and two third suspending lead portions (330-L1, 330-L2, Fig. 3-Annotated), the third pad portion (330-pad, Fig. 3-Annotated) includes a first edge and a second edge that are opposite to each other (1-edge and 2-edge, Fig. 3-Annotated), the two third suspending lead portions (330-L1, 330-L2, Fig. 3-Annotated) are connected to and extend from the first edge and the second edge, respectively (1-edge and 2-edge, Fig. 3-Annotated).
Lane does not expressly disclose as viewed in a thickness direction of each of the first semiconductor element and the second semiconductor element, the two third suspending lead portions extend on and along a common straight line, and each of the two third suspending lead portions has a shape symmetrical with respect to the common straight line.
However, in the same semiconductor device field of endeavor, Nakamura discloses wherein two third suspending lead portions (DP2-B, DP2-T, portions of the die pad DP2 in [0074], Fig. 6-Annotated) extend on and along a common straight line (Fig. 6-Annotated), and each of the two third suspending lead portions (DP2-B, DP2-T) has a shape symmetrical (DP2-B, DP2-T are symmetrical, Fig. 6-Annotated) with respect to the common straight line.
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Nakamura’s Figure 6-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Nakamura’s feature of the two third suspending lead portions extend on and along a common straight line, and each of the two third suspending lead portions has a shape symmetrical with respect to the common straight line to Lane’s device to obtain as viewed in a thickness direction (Lane: z-direction, out of the page, Fig. 3-Annotated) of each of the first semiconductor element and the second semiconductor element, the two third suspending lead portions extend on and along a common straight line, and each of the two third suspending lead portions has a shape symmetrical with respect to the common straight line to provide a technology capable of improving the reliability of semiconductor devices ([0016], Nakamura).
Re: Claim 13, Lane modified by Nakamura discloses the semiconductor device according to claim 1, wherein the insulator (Lane: 315, Fig. 3) is of a type that is one of an inductive type (Lane: 315 is a transformer as an inductor, Fig. 3) and a capacitive type (Lane: a capacitance formed between each turn of the transformer 315, Fig. 3).
Re: Claim 17, Lane modified by Nakamura discloses the semiconductor device according to claim 1, wherein the first edge and the second edge (1-edge and 2-edge, Fig. 3-Annotated, Lane) are provided with no lead portions other than the two third suspending lead portions (330-L1, 330-L2, Fig. 3-Annotated, Lane).
Claim(s) 2-12 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lane in view of Nakamura and further in view of Matsubara et al. (US 20160307854 A1, hereinafter Matsubara, of the record).
Re: Claim 2, Lane modified by Nakamura discloses the semiconductor device according to claim 1,
Lane modified by Nakamura does not expressly disclose further comprising a sealing resin covering the first semiconductor element, the second semiconductor element, the insulator, and at least a portion of each of the plurality of conductive members.
However, in the same semiconductor device field of endeavor, Matsubara discloses a sealing resin (6 sealing resin in [0042], Fig.2-Annotated) covering the first semiconductor element (111 control element in [0040], Fig.2), the second semiconductor element (112 drive element in [0041], Fig.2), the insulator (Matsubara:12 insulating element in [0040], Fig.2), and at least a portion of each of the plurality of conductive members (Matsubara: lead section 511, a pad section 512, a lead section 521, a pad section 522, and a connecting section 524 in [0054, 0056], Fig.2).
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Matsubara’s Figure 2-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Matsubara’s feature of further comprising a sealing resin covering the first semiconductor element, the second semiconductor element, the insulator, and at least a portion of each of the plurality of conductive members to the combination of Lane and Nakamura to electrically isolate the electronic components ([0042], Matsubara).
Re: Claim 3, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 2, wherein the first die pad (Lane: 320-pad, 320-L1, 320-L2, Fig. 3-Annotated) and the second die pad (Lane: 325-pad, 325-L1, 325-L2, Fig. 3-Annotated) are spaced apart from each other in a first direction (Lane: x-direction, Fig. 3-Annotated) perpendicular to the thickness direction (Lane: z-direction, out of the page, Fig. 3-Annotated), and the third die pad (Lane: 330-pad, 330-L1, 330-L2, Fig. 3-Annotated) is located between the first die pad (Lane: 320-pad, 320-L1, 320-L2, Fig. 3-Annotated) and the second die pad (Lane: 325-pad, 325-L1, 325-L2, Fig. 3-Annotated) in the first direction (Lane: x-direction, Fig. 3-Annotated).
Re: Claim 4, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 3, wherein the plurality of conductive members (Lane: portions of lead frame 320, 325, 330 Fig. 3) includes: a plurality of first terminals (Lane:1-terminal, left connections, Fig. 3-Annotated) exposed from one side of the sealing resin (Matsubara’s 6 applied to Lane’s 1-terminal, Fig. 3-Annotated) in the first direction (Lane: x-direction, Fig. 3-Annotated), and a plurality of second terminals (Lane:2-terminal, right connections, Fig. 3-Annotated) exposed from another side of the sealing resin (Matsubara’s 6 applied to Lane’s 2-terminal, Fig. 3-Annotated) in the first direction (Lane: x-direction, Fig. 3-Annotated), the first semiconductor element (Lane:305, Fig. 3) is electrically connected to the plurality of first terminals (Lane:1-terminal, Fig. 3-Annotated), and the second semiconductor element (Lane:310, Fig. 3) is electrically connected to the plurality of second terminals (Lane:2-terminal, Fig. 3-Annotated).
Re: Claim 5, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 4, wherein the plurality of first terminals (Lane:1-terminal, Fig. 3-Annotated) and the plurality of second terminals (Lane:2-terminal, Fig. 3-Annotated) are aligned in a second direction (Lane: y-direction, Fig. 3-Annotated) perpendicular to both of the thickness direction (Lane: z-direction, out of the page, Fig. 3-Annotated) and the first direction (Lane: x-direction, Fig. 3-Annotated).
Re: Claim 6, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 5, wherein the first die pad (Lane:320-pad, 320-L1, 320-L2, Fig. 3-Annotated) has a first pad portion (Lane:320-pad, Fig. 3-Annotated), on which the first semiconductor element (Lane:305, Fig. 3) is mounted, and two first suspending lead portions connected (Lane:320-L1, 320-L2, Fig. 3-Annotated) to respective sides of the first pad portion (Lane:320-pad, Fig. 3-Annotated) in the second direction (Lane: y-direction, Fig. 3-Annotated), and the two first suspending lead portions (Lane:320-L1, 320-L2, Fig. 3-Annotated) are exposed from the one side of the sealing resin (Matsubara’s 6 applied to Lane’s 320-L1, 320-L2, Fig. 3-Annotated) in the first direction (Lane: x-direction, Fig. 3-Annotated).
Re: Claim 7, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 6, wherein the first semiconductor element (Lane:305, Fig. 3) is electrically connected (Fig. 3-Annotated) to at least one of the two first suspending lead portions (Lane:320-L1, 320-L2, Fig. 3-Annotated).
Re: Claim 8, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 6, wherein the second die pad (Lane:325-pad, 325-L1, 325-L2, Fig. 3-Annotated) has a second pad portion (Lane:325-pad, Fig. 3-Annotated), on which the second semiconductor element (Lane:310, Fig. 3) is mounted, and two second suspending lead portions (Lane:325-L1, 325-L2, Fig. 3-Annotated) connected to respective sides of the second pad portion (Lane:325-pad, Fig. 3-Annotated) in the second direction (Lane: y-direction, Fig. 3-Annotated), and the two second suspending lead portions (Lane:325-L1, 325-L2, Fig. 3-Annotated) are exposed from the other side of the sealing resin (Matsubara’s 6 applied to Lane’s 325-L1, 325-L2, Fig. 3-Annotated) in the first direction (Lane: x-direction, Fig. 3-Annotated).
Re: Claim 9, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 8, wherein the second semiconductor element (Lane:310, Fig. 3) is electrically connected (Fig. 3-Annotated, Lane) to at least one of the two second suspending lead portions (Lane:325-L1, 325-L2, Fig. 3-Annotated).
Re: Claim 10, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 8, wherein the first edge and the second edge (1-edge and 2-edge, Fig. 3-Annotated, Lane) are spaced apart from each other in the second direction (Lane: y-direction, Fig. 3-Annotated),
Lane modified by Nakamura and Matsubara does not expressly disclose the two third suspending lead portions are exposed from respective sides of the sealing resin in the second direction.
However, in the same semiconductor device field of endeavor, Lane discloses in a second embodiment, two third suspending lead portions (Lane:420-L1, 420-L2, Fig. 4-Annotated) extending in a second direction (Lane: y-direction, Fig. 4-Annotated).
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Lane’s Figure 4-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the combination of Lane, Nakamura and Matsubara structure having of two third suspending lead portions extending in a second direction according to the Lane’s second embodiment to obtain the two third suspending lead portions are exposed from respective sides of the sealing resin in the second direction to tune the electrical properties of the device (Col 4, lines 38-51, Lane).
Re: Claim 11, Lane modified by Nakamura, Matsubara and Lane’s second embodiment the semiconductor device according to claim 10, wherein the two third suspending lead portions (Lane’s second embodiment:420-L1, 420-L2, Fig. 4-Annotated) extend from the third pad portion (Lane’s second embodiment:420-pad, portion of 420 below transformer 435, Fig. 4-Annotated) in the second direction (Lane’s second embodiment: y-direction, Fig. 4-Annotated).
Re: Claim 12, Lane modified by Nakamura, Matsubara and Lane’s second embodiment the semiconductor device according to claim 11, wherein, as viewed in the first direction (Lane: x-direction, Fig. 4-Annotated), the third pad portion (Lane’s second embodiment: 420-pad, Fig. 4-Annotated) overlaps with the first pad portion (Lane’s second embodiment: 430-pad, Fig. 4-Annotated) and the second pad portion (Lane’s second embodiment:425-pad, Fig. 4-Annotated).
Re: Claim 18, Lane modified by Nakamura and Matsubara discloses the semiconductor device according to claim 4,
Lane modified by Nakamura and Matsubara does not expressly disclose wherein a creepage distance of the sealing resin from the two third suspending lead portions to the plurality of first terminals is equal to a creepage distance of the sealing resin from the two third suspending lead portions to the plurality of second terminals.
However, in the same semiconductor device field of endeavor, Lane discloses in a second embodiment (Fig. 4), a third die pad (420-pad, 420-L1, 420-L2, Fig. 4-Annotated) in the middle and between a first (425-pad, 425-L1, 425-L2, Fig. 4-Annotated) and a second (430-pad, 430-L1, 430-L2, Fig. 4-Annotated) die pads.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the combination of Lane, Nakamura and Matsubara structure having of a third die pad in the middle and between a first and second die pads according to the Lane’s second embodiment to tune the electrical properties of the device (Col 4, lines 38-51, Lane).
The combination of Lane, Nakamura, Matsubara and Lane’s second embodiment results in wherein a creepage distance of the sealing resin (Matsubara’s 6 applied to Lane, Fig. 4-Annotated) from the two third suspending lead portions (Nakamura’s DP2-B, DP2-T applied to Lane, Fig. 4-Annotated) to the plurality of first terminals (Lane:1-terminal, Fig. 4-Annotated) is equal to a creepage distance of the sealing resin from the two third suspending lead portions (Nakamura’s DP2-B, DP2-T applied to Lane, Fig. 4-Annotated) to the plurality of second terminals (Lane:2-terminal, Fig. 4-Annotated).
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Lane’s Figure 4-Annotated.
Claim(s) 14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lane in view of Nakamura and further in view of Parto (US 20170331371 A1, hereinafter Parto, of the record).
Re: Claim 14, Lane modified by Nakamura discloses the semiconductor device according to claim 13, wherein the insulator has a first transceiver (Lane:315-A upper transformer in Col. 4, lines 4-6, Fig. 3-Annotated) electrically connected to the first semiconductor element (Lane:305, Fig. 3), a second transceiver (Lane:315-B lower transformer in Col. 4, lines 4-6, Fig. 3-Annotated) electrically connected to the second semiconductor element (Lane:310, Fig. 3).
Lane modified by Nakamura does not expressly disclose a relay portion that transmits and receives signals between the first transceiver and the second transceiver, and in a thickness direction of the insulator, the relay portion is located closer to the third die pad than are the first transceiver and the second transceiver.
However, in the same semiconductor device field of endeavor, Parto discloses a relay portion (455 including a switch, [0115,0116], Fig. 4C) that transmits and receives signals (Parto: the switch couple to the inductor in [0116]) of an inductor (Parto: 453 including an inductor, [0115], Fig. 4C), and in a thickness direction of the inductor (Parto: 453 including an inductor, Fig. 4C), the relay portion (Parto:455 including a switch, Fig. 4C) is located closer to the packaging layer (Parto:457 including a packaging layer, [0115,0116], Fig. 4C) than the inductor (Parto: 453 including an inductor, Fig. 4C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Parto’s feature a relay portion that transmits and receives signals of an inductor, and in a thickness direction of the inductor, the relay portion is located closer to the packaging layer than the inductor to the Lane’s device to obtain a relay portion that transmits and receives signals between the first transceiver and the second transceiver, and in a thickness direction of the insulator, the relay portion is located closer to the third die pad than are the first transceiver and the second transceiver to reduce the footprint of a DC-DC converter ([0119], Parto).
Claim(s) 15 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lane in view of Nakamura, in view of Tanghe (US 20210167169 A1, hereinafter Tanghe, of the record) and further in view of Kaeriyama (US 20130055052 A1, hereinafter Kaeriyama, of the record).
Re: Claim 15, Lane modified by Nakamura discloses the semiconductor device according to claim 13,
Lane modified by Nakamura does not expressly disclose wherein the insulator includes a first insulating element and a second insulating element that are spaced apart from each other, the first insulating element has a first transceiver electrically connected to the first semiconductor element, and a second transceiver that transmits and receives signals to and from the first transceiver, the second insulating element has a third transceiver electrically connected to the second transceiver, and a fourth transceiver that transmits and receives signals to and from the third transceiver, and in a thickness direction of the insulator, the second transceiver and the third transceiver are located closer to the third die pad than are the first transceiver and the fourth transceiver.
However, in the same semiconductor device field of endeavor, Tanghe discloses an insulator including a first insulating element (108a a top isolator component, [0046], Fig. 4) and a second insulating element (112a a top isolator component, [0046], Fig. 4) that are spaced apart from each other (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tanghe’s feature wherein the insulator includes a first insulating element and a second insulating element that are spaced apart from each other to the combination of Lane and Nakamura to form a multi-channel isolator device ([0046], Tanghe).
Lane modified by Nakamura and Tanghe does not expressly disclose the first insulating element has a first transceiver electrically connected to the first semiconductor element, and a second transceiver that transmits and receives signals to and from the first transceiver, the second insulating element has a third transceiver electrically connected to the second transceiver, and a fourth transceiver that transmits and receives signals to and from the third transceiver, and in a thickness direction of the insulator, the second transceiver and the third transceiver are located closer to the third die pad than are the first transceiver and the fourth transceiver.
However, in the same semiconductor device field of endeavor, Kaeriyama discloses an insulating element (ISO1 isolation element, [0099], Fig. 31) having a first transceiver (L11 primary side coil, [0099], Fig. 31) electrically connected to the first semiconductor element (Kaeriyama:Tx1 primary side coil, [0097], Fig. 31), and a second transceiver (Kaeriyama:L12 secondary side coil, [0099], Fig. 31) that transmits and receives signals (Kaeriyama: transmitting an AC signal from the primary side coil L11 to the secondary side coil L12 in [0099]) to and from the first transceiver (Kaeriyama:L11, Fig. 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Kaeriyama’s feature wherein the first insulating element has a first transceiver electrically connected to the first semiconductor element, and a second transceiver that transmits and receives signals to and from the first transceiver to the combination of Lane, Nakamura and Tanghe to obtain the first insulating element has a first transceiver electrically connected to the first semiconductor element, and a second transceiver that transmits and receives signals to and from the first transceiver, the second insulating element has a third transceiver electrically connected to the second transceiver, and a fourth transceiver that transmits and receives signals to and from the third transceiver, and in a thickness direction of the insulator, the second transceiver and the third transceiver are located closer to the third die pad than are the first transceiver and the fourth transceiver to form an inductor type isolator ([0099], Kaeriyama).
Claim(s) 16 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Lane in view of Nakamura and further in view of Matsubara and further in view of Ye (US 10083895 B2, hereinafter Ye, of the record).
Re: Claim 16, Lane modified by Nakamura discloses the semiconductor device according to claim 1,
Lane modified by Nakamura does not expressly disclose further comprising a bonding layer provided between the third die pad and the insulator, and the bonding layer is electrically insulative.
However, in the same semiconductor device field of endeavor, Matsubara discloses a bonding layer (a bonding layer as adhesive to attach the internal plating 72 and the insulating element 12, [0040], Figs. 2, 7) provided between the third die pad (Matsubara: 21 die pad, [0040], Figs. 2, 7) and the insulator (Matsubara: 12 insulating element, [0040], Figs. 2, 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Matsubara feature of a bonding layer provided between the third die pad and the insulator to the combination of Lane and Nakamura device to attach the die pad with the electronic component ([0040], Matsubara).
Lane modified by Nakamura and Matsubara does not expressly disclose wherein the bonding layer is electrically insulative.
However, in the same semiconductor device field of endeavor, Ye discloses a bonding layer (107-108 Insulation adhesive layer, Col. 3, Line 56, Fig. 3A) is electrically insulative.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ye’s feature wherein the bonding layer is electrically insulative to the combination of Lane, Nakamura and Matsubara to attach the die pad with the electronic component (Col. 4, Line 11-13, 3895).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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