DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected electronic component package, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/09/2026.
Claim Objections
Claim 15 is objected to because of the following informalities:
The limitation “the photoresist” of claim 15 should read “the photoresist layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation "the aperture" in page 3 line 19 of the claims filed 01/03/2023. There is insufficient antecedent basis for this limitation in the claim.
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite since they depend upon and require all the limitations of claim 15.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri et al. (US 20220155109 A1; hereinafter Koduri) in view of Chan et al. (US 20200027834 A1; hereinafter Chan).
Regarding claim 7, FIGS. 1-14 of Koduri teach a method of forming an electronic component package (e.g. FIGS. 1-14 ¶ [0005]), the method comprising: forming a lead frame (900, 902 ¶ [0021]); forming an electronic circuit die (102) on the lead frame (900 ¶ [0014], see FIGS. 9A-9B); depositing a photoresist layer (400) on the electronic circuit die (102 ¶ [0017]), the photoresist layer (400) forming a loop-shaped cavity (500) that extends to a surface of the electronic circuit die (surface of 102 exposed by 500 and covered by 300 ¶ [0018]) and an indentation (indentation filled by 1405 ¶ [0027], see FIG. 14) about a periphery of the loop-shaped cavity (500) at the surface of the electronic circuit die (surface of 102); depositing a metal material (e.g. copper, nickel, aluminum) to fill the loop-shaped cavity (500) to form a metal plate structure (600 in FIGS. 5A-13/1405 in FIG. 14 ¶ [0019]), the metal plate structure (1405) comprising a foot portion (foot portion of 1405, see FIG. 14) that is contoured to fill the indentation in the photoresist layer (indentation filled by 1405 ¶ [0027], see FIG. 14); removing the photoresist layer (400) to provide an aperture (800 ¶ [0020]) that extends through the metal plate structure (600) from a first surface coupled to the electronic circuit die (first surface of 600 coupled to 102 via 300) to a second surface opposite the first surface (second surface of 600 facing away from top surface of 102, see FIGS. 7A-8B); and forming a molding material (1006) to cover the electronic circuit die (102) around the metal plate structure (600 ¶ [0022], see FIGS. 10-11B).
Koduri does not teach the metal plate structure comprising a tapered foot portion.
FIG. 4B of Chan teaches a metal plate structure (22) comprising a tapered foot portion (tapered inner wall of 22 ¶ [0050]-[0051]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the metal plate structure taught by Chan for the purpose of increasing the connection ability or flexibility (¶ [0040]).
Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri in view of Chan, and further in view of Park et al. (US 20150024327 A1; hereinafter Park).
Regarding claim 8, Koduri as modified teaches the method of claim 7.
Koduri as modified does not teach wherein the depositing the photoresist layer on the electronic circuit die comprises applying a photoresist material to the electronic circuit die via a spin coating process.
FIG. 1 of Park teaches a method of forming a metal structure (metal film formed via metal deposition in FIG. 1) on a substrate (substrate) comprising: depositing a photoresist layer (photoresist composition) on the substrate (substrate) via a spin coating process (¶ [0062]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the spin-coating process taught by Park for the purpose of creating a uniform photoresist layer with nanoscale thicknesses.
Regarding claim 9, Koduri as modified teaches the method of claim 7.
Koduri as modified does not teach wherein the forming the photoresist layer on the electronic circuit die comprises performing a soft bake process at approximately 130º C or less.
FIG. 1 of Park teaches a method of forming a metal structure (metal film formed via metal deposition in FIG. 1) on a substrate (substrate) comprising: depositing a photoresist layer with (photoresist composition) with a reverse taper profile on the substrate (substrate ¶ [0062]); wherein the forming the photoresist layer (photoresist composition) on the substrate (susbtrate) comprises performing a soft bake process at approximately 130º C or less (e.g. 80 to 120° C ¶ [0043]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the prebake process taught by Park for the purpose of optimizing the cross-linked structure and to help the photoresist pattern formed with a good reverse taper profile (¶ [0002],[0043]).
Regarding claim 11, Koduri as modified teaches the method of claim 7.
Koduri as modified does not teach wherein the forming the photoresist layer on the electronic circuit die comprises performing a post bake process at greater than approximately 100º C.
FIG. 1 of Park teaches a method of forming a metal structure (metal film formed via metal deposition in FIG. 1) on a substrate (substrate) comprising: depositing a photoresist layer with (photoresist composition) with a reverse taper profile on the substrate (substrate ¶ [0062]); wherein the forming the photoresist layer (photoresist composition) on the substrate (substrate) comprises performing a post bake process at grater than approximately 100° C (e.g. 90 to 150° C ¶ [0043]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the post exposure bake process taught by Park for the purpose of optimizing the cross-linked structure and to help the photoresist pattern formed with a good reverse taper profile (¶ [0002],[0043]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri in view of Chan, and further in view of Ishii et al. (US 20250375963 A1; hereinafter Ishii).
Regarding claim 10, Koduri as modified teaches the method of claim 7.
Koduri as modified does not teach wherein the forming the photoresist layer on the electronic circuit die comprises exposing the photoresist layer to ultraviolet light at a rate of at least approximately 1900 mJ/cm².
FIG. 2 of Ishii teaches a method of forming a photoresist (4) on a support (3), wherein the forming the photoresist layer (4) on the support (3) comprises exposing the photoresist layer (4) to ultraviolet light (¶ [0190]-[0191]) at a rate of at least approximately 1900 mJ/cm² (e.g. 2000 mJ/cm2 ¶ [0285]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the method of forming the photoresist taught by Ishii for the purpose of patterning the photoresist.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri in view of Tsou et al. (US 20220328312 A1; hereinafter Tsou).
Regarding claim 15, FIGS. 1-14 of Koduri teach a method of forming an electronic component package (e.g. FIGS. 1-14 ¶ [0005]), the method comprising: forming a lead frame (900, 902 ¶ [0021]); forming an electronic circuit die (102) on the lead frame (900 ¶ [0014], see FIGS. 9A-9B); forming a photoresist layer (400) on the electronic circuit die (102 ¶ [0017]), the photoresist layer (400) comprising a ring-shaped cavity (500) that extends through the photoresist layer (400) to a surface of the electronic circuit die (surface of 102 exposed by 500 and covered by 300 ¶ [0018]) and a first indentation (indentation filled by 1405 ¶ [0027], see FIG. 14) about an outer periphery of the ring-shaped cavity (500) at the surface of the electronic circuit die (surface of 102); depositing a metal material (e.g. copper, nickel, aluminum) in the ring-shaped cavity (500) to form a metal ring structure (600 in FIGS. 5A-13/1405 in FIG. 14 ¶ [0019]), the metal ring structure (1405) comprising a first foot section (foot section of 1405, see FIG. 14) that is contoured to fill the first indentation in the photoresist layer (indentation filled by 1405 ¶ [0027], see FIG. 14); removing the photoresist layer (400); and forming a molding material (1006) to cover the electronic circuit die (102) around the outer periphery of the ring structure (outer periphery of 600 ¶ [0022], see FIGS. 10-11B).
Koduri does not teach a second indentation about an inner periphery of the ring-shaped cavity.
FIGS. 10-11 of Tsou teach a method of forming a first indentation (first reverse tapered portion of P’) and a second indentation (second reverse tapered portion of P’) in a photoresist (P’) and depositing a metal material (M1) in the first and second indentations (see FIG. 11 ¶ [0043]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the method of forming the photoresist with reverse tapered indentations taught by Tsou for the purpose of easily lifting off the photoresist in later steps and avoiding the production of metal residue during lift off (¶ [0043]).
Claims 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Koduri in view of Tsou, and further in view of Park.
Regarding claim 16, Koduri as modified teaches the method of claim 15.
Koduri as modified does not teach wherein the depositing the photoresist layer on the electronic circuit die comprises applying a photoresist material to the electronic circuit die via a spin coating process.
FIG. 1 of Park teaches a method of forming a metal structure (metal film formed via metal deposition in FIG. 1) on a substrate (substrate) comprising: depositing a photoresist layer (photoresist composition) on the substrate (substrate) via a spin coating process (¶ [0062]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the spin-coating process taught by Park for the purpose of creating a uniform photoresist layer with nanoscale thicknesses.
Regarding claim 17, Koduri as modified teaches the method of claim 15.
Koduri as modified does not teach wherein the forming the photoresist layer on the electronic circuit die comprises performing a soft bake process at approximately 130º C or less.
FIG. 1 of Park teaches a method of forming a metal structure (metal film formed via metal deposition in FIG. 1) on a substrate (substrate) comprising: depositing a photoresist layer with (photoresist composition) with a reverse taper profile on the substrate (substrate ¶ [0062]); wherein the forming the photoresist layer (photoresist composition) on the substrate (susbtrate) comprises performing a soft bake process at approximately 130º C or less (e.g. 80 to 120° C ¶ [0043]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the prebake process taught by Park for the purpose of optimizing the cross-linked structure and to help the photoresist pattern formed with a good reverse taper profile (¶ [0002],[0043]).
Regarding claim 19, Koduri as modified teaches the method of claim 15.
Koduri as modified does not teach wherein the forming the photoresist layer on the electronic circuit die comprises performing a post bake process at greater than approximately 100º C.
FIG. 1 of Park teaches a method of forming a metal structure (metal film formed via metal deposition in FIG. 1) on a substrate (substrate) comprising: depositing a photoresist layer with (photoresist composition) with a reverse taper profile on the substrate (substrate ¶ [0062]); wherein the forming the photoresist layer (photoresist composition) on the substrate (substrate) comprises performing a post bake process at greater than approximately 100° C (e.g. 90 to 150° C ¶ [0043]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the post exposure bake process taught by Park for the purpose of optimizing the cross-linked structure and to help the photoresist pattern formed with a good reverse taper profile (¶ [0002],[0043]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Koduri in view of Tsou, and further in view of Ishii.
Regarding claim 18, Koduri as modified teaches the method of claim 15.
Koduri as modified does not teach wherein the forming the photoresist layer on the electronic circuit die comprises exposing the photoresist layer to ultraviolet light at a rate of at least approximately 1900 mJ/cm².
FIG. 2 of Ishii teaches a method of forming a photoresist (4) on a support (3), wherein the forming the photoresist layer (4) on the support (3) comprises exposing the photoresist layer (4) to ultraviolet light (¶ [0190]-[0191]) at a rate of at least approximately 1900 mJ/cm² (e.g. 2000 mJ/cm2 ¶ [0285]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming an electronic component package taught by Koduri with the method of forming the photoresist taught by Ishii for the purpose of patterning the photoresist.
Allowable Subject Matter
Claims 12-14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 12 recites the method of claim 7, wherein depositing the metal layer to fill the aperture comprises depositing a metal material in each of a first set of nine or fewer puddling procedures to form a first portion of the metal layer and depositing the metal material in each of a second set of at least two puddling procedures to form the tapered foot portions of the metal layer.
Koduri in view of Chan teaches the method of claim 7.
However, the prior art fails to teach or reasonably suggest “wherein depositing the metal layer to fill the aperture comprises depositing a metal material in each of a first set of nine or fewer puddling procedures to form a first portion of the metal layer and depositing the metal material in each of a second set of at least two puddling procedures to form the tapered foot portions of the metal layer” together with all the limitations of claims 7 and 12 as claimed.
Claim 13 recites the method of claim 7, wherein depositing the photoresist layer comprises forming grooves in the indentation, wherein depositing the metal layer comprises depositing the metal layer to fill the grooves of the indentation.
Koduri in view of Chan teaches the method of claim 7.
However, the prior art fails to teach or reasonably suggest “wherein depositing the photoresist layer comprises forming grooves in the indentation, wherein depositing the metal layer comprises depositing the metal layer to fill the grooves of the indentation” together with all the limitations of claims 7 and 13 as claimed.
Claim 14 recites the method of claim 7, wherein depositing the photoresist comprises forming the indentation between approximately 15% and approximately 25% of an inner radius of the aperture of the metal plate structure.
Koduri in view of Chan teaches the method of claim 7.
However, the prior art fails to teach or reasonably suggest “wherein depositing the photoresist comprises forming the indentation between approximately 15% and approximately 25% of an inner radius of the aperture of the metal plate structure” together with all the limitations of claims 7 and 14 as claimed.
Claim 20 recites the method of claim 15, wherein depositing the metal layer to fill the ring-shaped cavity comprises depositing a metal material in each of a first set of nine or fewer puddling procedures to form a first portion of the metal layer and depositing the metal material in each of a second set of at least two puddling procedures to form the tapered foot portions of the metal layer.
Koduri in view of Tsou teaches the method of claim 15.
However, the prior art fails to teach or reasonably suggest “wherein depositing the metal layer to fill the ring-shaped cavity comprises depositing a metal material in each of a first set of nine or fewer puddling procedures to form a first portion of the metal layer and depositing the metal material in each of a second set of at least two puddling procedures to form the tapered foot portions of the metal layer” together with all the limitations of claims 15 and 20 as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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