DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 01/05/2026. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 11/09/2023.
Oath/Declaration
The oath or declaration filed on 09/26/2023 is acceptable.
Election/Restrictions
Applicant’s election of invention I, species I (Fig 1): claims 1-2 and 6-7 in the reply filed on 01/05/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)). The election is without traverse because the response is incomplete.
This office action considers claims 1-20 pending for prosecution, wherein claims 3-5 and 8-20 are withdrawn from further consideration, and 1-2 and 6-7 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SAWATARI et al (US 2014/0126157 A1; hereafter SAWATARI).
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Regarding claim 1. SAWATARI discloses an electronic component package comprising:
a wiring board (Fig. [2], “At an upper surface of the insulation layer 11f, four T type conductor vias 11m are disposed penetrating through the insulation layer 11f”, construed as wiring board 11f, Para [ 0035]) including a first principal surface and a second principal surface facing each other (Fig. [2], insulation layer 11f upper/lower surface, Para [ 0035]);
an electronic component (components 12 is an electronic component, Para [ 0050]) mounted on the first principal surface (Fig. [2], insulation layer 11f upper surface, Para [ 0035]);
a sealing member (sealing portion 13, Para [ 0032]) provided on the first principal surface for covering the electronic component (components 12 is an electronic component, Para [ 0050]); and
a shield film (shield 14, Para [ 0032]) provided on a surface of the sealing member (sealing portion 13, Para [ 0032]), wherein the wiring board (Fig. [2], insulation layer 11f upper/lower surface, Para [ 0035]) is provided with a plurality of through holes (Para [ 0035]) between the first principal surface and the second principal surface (Fig. [2], insulation layer 11f upper/lower surface, Para [ 0035]), an electronic component (components 12 is an electronic component, Para [ 0050]) including a columnar terminal (T type conductor vias 11m, Para [ 0035]) is mounted on the first principal surface (Fig. [2], insulation layer 11f upper surface, Para [ 0035]), and the columnar terminal (T type conductor vias 11m, Para [ 0035]) is inserted into at least one of the through holes from the first principal surface and is exposed on a side of the second principal surface (Fig. [2], insulation layer 11f upper/lower surface, Para [ 0035]).
Regarding claim 2. SAWATARI discloses the electronic component package according to claim 1, SAWATARI further discloses wherein the wiring board (Fig. [2], insulation layer 11f, Para [ 0035]) is provided with a plurality of conductor vias between the first principal surface and the second principal surface (Fig. [2], insulation layer 11f upper/lower surface, Para [ 0035]), an electronic component (components 12 is an electronic component, Para [ 0050]) including a planar terminal ( T type via 11m upper/ lower portion, Para [ 0035]) is mounted on the first principal surface (Fig. [2], insulation layer 11f upper surface, Para [ 0035]), and the planar terminal ( T type via 11m upper/ lower portion, Para [ 0035]) is directly connected to at least one of the conductor vias ( T type via 11m upper/ lower portion, Para [ 0035]).
Regarding claim 6. SAWATARI discloses the electronic component package according to claim 1, SAWATARI further discloses wherein a shield connection land (core layer 11a is made of a metal such as copper and a copper, construed as shield connection land, Para [ 0038]) connected to the shield film (shield 14, Para [ 0032]) is provided on the second principal surface (Fig. [2], insulation layer 11f lower surface, Para [ 0035]).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 7. The electronic component package according to claim 6, wherein the shield connection land is coupled to a ground land to which a ground terminal of the electronic component is connected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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