DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities:
Claim 8 recites “…before the step of laminating a plain protective film…” in lines 2-3 (emphasis added). Claim 1 depends from claim 1, which recites “a plain protective film” in line 2. Since it appears that the plain protective film of claim 8 is referring to the plain protective film of claim 1, the Examiner suggests the following amendment:
8. The process according to claim 1, wherein the front surface of the wafer comprises a cavity, optionally extending to the back surface, before the step of laminating [[a]] the plain protective film on the front surface of the wafer.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-7 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (PG Pub. No. US 2016/0023436 A1).
Regarding claim 1, Liu teaches a temporary wafer bonding process comprising the steps of:
providing a wafer (¶ 0021: substrate 12) for back processing (¶ 0033: backside processing) by laminating a plain protective film (¶ 0021: layer 20) on a front surface of the wafer (fig. 1a: 20 laminated on front surface 14);
providing a rigid carrier (¶ 0024: second substrate 24);
bonding the rigid carrier to the plain protective film by an intermediate of a bonding material layer (¶ 0031 & fig. 1b: 24 bonded to 20 by intermediate material layer 32);
processing a back surface of the wafer (¶ 0033: backside surface 16 processed); and
separating the rigid carrier and the plain protective film from the wafer (¶ 0035: 24 and 20 separated from 12).
Regarding claim 2, Liu teaches the process according to claim 1 wherein the step of separating the rigid carrier and the plain protective film from the wafer comprises:
separating the rigid carrier from the plain protective film (¶ 0035: 24 separated from 12); and
followed by removing the plain protective film from the front surface of the wafer (¶ 0035: remaining portion of 20 removed from 12).
Regarding claim 5, Liu teaches the process according to claim 1, wherein the wafer is a semiconductor substrate (¶ 0020), optionally comprising CMOS circuitry (optional feature, not given patentable weight).
Regarding claim 6, Liu teaches the process according to claim 1, wherein the rigid carrier is transparent (¶ 0024: 24 comprises glass).
Regarding claim 7, Liu teaches the process according to claim 1, wherein the rigid carrier is a glass carrier (¶ 0024: 24 comprises glass).
Regarding claim 12, Liu teaches the process according to claim 1, wherein the plain protective film either is glue- free (¶ 0039) or comprises a glue layer thinner than 5nm on the surface of the plain protective film that will contact the front surface of the wafer during the step of laminating the plain protective film on the front surface of the wafer.
Regarding claim 13, Liu teaches the process according to claim 1, wherein the bonding material layer comprises photosensitive material (¶ 0041: release layer is photosensitive).
Regarding claim 14, Liu teaches the process according to claim 13, wherein the step of separating the rigid carrier and the plain protective film from the wafer comprises a step of exposing the wafer to UV light (¶ 0034: excimer lasers at 248 nm, 308 nm, and 355 nm dissolve layer32).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Holsteyns et al. (PG Pub. No. US 2021/0098299 A1).
Regarding claim 3, Liu teaches the process according to claim 1, comprising a step of separating the rigid carrier and the plain protective film from the wafer (¶ 0035: 24 and 20 separated from 12).
Liu does not teach wherein the step of separating the rigid carrier and the plain protective film from the wafer comprises wet etching the plain protective film.
Holsteyns teaches a method including separating a rigid carrier (¶ 0051: 158) and a plain protective film (¶ 0052: 154) from a wafer (¶ 0040: 102) by a wet etch (¶ 0061 & fig. 11: 158/154 removed from 102 by a wet etch process).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Liu with the wet etch of Holsteyns, as a means to remove a plurality of back-side-processed wafer portions into a plurality of die, enhancing manufacturing efficiency.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the wet etch process of Holsteyns could be combined with the protective layer removal of Liu, with no change to their respective functions.
Regarding claim 8, Liu teaches the process according to claim 1, comprising a front surface of the wafer (¶ 0020: 12 includes front surface 14).
Liu does not teach wherein the front surface of the wafer comprises a cavity, optionally extending to the back surface, before the step of laminating a plain protective film (Examiner’s note: interpreted to mean “the” protective film of claim 1) on the front surface of the wafer.
Holsteyns teaches a method including laminating a plain protective film (¶ 0052: 154) on the front surface of a wafer (¶ 0052 & fig. 6a: 154 laminated on front surface of wafer 102) wherein the front surface of the wafer comprises a cavity (¶ 0049 & fig. 6A: front surface of 102 includes trenches 140a-140c).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of Liu with the cavity of Holsteyns, as a means to dice the semiconductor substrate into a plurality of dies, enhancing manufacturing efficiency.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02. In the instant case, the cavities of Holsteyns could be combined with the protective layer application of Liu, with no change to their respective functions.
Regarding claim 9, Liu in view of Holsteyns teaches the process according to claim 8, wherein the cavity has an aspect ratio of at least 1 (Holsteyns, fig. 4A among others: 140a-140c have height dimension greater than width dimension, meeting the broadest reasonable interpretation of “an aspect ratio of at least 1”).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Gao et al. (PG Pub. No. US 2022/0208650 A1).
Regarding claim 4, Liu teaches the process according to claim 1, wherein the step of processing a back surface of the wafer comprises a heating step of the back surface (¶ 0033: backside processing includes annealing).
Liu does not explicitly teach the heating step includes temperatures above 150 °C.
However, Liu does teach the protective film is utilized to form backside dielectric layers, and configured to survive processing temperatures above 200 °C (¶ 0033).
Gao teaches a method including form backside dielectric layers at temperatures above 150 °C (¶ 0037).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the step of processing the back surface of the wafer to comprise a heating step with temperatures above 150 °C, as a means to improve backside dielectric layer quality (Gao, ¶ 0039).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Lee et al. (PG Pub. No. US 2018/0358258 A1).
Regarding claim 10, Liu teaches the process according to claim 1, wherein the wafer comprises a stack of layers (¶ 0020: 12 comprises a plurality of layers),
Liu does not teach wherein at least one of the layers is formed by wafer bonding.
Lee teaches a wafer (¶ 0015: 105) comprising a stack of layers (¶ 0015: 105a/105b/105c), wherein at least one of the layers is formed by wafer bonding (¶ 0002: at least an active layer portion formed on a handle layer portion by wafer bonding).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the wafer of Liu by wafer bonding, as a means to achieve thinner and precise device layer and ensure the requirement of thickness uniformity and low defect density (Lee, ¶ 0002).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Tsuchiyama et al. (PG Pub. No. US 2013/0244402 A1).
Regarding claim 11, Liu teaches the process according to claim 1 wherein the plain protective film comprises a polymer (¶ 0039: 20 comprises a polymer).
Liu does not teach wherein the polymer has a glass transition temperature below 100 °C.
Tsuchiyama teaches an adhesive polymer film (¶ 0027: adhesive layer comprising polymer) with a glass transition temperature below 100 °C (¶ 0028: Tg preferably below 50 °C).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the polymer of Liu with a glass transition temperature below 100 °C, as a means to optimize adhesive force of the polymer film to a support (Tsuchiyama, ¶¶ 0028-0028).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liu as applied to claim 1 above, and further in view of Takahashi et al. (PG Pub. No. US 2014/0084491 A1).
Regarding claim 15, Liu teaches the process according to claim 13, including a step of laminating the plain protective film on the front surface of the wafer (fig. 1a).
Liu does not teach wherein the step of laminating the plain protective film on the front surface of the wafer is performed at a temperature above 85 °C and a pressure above 103 kPa.
Takahashi teaches a method including a step of laminating an adhesive film (¶ 0029: 1) on a substrate (fig. 3A: 1 laminated on substrate 21), the laminating performed at a temperature above 80 °C and a pressure of above 103 kPa (¶ 0029: 1 laminated on 21 at a temperature above 80 °C and a pressure of 0.5 MPa or higher).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the laminating process of Liu, including temperature and pressure, as a means to allow successful lamination without forming voids (Takahashi, ¶ 0029).
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed ranges of “a temperature above 85 °C and a pressure above 103 kPa” lie inside the ranges disclosed by Takahashi (temperature above 80 °C and pressure above 0.5 MPa).
Conclusion
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/BRIAN TURNER/ Examiner, Art Unit 2818
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