Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/474,872 filed on January 21, 2026.
Election/Restrictions
Applicant’s election without traverse of claims 1-11, 14, 20 drawn to device claims, Group I and Species I (Fig. 2A), in the reply filed on 01/21/2026 is acknowledged.
Claims 12-13, 15-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected method and species claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/21/2026.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1-3, 14, 20 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Shivaraman et al. (US 2023/0101111 A1).
Regarding independent claim 1, Shivaraman et al. teaches a semiconductor device (Figs. 1A-1- 3), comprising a first semiconductor structure (100), wherein the first semiconductor structure (100, para [0021]) comprises:
a first select transistor (130, para [0022]) comprising a first channel layer;
a second select transistor (140, para [0022]) comprising a gate; and
a capacitor structure (120, para [0021]) comprising a first electrode layer, wherein (see Fig. 1B below) two ends of the first electrode layer are connected with the gate of the second select transistor (140) and the first channel layer of the first select transistor (130), respectively.
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Regarding claim 2, Shivaraman et al. teaches wherein (Figs. 1A-1-3), the first select transistor (130, para [0022]) is configured to be turned on or not turned on according to writing content and allows a writing voltage to flow into the capacitor structure (120, para [0021]) through the first select transistor (130) (this is a functional limitation/an intended use), and the second select transistor (140, para [0022]) is configured to be turned on or not turned on according to storage content of the capacitor structure (120) and allows the storage content of the capacitor structure (120) to be read (this is a functional limitation/an intended use).
Regarding claim 3, Shivaraman et al. teaches wherein (Figs. 1A-1-3), the first semiconductor structure (100) further comprises:
a first stack structure (see the annotated figure below) having a first side (bottom side) and a second side (upper side) disposed oppositely in a first direction (vertical or Y- direction), wherein the capacitor structure (120) is located in the first stack structure;
a second stack structure (see the annotated figure below) located on the first side (bottom side) of the first stack structure, wherein the first select transistor (130) is located in the second stack structure; and
a third stack structure (see the annotated figure below) located on the second side (upper side) of the first stack structure, wherein the second select transistor (140) is located in the third stack structure.
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Regarding claim 14, Shivaraman et al. teaches wherein (3), further comprising a second semiconductor structure (304, para [0048]) that has a circuit element for controlling the first semiconductor structure (302) and is located on a side of the first semiconductor structure (302), wherein the second semiconductor structure (304) is connected with the first semiconductor structure (302) in the first direction by bonding (306 BGA, para [0048]).
Regarding claim 20, Shivaraman et al. teaches a memory system (Figs. 1A-1-2), comprising:
at least a semiconductor device comprising a first semiconductor structure (100), wherein the first semiconductor structure (100, para [0021]) comprises:
a first select transistor (130, para [0022]) comprising a first channel layer;
a second select transistor (140, para [0022]) comprising a gate; and
a capacitor structure (120, para [0021]) comprising a first electrode layer, wherein (see Fig. 1B below) two ends of the first electrode layer are connected with the gate of the second select transistor (140) and the first channel layer of the first select transistor (130), respectively; and
a controller (204, see Fig. 2) configured to control the semiconductor device (this is a functional limitation/an intended use).
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Allowable Subject Matter
8. Claim 4 (claims 5-11 depend on the claim 4) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. Claim 4: the prior art of record alone or in combination neither teaches nor makes obvious a semiconductor device, comprising:
Claim 4 recites…. the first stack structure comprises:
second electrode layer layers;
a plurality of first insulation layers, wherein any one of the second electrode layers is located between two adjacent ones of the first insulation layers; and
a plurality of first channel structures located in a deck formed by the second electrode layers and the first insulation layers along the first direction,
wherein each of the first channel structures comprises:
the first electrode layer extending in the first direction; and
an energy storage layer extending in the first direction and located between the second electrode layers and the first electrode layer,
wherein the second electrode layers and the first insulation layers are disposed around the energy storage layer, the energy storage layer is disposed around the first electrode layer, and the capacitor structure comprises the second electrode layers, the energy storage layer, and the first electrode layer.
10. The prior art, Shivaraman et al. (US 2023/0101111 A1) does not describe different layers in the first stack structure as stated in claim 4. Therefore, none of the prior art of references quoted in PTO-892, or in combination discloses the limitations quoted above.
Examiner’s Note
11. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
13. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812