DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (CN 114551241) in view of Lan et al. (CN 115064523).
Regarding claim 1, Sun teaches a semiconductor device, comprising:
a first region that comprises a semiconductor pillar array (see Fig. 6C, semiconductor pillars 601), wherein the semiconductor pillar array comprises semiconductor pillars that are arranged in an array along a first direction and a second direction (X and Y directions shown in Fig. 6C) and extend in a third direction (Z direction shown in Fig. 7), and the first direction, the second direction, and the third direction intersect each other (X, Y and Z directions); and
gate structures (Fig. 7, gate 707) and shielding structures (shield 708) extending along the first direction (see Fig. 8), wherein the gate structures and the shielding structures are in a staggered distribution along the second direction (see Fig. 8), and the semiconductor pillars are located between adjacent ones of the shielding structures and the gate structures (Fig. 8),
and orthographic projections of the gate structures are within ranges of orthographic projections of the shielding structures along the second direction (see Fig. 7 and 8).
Sun does not teach wherein sizes of the gate structures along the first direction are smaller than sizes of the shielding structures along the first direction. However, Lan teaches that the gate can be shorter than the shield (see Lan Fig. 2C). It would have been obvious to a person of skill in the art at the time of the effective filing date that the gate could have been shorter than the shield because Sun only teaches that the two should not be the same length, in order to avoid crowding at the terminal connection (Sun translation page 14), and Lan teaches that one way for them to not to be the same length is the shield longer than the gate (Lan Fig. 2C), which is one of only two possible options, with Sun choosing gate longer than shield and Lan choosing shield longer than gate, it would have been obvious to a person of skill in the art to try the other of two possible options.
Regarding claim 2, Sun in view of Lan teaches the semiconductor device of claim 1, wherein sizes of the gate structures along the third direction are greater than sizes of the shielding structures along the third direction (Sun Fig. 7), and
the orthographic projections of the gate structures are within the ranges of the orthographic projections of the shielding structures along the second direction (Sun Fig. 7 and 8).
Regarding claim 3, Sun in view of Lan teaches the semiconductor device of claim 1, further comprising a second region (Fig. 8, region at 801), wherein the second region and the first region are arranged along the first direction (X direction). Sun teaches a connector region, but does not teach specifics of the connector region.
Lan teaches the second region comprises a first conductive portion (Lan Fig. 5H, conductive portion 25) that comprises a first leading-out structure (Lan Fig. 5I, leading out structure 31) extending along the third direction and a first connector (connector 32) extending along the first direction (Fig. 5H-I),
two ends of the first leading-out structure along the third direction are in contact connection with the first connector and the gate structures respectively (see Fig. 5H), and
the first conductive portion is located on a side of the shielding structures along the third direction (Fig. 5I). It would have been obvious to a person of skill in the art at the time of the effective filing date that the connector of Sun could have been replaced by the connector of Lan because Lan teaches that positioning the conductive portion above and to the side of the transistor array reduces electric interference (Lan translation page 33).
Regarding claim 17, Sun in view of Lan teaches the semiconductor device of claim 1, wherein the gate structures comprise a first gate and a second gate that are adjacent in the second direction (see Sun Fig. 7-8), wherein the first gate and the second gate are respectively located on a side of the semiconductor pillars adjacent thereto (see Sun Fig. 7-8).
Regarding claim 20, Sun teaches a memory system, comprising:
a three-dimensional memory (Fig. 7-8) comprising one or more semiconductor devices comprising:
a first region (se Fig. 7-8) that comprises a semiconductor pillar array (Fig. 7-8, pillars 701), wherein the semiconductor pillar array comprises a plurality of semiconductor pillars that are arranged in an array along a first direction (X direction) and a second direction (Y direction) and extend in a third direction (Z direction), and the first direction, the second directions and the third direction intersect each other (Fig. 7-8); and
a plurality of gate structures (gate 707) and shielding structures (708) extending along the first direction (see Fig. 9), wherein the gate structures and the shielding structures are in a staggered distribution along the second direction (Fig. 9), and the plurality of semiconductor pillars are located between the shielding structures and the gate structures that are adjacent (Fig. 9),
wherein orthographic projections of the gate structures are within ranges of orthographic projections of the shielding structures along the second direction (Fig. 7 and 9); and
a memory controller coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data (it is inherent that a controller of some sort is paired with the cells in order to operate the memory).
Sun does not teach wherein sizes of the gate structures along the first direction are smaller than sizes of the shielding structures along the first direction. However, Lan teaches that the gate can be shorter than the shield (see Lan Fig. 2C). It would have been obvious to a person of skill in the art at the time of the effective filing date that the gate could have been shorter than the shield because Sun only teaches that the two should not be the same length, in order to avoid crowding at the terminal connection (Sun translation page 14), and Lan teaches that one way for them to not to be the same length is the shield longer than the gate (Lan Fig. 2C), which is one of only two possible options, with Sun choosing gate longer than shield and Lan choosing shield longer than gate, it would have been obvious to a person of skill in the art to try the other of two possible options.
Allowable Subject Matter
Claims 4-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4-16, the prior art, alone or in combination, fails to teach or suggest the gate structures in the two adjacent first regions are connected through first conductive portions, in combination with the other limitations of the claims.
Conclusion
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899
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